JPS63255926A - Hybrid integrated circuit device containing photodetector - Google Patents
Hybrid integrated circuit device containing photodetectorInfo
- Publication number
- JPS63255926A JPS63255926A JP62091156A JP9115687A JPS63255926A JP S63255926 A JPS63255926 A JP S63255926A JP 62091156 A JP62091156 A JP 62091156A JP 9115687 A JP9115687 A JP 9115687A JP S63255926 A JPS63255926 A JP S63255926A
- Authority
- JP
- Japan
- Prior art keywords
- light
- photodetector
- sealed
- face
- filter resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 abstract 3
- 239000000919 ceramic Substances 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、受光動作型混成集積回路装置の構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a light-receiving type hybrid integrated circuit device.
従来、この種の混成集積回路装置は、第３図に示すよう
に受光素子３とそれ以外の半導体素子４をともにセラミ
ック基板１に対してフェイスアップボンディングした後
、受光素子３のみを透光性フィルタ樹脂６で封止しＪ他
の半導体素子４を遮光性樹脂７で封止した構造、あるい
は第４図に示すように、受光素子３以外の半導体素子４
をフェイスアップボンデインクして遮光性樹脂７で封止
した基板１に、予め透光性フィルタ樹脂６にてトランス
ファモールド成形封止した受光素子３を半田付搭載した
構造を有していた。Conventionally, in this type of hybrid integrated circuit device, as shown in FIG. 3, after both the light receiving element 3 and other semiconductor elements 4 are face-up bonded to the ceramic substrate 1, only the light receiving element 3 is bonded to a light-transmitting element. A structure in which the semiconductor element 4 is sealed with a filter resin 6 and another semiconductor element 4 is sealed with a light-shielding resin 7, or as shown in FIG.
It had a structure in which a light-receiving element 3, which had been previously transfer-molded and sealed with a light-transmitting filter resin 6, was mounted by soldering on a substrate 1 which was face-up bonded and sealed with a light-shielding resin 7.
上述した従来の受光動作型混成集積回路装置は、受光素
子のみを透光性フィルター樹脂で封止し、他の半導体素
子を遮光性樹脂で封止するため、少なくとも二種類の封
止樹脂を必要とじ封止作業が複雑になり、作業効率が悪
いという欠点を有する。In the conventional light-receiving hybrid integrated circuit device described above, only the light-receiving element is sealed with a light-transmitting filter resin, and the other semiconductor elements are sealed with a light-blocking resin, so at least two types of sealing resin are required. This method has the disadvantage that the binding and sealing work becomes complicated and work efficiency is poor.
本発明は受光素子とこれ以外の半導体素子を所望の回路
配線を施した絶縁基板に搭載した受光動作型混成集積回
路装置において、基板面に対し受光素子をフェイスアッ
プボンディングし、他の半導体素子を照射光の影響を避
けるべくフェイスダウンボンディングし、これらの受光
素子と半導体素子とを一種類の透光性フィルタ樹脂で封
止したことを特徴とする。The present invention provides a light-receiving hybrid integrated circuit device in which a light-receiving element and other semiconductor elements are mounted on an insulating substrate with desired circuit wiring, in which the light-receiving element is face-up bonded to the substrate surface and other semiconductor elements are bonded to the substrate surface. It is characterized by face-down bonding to avoid the influence of irradiation light, and these light receiving elements and semiconductor elements are sealed with one type of light-transmitting filter resin.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の縦断面図である。セラ
ミック基板１上にはＡｇ−ＰｄまたはＡｕペースト等を
スクリーン印刷して回路配線導体２が形成されている。FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. Circuit wiring conductors 2 are formed on the ceramic substrate 1 by screen printing Ag-Pd or Au paste.
受光素子３がその受光面をフェイスアップして回路配線
導体２にダイボンディングされ、受光面側はボンディン
グワイヤ５によってワイヤポンディグされている。受光
素子３の信号を処理するための半導体素子４は受光素子
に照射される光よる影響を避けるように、その機能素子
形成面をフェイスダウンさせてフィンガーリード９にボ
ンディングされている。これら受光素子３および半導体
素子４の全体は、受光素子の動作帯域内の波長の光のみ
を透過し、それ以外の波長の光を遮断する透光性フィル
タ樹脂６によって封止されている。透光性フィルタ樹脂
６はエポキシ樹脂に光吸収顔料をブレンドしたものであ
る。かかる受光装置構造において、半導体素子４の機能
素子面に照射される光の経路としては、セラミック基板
１を透過する経路と樹脂６及び半導体素子４のＳｉ単結
晶サブストレートを透過する経路があるが、これらの経
路はセラミック基板厚を約０．５ｍｍ以上にし、半導体
素子厚を０．２ｍｍ以上にすれば十分遮断できる。上記
以外の経路として受光素子３と基板１とのすき間を散乱
通過するパスがあるが、そのすき間の高さを１００μｍ
以下（例えばバンプ電極８の厚さを３０μｍとし、フィ
ンガーリード厚を３５ ｉｔ ｍとする）にすることに
より十分遮光できる。The light-receiving element 3 is die-bonded to the circuit wiring conductor 2 with its light-receiving surface facing up, and the light-receiving surface side is wire bonded with a bonding wire 5. A semiconductor element 4 for processing a signal from the light receiving element 3 is bonded to the finger lead 9 with its functional element forming surface facing down so as to avoid the influence of light irradiated onto the light receiving element. The entirety of the light receiving element 3 and the semiconductor element 4 is sealed with a light-transmitting filter resin 6 that transmits only light of a wavelength within the operating band of the light receiving element and blocks light of other wavelengths. The light-transmitting filter resin 6 is a blend of epoxy resin and light-absorbing pigment. In such a light-receiving device structure, the paths of light irradiated onto the functional element surface of the semiconductor element 4 include a path that passes through the ceramic substrate 1 and a path that passes through the resin 6 and the Si single crystal substrate of the semiconductor element 4. These paths can be sufficiently blocked by making the ceramic substrate thicker than about 0.5 mm and making the semiconductor element thicker than 0.2 mm. As a path other than the above, there is a path that scatters through the gap between the light receiving element 3 and the substrate 1, but the height of the gap is set to 100 μm.
By setting the thickness to the following (for example, the thickness of the bump electrode 8 is 30 μm and the thickness of the finger lead is 35 it m), light can be sufficiently shielded.
第２図は本発明の第２の実施例の縦断面図である。第１
の実施例と異なる点は、セラミック基板の代わりにエポ
キシガラス基板を使用していることである。この実施例
では遮光性が悪いので、半導体素子の機能素子部への遮
光性を改善するために半導体素子４の搭載位置と対向す
るエポキシガラス基板１２の表面に遮光銅箔１３を形成
しである。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. 1st
The difference from the embodiment is that an epoxy glass substrate is used instead of a ceramic substrate. In this embodiment, the light shielding property is poor, so in order to improve the light shielding property to the functional element part of the semiconductor element, a light shielding copper foil 13 is formed on the surface of the epoxy glass substrate 12 facing the mounting position of the semiconductor element 4. .
以上説明したように本発明は、受光素子以外の半導体素
子をフェイスダウンボンディングすることにより、その
機能素子部への光の照射を基板の素子自体のサブストレ
ートにより遮光することができるようにすると共に、受
光素子は照射光を受光できるように受光面をフェイスア
ップしてボンディングしである。このため本発明の受光
動作型混成集積回路は、受光素子の動作帯域の波長の光
のみを透過させる特性を有する１種類の透光性フィルタ
樹脂で封止することができるという効果を奏する。As explained above, the present invention enables face-down bonding of semiconductor elements other than the light-receiving element, thereby making it possible to block light irradiation to the functional element part by the substrate of the element itself on the substrate. The light-receiving element is bonded with the light-receiving surface facing up so that it can receive the irradiated light. Therefore, the light-receiving hybrid integrated circuit of the present invention has the advantage that it can be sealed with one type of light-transmitting filter resin that has the property of transmitting only light having a wavelength within the operating band of the light-receiving element.
第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図および第４図は従来
例の構成を示す断面図である。
１・・・セラミック基板、２・・・回路配線導体、３・
・・受光素子、４・・・半導体素子、５・・・ボンディ
ングワイヤ、６・・・透光性フィルタ樹脂、７・・・遮
光性樹脂、８・・・バンプ電極、９・・・フィンガーリ
ード、１０・・・半田付用リード端子、１２・・・エポ
キシガラス基板、１３・・・遮光銅箔。FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, and FIGS. 3 and 4 are sectional views showing the configuration of a conventional example. . 1...Ceramic substrate, 2...Circuit wiring conductor, 3.
... Light receiving element, 4... Semiconductor element, 5... Bonding wire, 6... Transparent filter resin, 7... Light blocking resin, 8... Bump electrode, 9... Finger lead , 10... Lead terminal for soldering, 12... Epoxy glass substrate, 13... Light-shielding copper foil.
Claims (1)
半導体素子とを搭載し、樹脂封止した受光動作型混成集
積回路装置において、装置の基板面に対し受光素子のみ
を受光面をフェイスアップさせてボンディングし、他の
半導体素子をフェイスダウンボンディングし、全体を透
光性フィルタ樹脂で封止したことを特徴とする受光動作
型混成集積回路装置。In a light-receiving type hybrid integrated circuit device in which a light-receiving element and other semiconductor elements are mounted on an insulated substrate with circuit wiring and sealed with resin, only the light-receiving element is placed face-up with the light-receiving surface facing up to the substrate surface of the device. 1. A light-receiving type hybrid integrated circuit device, characterized in that the device is bonded with a light-receiving type, other semiconductor elements are bonded face-down, and the whole is sealed with a light-transmitting filter resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62091156A JPS63255926A (en) | 1987-04-13 | 1987-04-13 | Hybrid integrated circuit device containing photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62091156A JPS63255926A (en) | 1987-04-13 | 1987-04-13 | Hybrid integrated circuit device containing photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63255926A true JPS63255926A (en) | 1988-10-24 |
Family
ID=14018646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62091156A Pending JPS63255926A (en) | 1987-04-13 | 1987-04-13 | Hybrid integrated circuit device containing photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63255926A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0321861U (en) * | 1989-07-11 | 1991-03-05 | ||
| JPH0399447U (en) * | 1990-01-31 | 1991-10-17 |
-
1987
- 1987-04-13 JP JP62091156A patent/JPS63255926A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0321861U (en) * | 1989-07-11 | 1991-03-05 | ||
| JPH0399447U (en) * | 1990-01-31 | 1991-10-17 |
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