JPH1126782A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1126782A
JPH1126782A JP9187196A JP18719697A JPH1126782A JP H1126782 A JPH1126782 A JP H1126782A JP 9187196 A JP9187196 A JP 9187196A JP 18719697 A JP18719697 A JP 18719697A JP H1126782 A JPH1126782 A JP H1126782A
Authority
JP
Japan
Prior art keywords
light receiving
semiconductor element
semiconductor
semiconductor device
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9187196A
Other languages
Japanese (ja)
Inventor
Hideo Yamamoto
秀男 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP9187196A priority Critical patent/JPH1126782A/en
Publication of JPH1126782A publication Critical patent/JPH1126782A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Light Receiving Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate the package made of ceramic or the like, by forming a space only in the light receiving area of the light receiving element in a semiconductor element, providing airtight sealing by a transparent member, and directly soldering an external connecting electrode pad of the semiconductor element to another mounting substrate with Ni or the like. SOLUTION: The surface of a light receiving area 2 is covered by a transparent member 3 comprising glass or the like, wherein a frame part 3a is formed as a unitary body at a surrounding part, so that a space is formed on the light receiving area 2 of the light receiving element of a semiconductor element 1. Sealing resin 6 is provided at the junction part of the transparent member and the surface of the semiconductor element 1, and bonding sealing is performed. A wiring 4 from the light receiving area is introduced to the surface of the external surrounding part of the semiconductor element 1. The surface of an external connecting electrode pad 5 provided at the end of the wire comprises metal or alloy such a Ni or the like. The wire is directly soldered to the mounting substrate. Therefore, the package comprising ceramic or the like can be eliminated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、フォトダイオー
ド,ラインセンサ,イメージセンサ等の受光素子を有す
る半導体素子からなる半導体装置に関し、特に半導体素
子の実装構成を改善した半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comprising a semiconductor element having a light receiving element such as a photodiode, a line sensor, an image sensor, etc., and more particularly to a semiconductor device having an improved semiconductor element mounting structure.

【0002】[0002]

【従来の技術】従来、フォトダイオード,ラインセン
サ,イメージセンサ等の受光素子を有する半導体素子の
実装構成としては、図6に示すような構成のものが知ら
れている。すなわち、受光部エリア102 を備えた受光素
子を有する半導体素子101 は、セラミック等からなるパ
ッケージ103 内に収納され、半導体素子101 の表面の外
部接続用電極とパッケージ103 に設けられた電極とを金
属細線104 で接続し、パッケージ103 の表面にはガラス
等の透明部材105 が載置され、それらの接合部を封止樹
脂106 で封止して半導体装置を構成している。なお図6
において、107 はパッケージ103 の側面に設けられた外
部リードである。
2. Description of the Related Art Conventionally, as a mounting structure of a semiconductor device having a light receiving element such as a photodiode, a line sensor, an image sensor, etc., a structure as shown in FIG. 6 is known. That is, a semiconductor element 101 having a light receiving element having a light receiving section area 102 is housed in a package 103 made of ceramic or the like, and an external connection electrode on the surface of the semiconductor element 101 and an electrode provided in the package 103 are made of metal. The semiconductor devices are connected by thin wires 104, and a transparent member 105 such as glass is mounted on the surface of the package 103, and their joints are sealed with a sealing resin 106. FIG. 6
In the figure, 107 is an external lead provided on the side surface of the package 103.

【0003】また、特開平3−155671号には、図
7に示すように、受光部エリア202を備えた受光素子を
有する半導体素子201 が、配線204 を設けたガラス等か
らなる透明部材203 に、突起電極205 を介して電気的に
接続され、半導体素子201 の外周部が封止樹脂206 で封
止され、前記透明部材203 の表面に形成された電極パッ
ド207 で、別体の図示しない実装基板に接続できるよう
に構成したものが開示されており、この突起電極を介し
て接続し実装する方式は、COG(チップオングラス)
方式と呼ばれている。
As shown in FIG. 7, in Japanese Patent Application Laid-Open No. 3-155657, a semiconductor element 201 having a light-receiving element provided with a light-receiving section area 202 is mounted on a transparent member 203 made of glass or the like provided with a wiring 204. The semiconductor element 201 is electrically connected via a protruding electrode 205, the outer peripheral portion of the semiconductor element 201 is sealed with a sealing resin 206, and an electrode pad 207 formed on the surface of the transparent member 203 is mounted on the transparent member 203. A structure configured to be connectable to a substrate is disclosed, and a method of connecting and mounting via this protruding electrode is COG (chip-on-glass).
It is called a method.

【0004】[0004]

【発明が解決しようとする課題】ところで、図6に示し
たようなセラミック等のパッケージに半導体素子を収納
するようにした実装方式では、小型化並びに薄型化が難
しい上、セラミック等のパッケージが高価なため、コス
トの低減も難しいという問題点がある。また、図7に示
したようなガラス等の透明基板へ突起電極を介して接続
するCOG方式を用いた実装方式では、封止樹脂が受光
部エリアまで侵入しやすく、受光部エリアの一部が封止
樹脂で覆われてしまう危険がある。更にCOG方式を用
いた実装形態の一つとして、透明基板と受光素子を有す
る半導体素子の間を透明樹脂で充填してしまう実装方法
もあるが、このように透明樹脂を充填した場合、熱スト
レスや吸湿により、受光部エリア表面又は透明基板表面
に透明樹脂の剥離が発生しやすい上、受光素子としてマ
イクロレンズ付きのイメージセンサが設けられている場
合には、封止樹脂の充填によりレンズ効果が大幅に低下
してしまうなどの問題点が多く、したがって受光素子を
有する半導体素子の表面には空間を設けた方がよいこと
がわかっている。
By the way, in a mounting system in which a semiconductor element is housed in a package such as a ceramic as shown in FIG. 6, it is difficult to reduce the size and thickness and the package such as a ceramic is expensive. Therefore, there is a problem that cost reduction is difficult. Further, in the mounting method using the COG method of connecting to a transparent substrate made of glass or the like through a protruding electrode as shown in FIG. There is a risk of being covered with the sealing resin. Further, as one of the mounting modes using the COG method, there is a mounting method in which a space between a transparent substrate and a semiconductor element having a light receiving element is filled with a transparent resin. The transparent resin easily peels off on the surface of the light receiving area or the surface of the transparent substrate due to moisture absorption, and when an image sensor with a micro lens is provided as a light receiving element, the lens effect is obtained by filling the sealing resin. There are many problems such as drastic reduction, and it has been found that it is better to provide a space on the surface of a semiconductor element having a light receiving element.

【0005】本発明は、従来の実装方式による半導体装
置における上記問題点を解消するためになされたもの
で、実装サイズの小型化、薄型化並びに軽量化が可能
で、実装コストの低減が図れる半導体装置を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems in a semiconductor device using a conventional mounting method, and it is possible to reduce the mounting size, thickness and weight of the semiconductor device, and to reduce the mounting cost. It is intended to provide a device.

【0006】[0006]

【課題を解決するための手段】上記問題点を解決するた
め、本発明は、フォトダイオード,ラインセンサ,イメ
ージセンサ等の受光素子を有する半導体素子に対して、
ガラス,石英,サファイア,透明樹脂等の透明部材を、
該半導体素子の受光部表面との間に空間が形成されるよ
うに前記半導体素子の受光部エリアにのみ配設して、該
半導体素子の受光部エリアを封止し、前記半導体素子の
外周部に引き出された外部接続用電極パッドの表面を、
Ni,Cr,Au,Ag,ハンダ等の直接ハンダ付け可
能な金属又は合金で形成して半導体装置を構成するもの
である。
In order to solve the above problems, the present invention relates to a semiconductor device having a light receiving element such as a photodiode, a line sensor, an image sensor and the like.
Transparent members such as glass, quartz, sapphire, and transparent resin
The light receiving portion area of the semiconductor element is disposed only in the light receiving portion area of the semiconductor element so that a space is formed between the light receiving portion surface of the semiconductor element and the outer peripheral portion of the semiconductor element. The surface of the external connection electrode pad drawn out to
The semiconductor device is made of a metal or alloy that can be directly soldered such as Ni, Cr, Au, Ag, and solder.

【0007】このように構成された半導体装置において
は、受光部エリアのみが空間を形成して透明部材により
気密封止され、また直接ハンダ付け可能にされた外部接
続用電極パッドが設けられているため、セラミック等の
パッケージが不要となり、パッケージへのダイボンドや
ワイヤボンドも必要がなくなり、実装サイズの小型化、
薄型化及び軽量化を図ることができ、また実装コストの
低減化も可能となる。また、半導体基板に設けた凹部内
に受光素子の受光部エリアを設けた半導体素子を、CO
G方式で実装することにより、封止樹脂が受光部エリア
まで侵入しないようにすることができる。
In the semiconductor device thus constructed, only the light receiving section area forms a space, is hermetically sealed by a transparent member, and is provided with an external connection electrode pad which can be directly soldered. This eliminates the need for packages such as ceramics, and eliminates the need for die bonding and wire bonding to the package.
The thickness and the weight can be reduced, and the mounting cost can be reduced. Further, a semiconductor element having a light receiving portion area of a light receiving element provided in a concave portion provided in a semiconductor substrate is replaced with a CO.
By mounting by the G method, it is possible to prevent the sealing resin from entering the light receiving area.

【0008】[0008]

【発明の実施の形態】次に、実施の形態について説明す
る。図1の(A),(B)は、本発明に係る半導体装置
の第1の実施の形態を示す平面図及び断面図である。図
において、1は受光素子を有する半導体素子で、該半導
体素子1の受光素子の受光部エリア2上に空間が形成さ
れるように、周辺部に枠部3aが一体的に形成された、
ガラス,石英,透明樹脂等からなる透明部材3により、
該受光部エリア2の表面が覆われ、透明部材3と半導体
素子1の表面との接合部分には封止樹脂6が設けられ接
着封止している。また、半導体素子1の外周部表面には
受光部エリア2からの配線4が導出されていて、その末
端に設けられた外部接続用電極パッド5の表面は、N
i,Cr,Au,Ag,ハンダ等の金属又は合金からな
り、半導体素子1を別体の図示しない実装基板に直接ハ
ンダ付けできるように構成されている。
Next, an embodiment will be described. 1A and 1B are a plan view and a sectional view showing a first embodiment of a semiconductor device according to the present invention. In the figure, reference numeral 1 denotes a semiconductor element having a light receiving element, and a frame portion 3a is integrally formed in a peripheral portion so that a space is formed on a light receiving section area 2 of the light receiving element of the semiconductor element 1.
The transparent member 3 made of glass, quartz, transparent resin, etc.
The surface of the light receiving section area 2 is covered, and a sealing resin 6 is provided at the junction between the transparent member 3 and the surface of the semiconductor element 1 to seal and bond. On the outer peripheral surface of the semiconductor element 1, a wiring 4 is led out from the light receiving area 2, and the surface of the external connection electrode pad 5 provided at the end thereof is N
It is made of a metal or alloy such as i, Cr, Au, Ag, solder, or the like, and is configured so that the semiconductor element 1 can be directly soldered to a separate mounting board (not shown).

【0009】このように構成された半導体装置は、上記
のように半導体素子を実装基板に直接ハンダ付けできる
ため、セラミック等からなるパッケージが不要となり、
実装サイズの小型化、薄型化及び軽量化を図ることがで
き、実装コストの低減化も可能となる。
In the semiconductor device configured as described above, since the semiconductor element can be directly soldered to the mounting substrate as described above, a package made of ceramic or the like is not required.
The mounting size can be reduced in size, thickness and weight, and the mounting cost can be reduced.

【0010】次に、第2の実施の形態について説明す
る。図2は第2の実施の形態を示す断面図で、図1の
(A),(B)に示した第1の実施の形態と同一又は対
応する部材には同一符号を付して示している。この実施
の形態では、半導体素子1の受光部エリア2を囲む外周
上に、ポリイミド,エポキシ,フェノール等の合成樹脂
を用いて、封止枠7を印刷又はエッチング等の手法によ
り形成し、この封止枠7の表面にガラス,石英,サファ
イア,透明樹脂等からなる板状の透明部材3を、封止樹
脂6で接着封止して、半導体装置を構成するものであ
る。
Next, a second embodiment will be described. FIG. 2 is a sectional view showing a second embodiment, in which the same or corresponding members as those in the first embodiment shown in FIGS. 1A and 1B are denoted by the same reference numerals. I have. In this embodiment, a sealing frame 7 is formed on the outer periphery surrounding the light receiving section area 2 of the semiconductor element 1 using a synthetic resin such as polyimide, epoxy, or phenol by printing or etching. A plate-shaped transparent member 3 made of glass, quartz, sapphire, transparent resin or the like is bonded and sealed with a sealing resin 6 on the surface of the stop frame 7 to constitute a semiconductor device.

【0011】この実施の形態においては、透明部材3を
第1の実施の形態のように周辺部に枠部を一体的に形成
した成形品ではなく、単なる板体で構成できるので、更
に実装コストを低減することができる。なお、上記封止
枠7は印刷等の手法で形成する代わりに、樹脂等により
別体で成形等により形成し、半導体素子表面に接着して
配設するようにしてもよいことは勿論である。
In this embodiment, the transparent member 3 can be constituted by a simple plate rather than a molded product in which the frame is integrally formed in the peripheral portion as in the first embodiment. Can be reduced. Note that, instead of forming the sealing frame 7 by a method such as printing, it is needless to say that the sealing frame 7 may be formed separately by molding with a resin or the like and adhered to the surface of the semiconductor element. .

【0012】図3は、図2に示した第2の実施の形態の
変形例を示す断面図で、この変形例においては、枠体7
の外周部の大きさを板状の透明部材3の外周部より小さ
く形成して、封止樹脂6を透明部材3と半導体素子1の
表面との間に渡って塗布し、接着封止するようにしたも
ので、図2に示した第2の実施の形態と同様の効果が得
られる。
FIG. 3 is a sectional view showing a modification of the second embodiment shown in FIG. 2. In this modification, a frame 7 is shown.
Is formed smaller than the outer peripheral portion of the plate-shaped transparent member 3, the sealing resin 6 is applied between the transparent member 3 and the surface of the semiconductor element 1, and the sealing is performed. With this configuration, the same effect as that of the second embodiment shown in FIG. 2 can be obtained.

【0013】図4は、本発明の第3の実施の形態を示す
断面図であり、図1の(A),(B)に示した第1の実
施の形態と同一又は対応する部材には同一符号を付して
示している。この実施の形態においては、半導体素子1
を構成する半導体基板に予め凹部を形成しておき、該凹
部に受光素子の受光部エリア2を形成し、該受光部エリ
ア2から半導体素子1の外周部表面まで表面配線4を設
け、半導体素子1の表面に直接、板状の透明部材3を載
置して封止樹脂6で接着封止するようにしたものであ
る。
FIG. 4 is a sectional view showing a third embodiment of the present invention, in which members identical or corresponding to those of the first embodiment shown in FIGS. The same reference numerals are given. In this embodiment, the semiconductor element 1
A concave portion is previously formed in the semiconductor substrate constituting the semiconductor device, a light receiving portion area 2 of the light receiving element is formed in the concave portion, and a surface wiring 4 is provided from the light receiving portion area 2 to the outer peripheral surface of the semiconductor device 1. The plate-shaped transparent member 3 is placed directly on the surface of the substrate 1 and is sealed with a sealing resin 6.

【0014】この実施の形態においては、図2及び図3
に示した第2の実施の形態及びその変形例における封止
枠を形成する必要がないため、厚み方向において更に薄
型化を図ることができる。
In this embodiment, FIGS. 2 and 3
Since it is not necessary to form the sealing frame according to the second embodiment and its modification shown in FIG. 1, the thickness can be further reduced in the thickness direction.

【0015】なお、上記第1〜第3の実施の形態におい
て、透明部材3を、各種光学フィルタ,回折格子,偏光
板,ホログラム,プリズム,レンズ等の光学部品で形成
してもよいことは勿論である。
In the first to third embodiments, the transparent member 3 may be formed of optical components such as various optical filters, diffraction gratings, polarizing plates, holograms, prisms and lenses. It is.

【0016】図5は、第4の実施の形態を示す断面図で
ある。この実施の形態は、図4に示した第3の実施の形
態と同様に、半導体素子を構成する半導体基板に予め凹
部を形成しておき、該凹部に受光素子の受光部エリア2
を形成し、該受光部エリア2から半導体素子1の外周部
表面まで表面配線4を設け、その末端部にAu,ハンダ
等からなる突起電極8を形成する。一方、ガラス,石
英,サファイア等の板状の透明部材3には、端部に電極
パッド5を形成した表面配線4を設けておき、該透明部
材3の表面配線4に突起電極8を介して前記半導体素子
を電気的に接続し、該電気的接続部分を封止樹脂6で接
着封止して半導体装置を構成するものである。
FIG. 5 is a sectional view showing a fourth embodiment. In this embodiment, similarly to the third embodiment shown in FIG. 4, a concave portion is previously formed in a semiconductor substrate constituting a semiconductor element, and the light receiving portion area 2 of the light receiving element is formed in the concave portion.
Is formed, a surface wiring 4 is provided from the light receiving area 2 to the outer peripheral surface of the semiconductor element 1, and a protruding electrode 8 made of Au, solder or the like is formed at the end. On the other hand, a plate-shaped transparent member 3 made of glass, quartz, sapphire, or the like is provided with a surface wiring 4 having an electrode pad 5 formed at an end portion. The semiconductor element is electrically connected, and the electrically connected portion is bonded and sealed with a sealing resin 6 to form a semiconductor device.

【0017】この実施の形態においては、突起電極8を
介して半導体素子1と平板状の透明部材3とを電気的に
接続し、該接続部分を封止樹脂で封止するようにしたC
OG方式を用いた場合においても、受光素子の受光部エ
リアが半導体基板の凹部に形成されているため、封止樹
脂が受光部エリアまで侵入するのを防止することができ
る。
In this embodiment, the semiconductor element 1 and the plate-shaped transparent member 3 are electrically connected via the protruding electrode 8, and the connection portion is sealed with a sealing resin.
Even when the OG method is used, since the light receiving area of the light receiving element is formed in the concave portion of the semiconductor substrate, it is possible to prevent the sealing resin from entering the light receiving area.

【0018】[0018]

【発明の効果】以上実施の形態に基づいて説明したよう
に、本発明によれば、半導体素子における受光素子の受
光部エリアのみが空間を形成して透明部材により気密封
止され、また半導体素子の外部接続用電極パッドが別体
の実装基板に直接ハンダ付けが可能なように構成されて
いるため、セラミック等のパッケージが不要となり、ま
たパッケージへのダイボンドやワイヤボンドも必要がな
く、実装サイズの小型化、薄型化及び軽量化を図ること
ができ、また実装コストを低減することができる。ま
た、受光素子の受光部エリアを半導体基板の凹部に形成
することにより、突起電極を利用したCOG方式を用い
て実装を行った場合においても、封止樹脂の受光部エリ
アへの侵入を防止することができる。
As described above with reference to the embodiments, according to the present invention, only the light receiving portion area of the light receiving element in the semiconductor element forms a space and is hermetically sealed by the transparent member. The external connection electrode pads are configured so that they can be soldered directly to a separate mounting board, eliminating the need for packages such as ceramics, and eliminating the need for die or wire bonding to the package. It is possible to reduce the size, thickness, and weight of the device, and to reduce the mounting cost. Further, by forming the light receiving portion area of the light receiving element in the concave portion of the semiconductor substrate, even when mounting is performed using the COG method using the protruding electrodes, the sealing resin is prevented from entering the light receiving portion area. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体装置の第1の実施の形態を
示す平面図及び断面図である。
FIG. 1 is a plan view and a cross-sectional view illustrating a first embodiment of a semiconductor device according to the present invention.

【図2】本発明の第2の実施の形態を示す断面図であ
る。
FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】図2に示した第2の実施の形態の変形例を示す
断面図である。
FIG. 3 is a cross-sectional view showing a modification of the second embodiment shown in FIG.

【図4】本発明の第3の実施の形態を示す断面図であ
る。
FIG. 4 is a sectional view showing a third embodiment of the present invention.

【図5】本発明の第4の実施の形態を示す断面図であ
る。
FIG. 5 is a sectional view showing a fourth embodiment of the present invention.

【図6】従来の半導体装置の構成例を示す断面図であ
る。
FIG. 6 is a cross-sectional view illustrating a configuration example of a conventional semiconductor device.

【図7】従来の半導体装置の他の構成例を示す断面図で
ある。
FIG. 7 is a cross-sectional view showing another configuration example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 受光部エリア 3 透明部材 4 表面配線 5 電極パッド 6 封止樹脂 7 封止枠 8 突起電極 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Light-receiving area 3 Transparent member 4 Surface wiring 5 Electrode pad 6 Sealing resin 7 Sealing frame 8 Projecting electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 フォトダイオード,ラインセンサ,イメ
ージセンサ等の受光素子を有する半導体素子に対して、
ガラス,石英,サファイア,透明樹脂等の透明部材を、
該半導体素子の受光部表面との間に空間が形成されるよ
うに前記半導体素子の受光部エリアにのみ配設して、該
半導体素子の受光部エリアを封止し、前記半導体素子の
外周部に引き出された外部接続用電極パッドの表面を、
Ni,Cr,Au,Ag,ハンダ等の直接ハンダ付け可
能な金属又は合金で形成していることを特徴とする半導
体装置。
1. A semiconductor device having a light receiving element such as a photodiode, a line sensor, and an image sensor.
Transparent members such as glass, quartz, sapphire, and transparent resin
The light receiving portion area of the semiconductor element is disposed only in the light receiving portion area of the semiconductor element so that a space is formed between the light receiving portion surface of the semiconductor element and the outer peripheral portion of the semiconductor element. The surface of the external connection electrode pad drawn out to
A semiconductor device formed of a directly solderable metal or alloy such as Ni, Cr, Au, Ag, and solder.
【請求項2】 前記半導体素子の受光部エリアの外周部
上に、ポリイミド,エポキシ,フェノール等の合成樹脂
からなる封止枠を配設し、該封止枠の表面に前記受光部
エリアを覆うように前記透明部材を載置したことを特徴
とする請求項1記載の半導体装置。
2. A sealing frame made of a synthetic resin such as polyimide, epoxy or phenol is provided on an outer peripheral portion of a light receiving area of the semiconductor element, and the surface of the sealing frame covers the light receiving area. 2. The semiconductor device according to claim 1, wherein the transparent member is mounted as described above.
【請求項3】 前記半導体素子の受光部エリアが予め半
導体基板に設けられた凹部内に形成されており、該受光
部エリアからの配線が前記半導体基板の外周部表面に引
き出されていることを特徴とする請求項1記載の半導体
装置。
3. The semiconductor device according to claim 1, wherein a light receiving area of the semiconductor element is formed in a concave portion provided on the semiconductor substrate in advance, and a wiring from the light receiving area is drawn out to an outer peripheral surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein:
【請求項4】 半導体基板に設けた凹部内に受光素子の
受光部エリアを形成し、半導体基板の外周部表面に引き
出された配線に外部接続用電極パッドを形成してなる半
導体素子に、配線を施した透明部材を前記半導体素子の
受光部エリアに対向させて配置し、前記半導体素子の電
極パッドをAu,ハンダ等からなる突起電極を介して前
記透明部材の配線に電気的に接続し、該電気的接続部を
封止材で封止したことを特徴とする半導体装置。
4. A semiconductor device comprising: a light receiving portion area of a light receiving element formed in a concave portion provided in a semiconductor substrate; and an external connection electrode pad formed on a wiring led out to an outer peripheral surface of the semiconductor substrate. The transparent member subjected to the above is disposed facing the light receiving area of the semiconductor element, and the electrode pad of the semiconductor element is electrically connected to the wiring of the transparent member via a projecting electrode made of Au, solder, or the like, A semiconductor device, wherein the electrical connection portion is sealed with a sealing material.
JP9187196A 1997-06-30 1997-06-30 Semiconductor device Withdrawn JPH1126782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9187196A JPH1126782A (en) 1997-06-30 1997-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9187196A JPH1126782A (en) 1997-06-30 1997-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1126782A true JPH1126782A (en) 1999-01-29

Family

ID=16201789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9187196A Withdrawn JPH1126782A (en) 1997-06-30 1997-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1126782A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005096366A (en) * 2003-09-26 2005-04-14 Seiko Epson Corp Liquid jetting apparatus and method for manufacturing the same
JP2011030173A (en) * 2009-06-23 2011-02-10 Sony Corp Solid-state imaging device
US9548145B2 (en) 2007-01-05 2017-01-17 Invensas Corporation Microelectronic assembly with multi-layer support structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005096366A (en) * 2003-09-26 2005-04-14 Seiko Epson Corp Liquid jetting apparatus and method for manufacturing the same
JP4649827B2 (en) * 2003-09-26 2011-03-16 セイコーエプソン株式会社 Liquid ejecting apparatus and manufacturing method thereof
US9548145B2 (en) 2007-01-05 2017-01-17 Invensas Corporation Microelectronic assembly with multi-layer support structure
JP2011030173A (en) * 2009-06-23 2011-02-10 Sony Corp Solid-state imaging device

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