JPS63254822A - Exclusive nor circuit - Google Patents

Abstract

PURPOSE:To obtain an exclusive NOR circuit where an output of a N-channel FET is not decreased by a threshold level when both of two input signals are at 'H' by adding a P-channel FET outputting an 'H' level when both two input signals are at 'H' and a control circuit of the FET in the circuit constitution of MOSFETs. CONSTITUTION:A P-channel FET 21 is controlled by a control circuit 24. The on-resistance ratio of the FET 21 and the N-channel FETs 13, 14 is decided so that the output C goes to 'H'-Vth or below when both are turned on simultaneously and a through-current flows. With both input signals A, B at 'H', a series circuit 9 of the P-channel FET is turned off and a series circuit 16 of the N-channel FET is turned on. A level of 'H'-Vth is fed to a terminal 7 from terminals 3, 5, but the gate of the P-channel FET 21 goes to 'L' and an 'H' level is outputted to the terminal 7 from a power terminal 20 through the FET 21, resulting that the output signal goes to 'H', and even when both inputs A, B are at 'H', an exclusive NOR circuit obtaining an output without decreased Vth is obtained even when both inputs A, B are at 'H'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an exclusive NOR circuit constituted by MOS transistors.

[Conventional technology]

FIG. 4 is a diagram showing an exclusive NOR circuit constructed from conventional MOS transistors. In the figure, A and B are input signals, C is an output signal, (1) to (3) are input terminals to which input signal A is input, (4) to (6) are input terminals to which input signal B is input, and (7) is an input terminal to which input signal B is input. The output terminal (0 or (9), which is the original terminal for 81 companies) is a series circuit of P-channel transistors,
(The source of the P-channel transistor II is the power supply terminal (
8), its gate is connected to the input terminal (1), its drain is connected to the source of one P-channel transistor (a), the gate of the P-channel transistor (b) is connected to the input terminal (4), and the drain is connected to the output terminal (7). (2) is a parallel circuit of N-channel transistors, and the N-channel transistor (2) has its source (drain) connected to the input terminal (5), its gate connected to the input terminal (2), and its drain ( The N-channel transistor of α has its source (drain) connected to the input terminal (3), its gate connected to the input terminal (61), and its drain (source) connected to the output terminal (7). It is connected to terminal (7). - Next, for the 0 human power signals A and H whose operation will be explained, "H"(HIGH==5'V),L" (LO
It is assumed that only two levels are available (W=φV), and that 5V is supplied from the power supply terminal. When input signals A and B are both high, a series circuit of P-channel transistors (9
) is 0FFI, the N-channel transistor (transfer) and the α field are turned on. The N-channel transistor that was turned on at this time (
input signal A from input terminal (3), t5) through α→.

B is output to the output terminal (7), and both input signals A and B are K.
5SH1l, the output signal C is IsH"-vt
h (threshold voltage). When input signals A and B are both "L", the series circuit of P-channel transistors (9) is ON, and the parallel circuit of N-channel transistors (to) is OFF.The series circuit of P-channel transistors that is ON at this time Through (9), "H" is output from the power supply (8) to the output terminal (7), and the output signal O is V
″H//.

When the input signal A is "H" and the input signal B is "L", the P-channel transistor series circuit (9) and the N-channel transistor a4 are turned OFF, and the N-channel transistor 0 is turned ON. , from the input terminal (5) to the output terminal (7) through the turned-on N-channel transistor 01.
Since the input signal B is output to , and the output signal B is "L", the output signal C becomes "1L". Similarly, even if the input signal A is "L" and the input signal B is "H", the output signal O becomes "L". The exclusive NOR circuit is configured as described above.

[Problem that the invention seeks to solve]

Since the conventional exclusive NOR circuit is configured as described above, when the input signals A and B are both "H", the output signal C is output through the N channel transistor.
There was a problem that tb was reduced.

This invention was made in order to solve the above-mentioned problems, and is an exclusive NO that does not cause the output signal C to fall below "H" by Vth even when the input signals A and B are both "H".
The purpose is to obtain an R circuit.

[Means for solving problems]

The exclusive NOR circuit according to the present invention has a circuit configuration using MOS transistors, and input signals A and B are both %SH/
A P-channel transistor that outputs "H" at the time of / and a circuit that controls this P-channel transistor are added.

[Effect]

The circuit for controlling the P-channel transistor in this invention outputs "H" when both input signals A and B are "H", so it obtains an output signal C of "NH" that does not decrease by vth. be able to.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, Ov is the ground, M is a series circuit of N-channel transistors, and αp is the N-channel transistor whose source is connected to the ground (to) and whose gate is the input terminal (
1), the drain is connected to the source of the (to) N-channel transistor, and the N-channel transistor a8i is
The gate is connected to the input terminal (4), the drain is connected to the connection point αC, the vertical line is the power supply terminal, the vertical p is a P-channel transistor, the source is connected to the power supply terminal -, and the gate is connected to the connection point α9. 0, the drain is connected to the output terminal (7), the wire is a 5V single power supply, the wire is a P-channel transistor, the source is connected to the power supply terminal -,
The gate is connected to the output terminal (7), and the drain is connected to the connection point α0. (Incorporated) is a control circuit that controls the P-channel transistor. In addition, P channel transistor QD and N channel transistor (to), α4
The ratio of ON resistances is set so that when both are simultaneously IC0N and a through current flows, the output signal C becomes (ttH//-y, h) or less.

Next, the operation will be explained. Both input signals A and B are H“
When , the series circuit (9) of P-channel transistors is 0FFj,, N-channel transistor @.

The series circuit α· of α→ and N-channel transistors is turned on. At this time, ONI is a nine-channel transistor.

Input terminals (3) and (5) through α4)
-Vth is about to be output to the output terminal (7). However, at the same time, due to the series circuit αQ of the N-channel transistor, the gate of the P-channel transistor becomes 1L, so the P-channel transistor is turned on.
'SH' is output from the power supply terminal - to the output terminal (7) through the P-channel transistor Qυ, and as a result, the output signal C becomes 'H'. Both input signals A and B are 'L'. When ", the series circuit (9) of P-channel transistors is ONj, and the parallel circuit (2) of N-channel transistors and the series circuit aQ of N-channel transistors are OFF'. At this time, it is turned ON and connected to the power supply terminal (8) through the series circuit (9) of nine P-channel transistors.
" is output to the output terminal (7), and the output signal C becomes "H".

Also, at this time, I'H" may be output from the power supply terminal Q to the output terminal (7) through the P-channel transistor (2), but this is not a problem since it is used for the same purpose. Input signal A When is H and the output signal B is 1, the series circuit (9) of P channel transistors, the series circuit αQ of N channel transistors, the N channel transistor 0 is OF'FL, and the N channel transistor Ql is ON. When the N-channel transistor is turned on (
2), the input terminal (5) is about to be output to the output terminal (7). However, when the P-channel transistor ■ is ON, ゝゝH〃 is going to be output from the power supply wire to the output terminal (7) through the P-channel transistor (c), so the output signal O is simultaneously It is determined by comparing the ON resistances of the N-channel transistor α1 and the P-channel transistor (c) that are turned on. However, the ratio of ON resistance is such that the output signal C is (ゝ'H//-y
, h) is set in advance to be below, so
As a result, the p-channel transistor 6 is turned on, and "H" is output from the current g terminal 4 to the gate of the p-channel transistor CD through this p-channel transistor 7, and the p-channel transistor 1) is turned off. . Therefore, only the 6L" signal is output from the input terminal (5) to the output terminal (7) through the N-channel transistor (to), and the output signal C becomes SSL".

Similarly, when the input signal A is 1'L" and the output signal B is X'H, the output signal C becomes L. The input signal A is obtained as described above.

An exclusive NOR circuit can be configured in which the output signal C becomes "H//" even when both B are SSH//.

In the above embodiment, a circuit configuration like that of the control circuit φ was used to control the P-channel transistor, but a circuit configuration as shown in FIG. 2.3 may also be used. Figure 2 shows an ordinary NAND circuit. In FIG. 3, (7) is a resistance. In this circuit, input signals A and B are both 1c
At the time of "H", the parallel circuit of P channel transistors (
) becomes OF'FL, connection point 0 company 1L IJ. When at least one of input signals A and B is 1L'', P
The parallel circuit of channel transistors (A) turns on, and current flows from the power supply (A) to the ground (13). At this time, the potential of the connection point α [present] is equal to the ON resistance of the parallel circuit of P channel transistors (A). It is determined by the ratio of resistance (7),
The resistance ratio is determined so that the potential at the connection point becomes about 112 so that the P-channel transistor I21) connected to this connection point α9 is not turned on. As a result, the P-channel transistor 蓅υ connected to the connection point α is turned on only when the input signals A and B are both ``H''.

〔Effect of the invention〕

As described above, according to the present invention, the input signal A.

Since the structure is configured such that when both B and B are at "H", the signal 1" is outputted to the output terminal through the P-channel transistor, it is possible to obtain an output signal of HT1 that does not drop by Vth.

[Brief explanation of drawings]

! 1 is a circuit diagram showing an exclusive NOR circuit according to one embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of a control circuit showing other embodiments of the present invention, and FIG. 4 is a circuit diagram showing a conventional exclusive NOR circuit. FIG. 2 is a circuit diagram showing a NOR circuit. A, B are input signals, C are output signals (1) to (6), (c), @ is an input terminal, (7) is an output terminal, (8), 翺, @ is a 5V power supply terminal, QQ is ov
ground, (II, α, 翰, @, (c). 翰 is a P-channel transistor, (9) is a series circuit of P-channel transistors, (A) is a parallel circuit of P-channel transistors, (to), α station, αη, (g) is an N-channel transistor, (2) is a parallel circuit of N-channel transistors, QQ is a series circuit of N-channel transistors, α is a connection point, (c) is a control circuit, (7) is a resistor In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an exclusive NOR circuit constituted by a series circuit of first and second P-channel transistors and a parallel circuit of first and second N-channel transistors, in order to obtain a HIGH output when both input signals are HIGH, Third P
An exclusive NOR circuit characterized in that a control circuit is added that turns on the channel transistor and the third P-channel transistor when both input signals are HIGH, and turns them off when one of the input signals is HIGH and the other is LOW. .