JPH04263513A - Variable input threshold value input device - Google Patents

Abstract

PURPOSE:To control the input threshold value of an input device and to connect a pre-step device having various valid output levels to one input device. CONSTITUTION:One of serially connected first and second transistor circuits 1 and 2 is defined as an MOSFET circuit to respond to the input signal at least, and one branching circuit 4 is provided at least parallelly to an FET 3 responding to the input of this MOSFET circuit and composed of two FET 5 and 6 serially connecting the channels. Then, the input signal is applied to the gate of one FET 5, and the control input signal of threshold value control is applied to the gate of the other FET 6. When the FET 6 is turned on, FET 3 and 5 are parallelly operated to the input, and conductivity is the sum of the channels of the FET 3 and 5. Since the input threshold value is decided according to the balance of conducitivity between the two transistor circuits, the input threshold value can be controlled by the control input signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable input threshold type input device, and is suitable for use in level conversion circuits, output stage buffer circuits, and the like.

0002

2. Description of the Related Art In a digital system, when the effective output level of a preceding circuit and the effective input level of a subsequent circuit are different, a level conversion circuit or a buffer circuit is provided at the input section of the subsequent circuit. Generally, the input threshold of such a level conversion circuit or buffer circuit is fixed, and the threshold is set in accordance with the output level of the preceding stage circuit.

[0003] When multiple types of pre-stage circuits or devices are planned to be connected to a post-stage circuit or device, and the effective output levels of each pre-stage circuit are different, the input section of the post-stage circuit must have multiple input threshold values. It won't happen. Conventionally, a plurality of input sections with different input thresholds have been provided in a subsequent circuit, or a plurality of types of subsequent circuits (devices) with different input thresholds have been prepared.

0004

[Problems to be Solved by the Invention] Providing a plurality of input sections in a subsequent-stage circuit or device increases the circuit scale, and providing multiple types of subsequent-stage circuits or devices with different input thresholds increases the circuit size. Otherwise, it is extremely cumbersome for equipment suppliers and users. In view of this point, the present invention
It is an object of the present invention to enable a plurality of types of pre-stage circuits or output devices having different effective output levels to be connected to one input device.

[0005]

[Means for Solving the Problems] As shown in the principle diagram of FIG. 1, a variable input threshold type input device according to the present invention has first and second parts connected in series to form a current path. It consists of transistor circuits 1 and 2, and at least one of the first and second transistor circuits 1 and 2 outputs an output signal in response to an input signal from an input terminal 7 to a connection point between the first and second transistor circuits. It is output from the output terminal 8 connected to A. One transistor circuit 2 responsive to the input signal includes a MOSFET 3 having a channel corresponding to the current path and receiving the input signal, and at least one shunt circuit 4 connected in parallel with the channel. The shunt circuit 4 consists of two MOSFETs 5 and 6 whose channels are connected in series along the shunt path,
One of the MOSFETs receives the input signal, and the other MOSFET 6 receives a control input signal from the control terminal 9 for selectively forming the branch path.

According to another feature of the present invention, the first
, the other of the second transistor circuits has the same configuration as the one transistor circuit, and each transistor circuit includes MOSFETs of mutually different conductivity types that operate complementary to the input signal. . According to another feature of the invention, the other of the first and second transistor circuits is a MO of the same conductivity type as the one transistor circuit.
MO composed of SFET and constituting the above current path
The SFET is configured with a load MOS circuit.

[0007]

[Operation] When a control input signal is applied to turn off the MOSFET 6 constituting the shunt circuit 4, no shunt path is formed, so that only the MOSFET 3 operates as a single inverter for the input signal. When a control input signal is applied to turn on MOSFET 6, a shunt path is formed and the MOSFET
3 and 5 operate in parallel to the input signal. Therefore, the transistor circuit 2 operates with the combined capacity of the MOSFETs 3 and 5, and the channel width of the current path is equivalently widened when viewed from the input terminal 7. The input threshold is transistor circuit 1, 2
The input threshold can be controlled by a control input signal.

[0008]

Embodiment FIG. 2 shows an embodiment in which the input device of the present invention is applied to a CMOS inverter circuit, and FIG. 3 shows a specific circuit configuration of FIG. Similar to FIG. 1, the input device of the embodiment consists of first and second transistor circuits 1, 2 arranged in series with respect to the power supply VDD to form a current path. These transistor circuits 1 and 2 constitute a complementary MOSFET circuit, with one transistor circuit 2 comprising, for example, an N-channel MOSFET, and the other transistor circuit 1 comprising a P-channel MOSFET. An input signal is supplied to each transistor circuit 1, 2 from an input terminal 7, and an output signal is derived from a connection point A of each transistor circuit 1, 2 to an output terminal 8. Each transistor circuit 1
, 2 are control terminals 9, 1 for controlling the input threshold
I have 0.

As shown in FIG. 3, an N-channel MOSF
The transistor circuit 2 composed of ET includes an N-channel MOSFET 3a having a gate to which an input signal is supplied from an input terminal 7 and a channel connected to a connection point A connected to an output terminal 8, as in FIG. Be prepared. Further, the transistor circuit 2 has a shunt circuit 4a connected in parallel with the channel of the MOSFET 3a, and this shunt circuit 4a includes an N-channel MOSFET 5 whose channel is connected in series with the output terminal 8 to form a shunt path.
It consists of a and 6a. One of these FETs 5a and 6a (
5a) receives an input signal from the input terminal 7 as a gate input, and the other (6a) receives a control input signal from the control terminal 9 for forming a branch channel.

On the other hand, the transistor circuit 1 is a P-channel MOSFET connected in the same way as the transistor circuit 2.
It consists of 3b, 5b, and 6b. MOSFET 3b receives the input signal as a gate input, and its channel is connected to connection point A. The channels of the MOSFETs 5b and 6b are connected in series at the connection point A to form a shunt circuit 4b. Further, MOSFET 5b receives an input signal as a gate input, and MOSFET 6b receives a control input signal for forming a branch channel from the control terminal 10 as a gate input.

Control input signal N applied to control terminals 9 and 10
, P is a 2-bit threshold control code that controls on/off of MOSFETs 6a and 6b. To explain an example of the operation of the transistor circuit 2, first, the control input N (low level) turns off the FET 6a of the shunt circuit 4a.
When the current is applied, the shunt circuit 4a becomes inactive. Therefore, MOSFET 3a operates as a single inverter element, and outputs an inverted input signal to output terminal 8.

Next, control input N to turn on FET6b
(high level), the shunt circuit 4a becomes effective,
The channels of the FETs 3a and 3b are connected in parallel to the connection point A connected to the output terminal 8. Each FET3a
, 5a have a common gate input, so if the transistors have the same size, they are equivalent to a single transistor with twice the channel width. That is, the conduction ability of the transistor circuit 2 is doubled.

The transistor circuit 1 composed of a P-channel MOSFET operates complementary to an input signal, and operates similarly to the transistor circuit 2 in response to a control input signal P applied to a control terminal 10. That is, when FET6b is off, FET3b operates as a single inverter, and when FET6b is on, FET3b operates with twice the conduction capacity.
, 5b operate in parallel is selected by control input P.

The input threshold of the CMOS input device (inverter) shown in FIG. 3 is determined by the balance between the conduction capabilities of the transistor circuits 1 and 2. If the sizes of transistors 3a, 3b, 5a, and 5b are the same, the result will be as shown in Table 1 below.

[0015]

[Table 1]

As shown in Table 1, the input threshold values are (1/2) VDD, (2/3) VDD, (1/3) VD.
D can be selected by the levels H and L (high level, low level) of the control input signals P and N. That is, if the control input signals P and N are a combination of (H, L),
Both FET6a, 6b are off, and FET3a, 3
Since the conduction capabilities of circuits 1 and 2 in which b operates as a CMOS inverter are equal, the input threshold value is (1/2) VDD. Similarly, if the control input signals P and N are a combination of (L, H), both FETs 6a and 6b are turned on, and FET 3
a, 3b, 5a, and 5b operate as parallel CMOS inverters. In this case as well, since the conduction abilities of circuits 1 and 2 are equal, the input threshold value is (1/2) VDD.

The combination of control input signals P and N is (L, L)
If so, FET6a is off and FET6b is on. In this state, the shunt circuit 4a of the transistor circuit 2
is off and the shunt circuit 4b of transistor circuit 1 is on, so the conduction ability of transistor circuits 1 and 2 is 2:1.
It is. Therefore, the input threshold value is (2/3) VDD. Further, when the combination of control input signals P and N is (H, H), FET 6a is on and FET 6b is off, so contrary to the above, the conduction ability of transistor circuits 1 and 2 is 1:2. becomes. Therefore, the input threshold is (1/3)VDD
becomes.

In the above example, FETs 3a, 3b, 5a, 5
This is a case where the sizes of b are the same, but they may be different sizes. For example, if only FET 5b is made twice the size of the others, the conduction capacity ratio of circuits 1 and 2 will be 1:1, 3:1,
Four types can be selected: 1:2 and 3:2, and the input threshold is set to 1 of VDD by 2-bit control input signals P and N.
It can be changed to /2, 3/4, 1/3, 3/5.

It is also possible to increase the number of shunt circuits 4a, 4b. For example, in the example of FIG.
If the same circuit as b is added to the transistor circuits 1 and 2, a larger number of input threshold values can be set by combining the 4-bit control input signal and the transistor size. In addition, in the example of FIG. 3, the FE for threshold control
Although T6a and 6b are of different conductivity types, they may be of the same conductivity type. In this case, in Table 1, the input threshold is (1/2) VDD when the control input signals P and N are at complementary levels, and the input threshold is (1/2) VDD when the control input signals P and N are at the same level. The threshold value becomes (1/3) VDD or (2/3) VDD.

FIG. 4 shows an embodiment in which the input device of the present invention is applied to an NMOS inverter circuit. This NMOS inverter circuit is composed of first and second transistor circuits 1 and 2, each of which is composed of an N-channel MOSFET, as in FIG. The transistor circuit 2 includes FETs 3, 5, and 6 connected in the same manner as in FIG. 1 or 3.
constitutes a shunt circuit 4 that can be turned on and off, and FETs 3 and 5
constitute a parallel MOS inverter circuit having a common input.

The transistor circuit 1 includes an N-channel MOSFET 11 that constitutes a load circuit of a MOS inverter. The gate and drain of this FET 11 are coupled, and its channel resistance is equal to that of the FET of the transistor circuit 2.
The load is 3. Both FETs 3 and 11 may be enhancement type, in which case they are F/E type MO
This becomes an S inverter circuit.

The transistor circuit 1 includes an N-channel MOSFET 12 forming a parallel channel with the FET 11. This FET 12 receives a control input signal from the control terminal 10 as a gate input, and is controlled on/off. This FET 12 may also be of the enhancement type, and becomes conductive when a high level control input signal is applied, forming a parallel load circuit with FET 11. Further, the FET 12 is turned off by a low level control input signal. Therefore, FET12 is
FET 5 forming a shunt path in transistor circuit 2
It also has the functions of a control FET 6 that controls on/off (operation/inoperation) of the branch channel.

The principle of threshold control of the NMOS inverter circuit shown in FIG. 4 is the same as that shown in FIG. and control circuits 1 and 2
The input threshold is controlled by the balance of the conduction ability. Note that the FET 12 of the transistor circuit 1 is removed, only the load MOSFET 11 is used, and the FET of the transistor circuit 2 is
The threshold value may be changed only by controlling the ET6. Furthermore, in FIG. 4, the FETs 6 and 12 may be depletion type to form an E/D type MOS inverter circuit. In addition, a circuit equivalent to that shown in Fig. 4 is constructed using a P-channel MOSFET.
It can also be composed of

[0024]

Effects of the Invention As described above, the input device of the present invention includes at least one controllable shunt circuit provided in at least one of the first and second transistor circuits connected in series, thereby controlling the conduction of each transistor circuit. It is configured to change the input threshold by changing the ratio of the number of channels (conducting capacity). Therefore, it is possible to connect one input device to pre-stage circuits having various effective output levels, and the overall device can be made smaller and simpler.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the principle of an input device of the present invention.

FIG. 2 is a block circuit diagram showing an embodiment in which the input device of the present invention is applied to a CMOS inverter circuit.

FIG. 3 is a circuit diagram showing a specific configuration of the CMOS inverter circuit of FIG. 2;

FIG. 4 is a circuit diagram showing an embodiment in which the input device of the present invention is applied to an NMOS inverter circuit.

[Explanation of symbols]

1...First transistor circuit 2...Second transistor circuit 3...PMOSFET 4, 4a, 4b...Shunt circuit 5, 6...MOSFET 7...Input terminal 8...Output terminal 9...Control terminal

Claims (4)

[Claims] 1. A transistor circuit comprising first and second transistor circuits connected in series to form a current path;
, at least one of the second transistor circuits outputs an output signal responsive to the input signal from a connection point between the first and second transistor circuits, and the one transistor circuit responsive to the input signal is connected to the current path. A MOSFET having a channel corresponding to the above and receiving the above input signal.
and at least one shunt circuit connected in parallel with the channel, the shunt circuit comprising two MOSFETs with channels connected in series along the shunt path, one of the MOSFETs receiving the input signal. In addition, the other MOSFET receives a control input signal for selectively forming the branch channel. 2. The other of the first and second transistor circuits has the same configuration as the one transistor circuit, and each transistor circuit is different from the other and operates complementary to the input signal. The input device according to claim 1, further comprising a conductive type MOSFET. 3. The input device according to claim 1, wherein the control input signal is a control code signal for changing an input threshold value. 4. The other of the first and second transistor circuits is an M of the same conductivity type as the one transistor circuit.
M, which is composed of OSFET and constitutes the above-mentioned current path.
2. The input device according to claim 1, wherein the OSFET is constituted by a load MOS circuit.