JPH0619682A - Full adding circuit - Google Patents

Abstract

PURPOSE:To obtain a full adding circuit which is operated at a high speed, and which is suitably constituted of a field-effect transistor, in which the number of necessary transistors for one bit can be reduced, and a power consumption can be reduced. CONSTITUTION:A one bit full adder l is constituted of P type FET P1-P3, and N type FET N1-N14. The FET P1, P2, and N14 constitute a switch part which controls a precharge operation, the FET N13 constitutes the switch part which controls an enable operation, the FET P3, and N1-N5 constitute a carry signal preparing part which inputs input data signals A1 and B1 and a carry signal C1, and outputs a carry signal C2 and an addition control signal, and the FET N6-N12 constitute an addition signal preparing part which inputs the input data signals A1 and B1, carry signal C1 and addition control signal, and outputs an addition data signal S1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder circuit, and more particularly to a full adder circuit suitable for being constituted by a field effect transistor (hereinafter abbreviated as FET).

[0002]

2. Description of the Related Art A full adder circuit formed by combining CMOS logic gates is widely used. The multi-bit full adder circuit can be configured by a 1-bit full adder whose number is equal to the number of bits.

FIG. 3 is an ethical circuit diagram showing an example of such a conventional full adder circuit. This conventional example is a 2-bit full adder circuit, which is configured to include a 1-bit full adder 3 for lower bits and a 1-bit full adder 4 for upper bits. The 1-bit full adder 3 has a NOR gate 31 and an NAN that receive input data signals A ₁ and B ₁ from the outside.
A D gate 32, a NOT gate 33 that receives the output of the NAND gate 32, a NOR gate 34 that receives the outputs of the NOT gate 33 and NOR gate 31, and a NOR
NOR gate 35 and NAND gate 36 to which the output of the gate 34 and the carry signal C ₁ from the outside are input
And a NOR gate 37 to which the output of the NAND gate 36 is input, and a NOR to which the output of the NOT gate 37 / NOR gate 35 is input and which outputs the addition data signal S ₁ to the outside.
N which outputs the carry signal C ₂ to the 1-bit full adder 4 by inputting the outputs of the gate 38 and the NAND gates 32 and 36
An AND gate 39 is provided. These 9
All two gates are CMOS ethics gates. The 1-bit full adder 4 has the same configuration as the 1-bit full adder 3, and the input data signals A ₂ and B ₂ are externally input with the carry signal C ₂ from the 1-bit full adder circuit 3 and the addition data signal S
_2. Output carry signal C ₃ to the outside.

Since the 1-bit full adder circuits 3 and 4 operate in the same manner, the operation of the 1-bit full adder circuit 3 will be described.

First, the case where the carry signal C ₁ is the ethical value "0" will be described. When both input data signals A ₁ and B ₁ are ethical value “0”, NOR gate 31 output becomes ethical value “1”, NOR gate 34 output becomes ethical value “0”, NOR gate 35 output becomes ethical value “1”. Becomes, and N
The output of the OR gate 38, that is, the addition data signal S ₁ becomes the ethical value “0”. At this time, the NAND gate 3
Both the 2 and 36 outputs become the ethical value "1", and the output of the NAND gate 39, that is, the carry signal C ₂ becomes the ethical value "0".
Becomes When one of the input data signals A ₁ and B ₁ is the ethical value “1” and the other is the ethical value “0”, NOR
The output of the gate 31 and the output of the NOT gate 33 both become the ethical value "0", the output of the NOR gate 34 becomes the ethical value "1", and the output of the NOR gate 35 and the output of the NOT gate 37 both become the ethical value "0". The data signal S ₁ has the ethical value “1”. At this time, the NAND gate 32
Since, 36 output are both ethical value "1", the carry signal C ₂ is the ethical value "0". Input data signal A ₁・ B ₁
When both are ethical values “1”, the output of the NOT gate 33 becomes the ethical value “1”, the output of the NOR gate 34 becomes the ethical value “0”, and the output of the NOR gate 35 becomes the ethical value “1”. The signal S ₁ has the ethical value “0”, and the carry signal C ₂ has the ethical value “1”.

Next, the case where the carry signal C ₁ is the ethical value "1" will be described. When both the input data signals A ₁ and B ₁ are the ethical value “0”, the output of the NOR gate 34 is the ethical value “0”, and the output of the NOR gate 35 and the NOT gate 3
Since all seven outputs have the ethical value “0”, the added data signal S ₁ has the ethical value “1”. At this time, since the NAND gates 32 and 36 both have the ethical value "1", the carry signal C ₂ has the ethical value "0". Input data signal A ₁
When _one of B ₁ is the ethical value “1” and the other is the ethical value “0”, the output of the NOR gate 34 is the ethical value “1”.
Since the output of the NOR gate 37 becomes the ethical value “1”, the added data signal S ₁ is the ethical value “0” and the carry signal C.
₂ becomes ethical value "1". When both the input data signals A ₁ and B ₁ are the ethical value “1”, the output of the NOR gate 34 is the ethical value “0”, and the outputs of the NOR gate 35 and the NOT gate 37 are both the ethical value “0”. , The addition data signal S ₁ and the carry signal C ₂ both have the ethical value "1".

FIG. 4 shows the above-mentioned input / output relationship, that is, 1
3 is a truth table showing the input / output relationship of a bit full adder in general. The input / output relationship shown in FIG. 4 is also expressed by the following mathematical formula 1.

[0008]

[Equation 1]

As is well known, a CMOS NOR gate
Each NAND gate requires 4 FETs, and also NO
The T gate requires 2 FETs. Therefore, the conventional example shown in FIG. 3 requires 32 FETs per bit. n
In a full adder circuit with the same bit, the required number of FETs is 32n
Therefore, for example, a conventional 16-bit full adder circuit has 5
Requires 12 FETs.

[0010]

As described above, since the conventional full adder circuit has a large number of required FETs per bit, it has the drawbacks of high cost and large power consumption, and complicated wiring. Since the wiring length becomes long, there is a drawback that the calculation speed is slow.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a full adder circuit which requires a small number of FETs, is economical, consumes less power, has simple wiring, and has a high operation speed. It is in.

[0012]

The full adder circuit of the present invention is
First and second switch means that are periodically and simultaneously turned on and off, a carry signal generation unit that outputs a signal of a carry calculation result, and an addition signal generation unit that outputs a signal of the addition result In the carry signal generator, the first input end is a first terminal of the power supply, the second input end is a first input data signal terminal, and the third input end is a second input. The data signal terminal, the fourth input terminal is connected to the input carry signal terminal, the output terminal is connected to the output carry signal terminal and the second terminal of the power source via the first switch means, respectively, A first input end of the addition signal generation unit is the first terminal of the power source, a second input terminal is the first input data signal terminal, and a third input end is the second input data. Signal terminal, 4th input terminal to said input carry signal terminal, 5th input terminal to said carry And a 1-bit full adder having an output end connected to the second terminal of the power source via the addition data signal terminal and the second switch means. It

Further, the carry signal generation section includes first, second, third, fourth and fifth transistors of a field effect type which is a first conductivity type. The sources of the transistors are both connected to the first input terminal, the drains are both connected to the source of the third transistor, and one and the other of the gates are connected to the second and third input terminals, respectively. The source of the transistor is connected to the first input terminal, the drain is connected to the source of the fifth transistor, and the drains of the third and fifth transistors are both connected to the output terminal of the fourth transistor. Connecting one and the other of the gates of a fifth transistor to the second and third inputs and connecting the gate of the third transistor to the fourth input.

Further, the addition signal generation unit controls the output of the addition result signal, and the sixth conductivity type field effect type sixth, seventh, eighth, ninth, and ninth conductivity types. And eleventh transistors, wherein the sources of the sixth, seventh, and eighth transistors are both at the first input terminal, and one or the other and the other of the gates are at the second or third transistor. And a fourth input terminal, the source of the ninth transistor is connected to the first input terminal, the drain is connected to the source of the tenth transistor, respectively, and the eleventh transistor is connected. The source is connected to the drain of the tenth transistor, and the drain is connected to the output terminal, and one, the other, and the other of the gates of the ninth, tenth, and eleventh transistors are connected to the second. At the third and fourth inputs Then, the first input of the output control unit is commonly to the drains of the sixth, seventh, and eighth transistors, the second input is the fifth input end, the output is the output end, or Further, the third input is connected to the first input end, respectively.

Further, the output control section is turned on from off during the period in which the first switch means is off, and thereafter, is turned on from off before turning on from the first switch means. And a twelfth transistor of the field effect type that is the first conductivity type, the source of the twelfth transistor being the first input, and the drain being the first input. The gate is connected to the output via the third switch means, and the gate is connected to the second input.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The embodiment shown in FIG. 1 is a 2-bit full adder circuit, which comprises a 1-bit full adder 1 for lower bits and a 1-bit full adder 2 for upper bits.

The 1-bit full adder 1 is a P-type FET P ₁
It is constituted by a FETn ₁ to N ₁₄ of to P ₃ and N-type.

The gates of the FETs P ₁ and P ₂ are both precharge signals bar p (bar p is a precharge signal p to be described later).
Represents a signal of the opposite phase, and is usually a bar above the p, but here it is to be preceded by a letter. same as below. ) Terminal, the source is the power supply voltage _VDD terminal,
Each is connected. The gate of the FET N ₁₄ is connected to the terminal of the precharge signal P, and the source thereof is connected to the terminal of the power supply voltage V _SS . The gate of the FET N ₁₃ is connected to the terminal of the enable signal E, and the drain thereof is connected to the drain of the FET P ₂ and the terminal of the addition data signal bar S ₁ (the same as the case of the bar P. The same applies hereinafter).

The sources of the FETs N ₁ and N ₂ are both connected to the terminal of the power supply voltage V _SS , the drains thereof are both connected to the source of the FET N ₃ , and the gates thereof are connected to the input data signal A ₁ and B ₁ terminals, respectively. The source of FETN ₄ is the power supply voltage V
_The drain is connected to the terminal of _SS and the source is connected to the source of the FET N ₅ . The drains of the FETs N ₃ and N ₅ are both connected to the gate of the FET P ₃ and the drain of the FET P ₁ . The gates of FETs N ₄ and N ₅ are input data signals A
The gate of FET N ₃ is connected to the terminal of ₁ · B ₁ and carry signal C
It is connected to the terminal of ₁ , respectively.

The sources of the FETs N ₆ , N _7, and N ₈ are both connected to the terminal for the power supply voltage V _SS , and the gates are connected to the terminals for the carry signal C ₁ and the input data signal B ₁ · A ₁ , respectively. The source of the FET N ₉ is connected to the terminal of the power supply voltage V _SS , and the drain thereof is connected to the source of the FET N ₁₀ . The source of FETN ₁₁ is the drain of FETN ₁₀ ,
The drains are respectively connected to the drains of FETP ₂ . The gates of the FETs N ₉ , N ₁₀ , N ₁₁ are connected to the input data signals A ₁ , B _1, and carry signal C ₁ .

The 1-bit full adder 2 also has the same configuration as the 1-bit full adder 1, and the input data signal A ₂ · B ₂ · added data signal bar S ₂ · carry signal C ₃ is 1-bit full adder _2. It corresponds to the input data signals A ₁ and B ₁ , the addition data signal bar S ₁ and the carry signal C ₂ of the adder ₁ . A carry signal C ₂ input from the 1-bit full adder 1 corresponds to the carry signal C ₁ of the 1-bit full adder 1.

FIG. 2 is a time chart for explaining the operation of the 1-bit full adder 1. The same applies to the 1-bit full adder, and a description thereof will be omitted.

As shown in FIG. 2, the precharge signal p has an ethical value of "1" in the section a, and a section b.c.d.e.f.
・ It is a signal that takes an ethical value of “0” in g. The precharge signal bar p is a signal having a reverse phase to the precharge signal P, as described above. The enable signal E changes from the ethical value "1" to "0" at the start of the section a, and the section b.c.
Ethics value from "0" to "1" in the middle of d ・ e ・ f ・ g ...
Is a signal that changes to.

First, the operation in the section a will be described. In this section, the carry signal C ₁ and the input data signal B ₁ are set to the ethical value “0”. FETN ₃ and N ₅ are off,
Since FETP ₁ is on, the gate of FETP ₃ · N ₁₂ is charged to the supply voltage V _DD, FETP ₃ · N ₁₂ is turned off on. FETN ₁₁ and N ₁₃ are off, and F
Since the ETP ₂ · N ₁₄ is on, the drain of the FET N ₁₃ · P ₃ has the potential of the power supply voltage V _DD (potential of the ethical value “1”).
-It is charged to the potential of V _SS (potential of ethical value "0"). Therefore, the addition data signal bar S ₁ and the carry signal C _{2 become} the ethical values “1” and “0”. In this way, the section a is a section in which the gate and drain of the FET N ₁₃ · P ₃ are precharged and set to the initial state of the operation cycle. The FETs P ₁ , P _2, and N ₁₄ operate as switches that control this precharge operation.

The section b is a calculation section when the carry signal C ₁ and the input data signal B ₁ and A ₁ are both ethical values "0". FETP ₁ is off, because FETn _{3-N 5} is turned off, the gate of FETP ₃ · N ₁₂ remains precharged in an interval a, FETP ₃ · N ₁₂ remains turned off and on. FETP ₂ · N ₁₄ is off and FETN ₆ · N ₇ · N ₈ · N ₁₁ are off,
The drains of the FETs N ₁₃ and P ₃ remain precharged in the section a, and the addition data signal bar S ₁ and the carry signal C ₂ remain at the ethical values "1" and "0".

The section c is a calculation section when the carry signal C ₁ and the input data signal B ₁ and A ₁ are both ethical values "0", "0", and "1". FETP ₁ is off and F
Since ETN ₃ · N ₅ is turned off, FETP ₃ · N ₁₂ remains off / on in the section a. Since the FET N ₁₄ is off, it remains precharged in the drain section a of the FET P ₃ and the carry signal C ₂ remains at the ethical value “0”. On the other hand, FETP ₂ is off,
Since FETN ₈ and N ₁₁ are turned on and off, FETN ₁₃
There section is on (while the enable signal E is ethical value "1"), addition data signal bars S ₁ is at the potential of the power supply voltage V _SS, that is, the ethical value "0". As shown in FIG. 2, the addition data signal S ₁ and the carry signal C ₂ are sampled at the timing T _c when the enable signal E is the ethical value “1”. The FET N ₁₃ operates as a switch that controls the enable operation. In addition, section b, d, e,
f ・ g ... _Tb・_Td・ T corresponding to the timing _Tc
The addition data signal bar S ₁ and carry signal C ₂ are sampled at _e · T _f · T _g .

Since the operation does not change even if the input data signals B ₁ and A ₁ are exchanged, the carry signal C ₁ and the input data signal B
_{Even when 1} · A ₁ is the ethical value “0”, “1”, “0”, the added data signal bar S ₁ and the carry signal C ₂ are both the ethical value “0”.

The section d is a calculation section when the carry signal C ₁ and the input data signal B ₁ and A ₁ are the ethical values "0", "1" and "1". FETP ₁ is off, FET
Since the N ₄ - N ₅ both turned ON, the gate of FETP ₃ · N ₁₂ becomes the power supply voltage V _SS, FETP ₃ · N ₁₂ is turned on and off. FETP2 · N ₁₄ is off, FET
Since N ₁₁ is turned off, the carry signal C ₂ becomes the power supply voltage V _DD.
To the electric potential of FE, that is, the ethical value becomes "1", while FE
The drain of TN ₁₃ remains precharged in the section a, and the added data signal bar S ₁ remains at the ethical value “1”.

The section e is a calculation section when the carry signal C ₁ and the input data signal B ₁ and A ₁ are the ethical values "1", "0" and "0". FETP ₁ and N ₁₄ are off,
FETN ₁ , N ₂ , N ₁₅ are turned off, and FETP ₃ , N
_{Since 12} remains off / on in the section a, the carry signal C ₂ remains at the ethical value “0”. On the other hand, FET
Since P ₂ is off and FETN ₆ and N ₁₀ are on and off, the added data signal bar S ₁ has the ethical value “0” while the FET N ₁₃ is on.

The section f is a calculation section when the carry signal C ₁ and the input data signal B ₁ and A ₁ are the ethical values "1", "0", and "1". FETP ₁ and N ₁₄ are off,
Since both FETN ₂ and N ₃ are turned on, FETP ₃
N ₁₂ is turned on and off, the carry signal C ₂ is the ethical value "1". On the other hand, the FET P ₂ is off, and the FET
Since N ₁₀ is turned off, the added data signal bar S ₁ remains at the ethical value “1”.

Since the operation does not change even if the input data signals B ₁ and A ₁ are exchanged, the carry signal C ₁ and the input data signal B ₁ and A ₁ ethical values "1", "1" and "0" are used. Even in some cases, the added data signal bar S ₁ and the carry signal C ₂ both have the ethical value "1".

The section g is a calculation section when the carry signal C ₁ and the input data signal B ₁ and A ₁ are both ethical value "1". FETP ₁ · N ₁₄ is off, FETN ₁ ·
Since both N ₁₃ are turned on, FETP ₃ and N ₁₂ are turned on.
The signal is turned off and the carry signal C ₂ becomes "1". On the other hand, F
Since the ETP ₂ is off and the FETs N ₉ , N ₁₀ and N ₁₁ are all on, the added data signal bar S ₁ has the ethical value “0”.

As described above, the 1-bit full adder 1
Certainly operates so as to satisfy the input / output relationship as a 1-bit full adder. The 1-bit full adder 1 has 17 F
It is composed of ET. If a 16-bit full adder circuit is constructed as in the embodiment shown in FIG.
The number is 272.

In the embodiment shown in FIG. 1, the FET
Instead of _{P 1 · P 2 · N 13} · N 14, it is also possible to use other switching elements. Also, the input data signal B ₁ · A
₁ and FETN ₁ · N ₂ connection, or FETN ₅ ·
The operation does not change even if the connection with N ₄ is reversed from that shown in FIG. Further, the connection between the carry signal C ₁ and the input data signal B ₁ · A ₁ and the FETs N ₆ , N _7, and N ₈ or the connection with the FETs N ₁₁ , N ₁₀ and N ₉ is as shown in FIG. The operation does not change even if they are replaced with each other.

FIG. 5 is a circuit diagram showing another embodiment of the present invention. This embodiment is a 2-bit full adder circuit including a 1-bit full adder 5 for lower bits and a 1-bit full adder for upper bits.
The bit full adder 6 is provided. The 1-bit full adders 5 and 6 correspond to the 1-bit full adders 1 and 2 in the embodiment shown in FIG. 1-bit full adder 1
In place of the FETs N ₁₂ and N ₁₃ in, the 1-bit full adder 5 includes FETs N ₁₂ , N ₁₃ and N ₁₅ .

The source of FET N ₁₂ is FET N ₆ and N _7.
The drain of · N _8, each drain terminal of the addition data signal bars S ₁ of the drain FETP ₂ · N _11, gates F
It is connected to one end of the source / drain of ETN _{13 and} the drain of FET N ₁₅ , respectively. Of FETN ₁₃ ,
The remaining one end of the source drain is connected to the drain of the FET P ₁ and the gate is connected to the terminal of the enable signal E. The source and the gate of the FET N ₁₅ are connected to the power supply voltage V _SS terminal and the precharge signal p terminal, respectively. Incidentally, the remaining FETn ₁ to N _11, N
₁₄ , P _{1 to} P ₃ are connected by FET N ₁₁₂ , N ₁₁₃ , N
Except for the connection with ₁₁₅ , it is the same as the connection in the 1-bit full adder 1.

The time chart showing the operation of the 1-bit full adder 5 is the same as FIG. The FETN ₁₁₅ operates as a switch that controls the precharge operation of precharging the gate of the FETN ₁₁₂ to the power supply voltage V _SS and turning off the FETN ₁₁₂ to set the operation cycle to the initial state in the section a.

The FET N ₁₁₃ operates in the sections c and e, that is, the carry signal C ₁ and the input data signal B ₁
When _one of A ₁ has an ethical value of “1” and the other two have an ethical value of “0”, FETN ₆ · N ₇ ·
When any one of N ₈ is turned on, the drain potential of the FET P ₁ , that is, the potential of the power supply voltage V _DD is set to the FET N.
_By transmitting it to the gate of ₁₁₂ , it operates as a switch for controlling the enable operation of setting the added data signal S ₁ to the ethical value “0”.

[0039]

As described above, in the full adder circuit of the present invention, the number of required FETs per bit is small and the wiring is simple. Further, since it is a dynamic operation, the through current between power supplies when the signal level changes is generated. Economic because there is no IC
It is suitable for high efficiency, has a high calculation speed, and has a small power consumption effect.

These effects become more remarkable as the number of bits increases.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the 1-bit full adder 1 in FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a truth table showing the input / output relationship of a 1-bit full adder in general.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

1 ・ 2 ・ 3 ・ 4 ・ 5 ・ 6 1-bit full adder P _{1 to} P ₃・ N _{1 to} N ₁₄・ N ₁₁₂・ N ₁₁₃・ N ₁₁₅
FET 31 ・ 34 ・ 35 ・ 38 NOR gate 32 ・ 36 ・ 39 NAND gate 33 ・ 37 NOT gate C ₁・ C ₂・ C ₃ Carry signal A ₁・ A ₂・ B ₁・ B ₂ Input data signal S ₁・S ₂ bar S ₁ bar S ₂ addition data signal p bar p precharge signal E enable signal V _DD V _SS power supply voltage a to _g section T _{b to} T _g timing

Claims (8)

[Claims] 1. A first and second switch means which are periodically and simultaneously turned on and off, a carry signal generation section which outputs a signal of a carry calculation result, and a signal of an addition result. An addition signal generation unit, the first input terminal of the carry signal generation unit, the first terminal of the power supply, the second input terminal to the first input data signal terminal,
The third input end serves as the second input data signal terminal, the fourth input end serves as the input carry signal terminal, and the output end serves as the output carry signal terminal and the first switch means through the first switch means. And a second input terminal connected to the first input data signal terminal and a second input terminal connected to the second terminal, respectively. The input end of the second input data signal terminal, the fourth input end to the input carry signal terminal, the fifth input end to the output end of the carry signal generator, and the output end A full adder circuit comprising a 1-bit full adder connected to the second terminal of the power source via the data signal terminal and the second switch means, respectively. 2. The carry signal generation section includes first, second, third, fourth and fifth transistors of a field effect type which is a first conductivity type. Of the transistor,
The sources are connected to the first input terminal, the drain is connected to the source of the third transistor, and one and the other of the gates are connected to the second and third input terminals, respectively.
A source of the fourth transistor is connected to the first input terminal, a drain thereof is connected to a source of the fifth transistor, and drains of the third and fifth transistors are both connected to an output terminal, One and the other of the gates of the fourth and fifth transistors are connected to the second and third input ends, and the gate of the third transistor is connected to the fourth input end. The full adder circuit according to the claims and claim 1. 3. The output signal control unit for controlling the signal output of the addition result by the addition signal generation unit, and the sixth, seventh, eighth, ninth and ninth electric field effect type which is the first conductivity type. And eleventh transistors, wherein the sources of the sixth, seventh, and eighth transistors are both at the first input terminal, and one or the other and the other of the gates are at the second or third transistor. And a fourth input terminal, the source of the ninth transistor is connected to the first input terminal, the drain is connected to the source of the tenth transistor, respectively, and the eleventh transistor is connected. , The source is connected to the drain of the tenth transistor, and the drain is connected to the output terminal, and one, the other, and the other of the gates of the ninth, tenth, and eleventh transistors are connected to the second. Connect to the third and fourth inputs The first input of the output control unit is commonly to the drains of the sixth, seventh, and eighth transistors, the second input is the fifth input end, the output is the output end, or further, The full adder circuit according to claim 1, wherein the three inputs are respectively connected to the first input terminal. 4. The carry signal generation section includes first, second, third, fourth and fifth transistors of field effect type which are the first conductivity type, and the first and second transistors. Of the fourth transistor, the sources thereof are connected to the first input terminal, the drains thereof are both connected to the source of the third transistor, and one and the other of the gates thereof are connected to the second and third input terminals, respectively. The source of the transistor is the first input terminal,
The drain is connected to the source of the fifth transistor, the drains of the third and fifth transistors are both connected to the output terminal, and one and the other of the gates of the fourth and fifth transistors are connected to the An output control unit that is connected to the second and third input terminals, the gate of the third transistor is connected to the fourth input terminal, and that the addition signal generation unit determines the signal output of the addition result; And a field effect type sixth, seventh, eighth, ninth, tenth, and eleventh transistor that is the first conductivity type, of the sixth, seventh, and eighth transistors, The sources are connected to the first input terminal, and one, the other, and the other of the gates are connected to the second, third, and fourth input terminals, respectively, and the source of the ninth transistor is connected to the first input terminal. At the input end of the drain of the tenth A source of the transistor, a source of the eleventh transistor, a source of the tenth transistor, a drain of the tenth transistor, and a drain of the ninth transistor, the tenth transistor and the eleventh transistor, respectively. One, the other, and the other of the gates of the transistors are connected to the second, third, and fourth input terminals, and the first input of the output control unit is connected to the sixth, seventh, and eighth transistors. The second input is commonly connected to the drain, the second input is connected to the fifth input end, the output is connected to the output end, or further, the third input is connected to the first input end, respectively. The full adder circuit according to claim 1. 5. The output control section is switched from off to on during the period when the first switch means is off, and then from on to off before the first switch means is switched from off to on. And a twelfth transistor of the field effect type that is the first conductivity type, the source of the transistor to the tenth is the first input, and the drain is the 4. The full adder circuit according to claim 3, wherein a gate is connected to the output via the third switch means, and a gate is connected to the second input. 6. The output control section is switched from off to on during the period when the first switch means is off, and thereafter from on to off before the first switch means is switched from off to on. A third switch means, a fourth switch means that is turned on / off at the same time as the first switch means, and a field effect type twelfth transistor that is the first conductivity type. A twelfth transistor has a source for the first input, a drain for the output, and a gate for the second input through the third switch means and the fourth input for the fourth switch means. The full adder circuit according to claim 3, wherein the full adder circuit is connected to each of the three inputs. 7. The output control section is switched from off to on during the period in which the first switch means is off, and then from on to off before being switched from off to on of the first switch means. And a twelfth transistor of the field effect type which is the first conductivity type, the source of the twelfth transistor being the first input, and the drain being the first input. 5. The full adder circuit according to claim 4, wherein a gate is connected to the second input via the third switch means, and a gate is connected to the second input. 8. The output control unit is switched from OFF to ON during the period in which the first switch means is OFF, and thereafter is switched from ON to OFF before being switched from OFF to ON of the first switch means. A third switch means, a fourth switch means that is turned on / off at the same time as the first switch means, and a field effect type twelfth transistor that is the first conductivity type. A twelfth transistor has a source for the first input, a drain for the output, and a gate for the second input through the third switch means and the fourth input for the fourth switch means. The full adder circuit according to claim 4, wherein the full adder circuit is connected to each of the three inputs.