CN111654280B - One-bit full adder based on three-input TFET device - Google Patents

One-bit full adder based on three-input TFET device Download PDF

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CN111654280B
CN111654280B CN202010380082.2A CN202010380082A CN111654280B CN 111654280 B CN111654280 B CN 111654280B CN 202010380082 A CN202010380082 A CN 202010380082A CN 111654280 B CN111654280 B CN 111654280B
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tfet
tube
grid electrode
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electrode
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CN111654280A (en
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胡建平
高晗晔
叶浩
张子豪
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Shenzhen Wanzhida Technology Co ltd
Shenzhen Yuanshixin Intelligent Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination

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  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a one-bit full adder based on a three-input TFET device, which comprises a fourteenth TFET tube, wherein seven TFET tubes are realized by adopting a P-type three-input TFET device, seven TFET tubes are realized by adopting an N-type three-input TFET device, when any two or three accessed input signals in three grid electrodes of the N-type three-input TFET device are 1, the source electrode and the drain electrode of the N-type three-input TFET device are conducted, and when any two or three accessed input signals in three grid electrodes of the P-type three-input TFET device are 0, the source electrode and the drain electrode of the P-type three-input TFET device are conducted; the circuit has the advantages of simpler circuit structure, smaller circuit area and power consumption and higher speed.

Description

One-bit full adder based on three-input TFET device
Technical Field
The invention relates to a one-bit full adder, in particular to a one-bit full adder based on a three-input TFET device.
Background
With the rapid development of integrated circuit technology, the conventional CMOS process has not been able to meet the increasing demands of miniaturization, low power consumption, etc. of the current digital circuits. In recent years, some new nano-devices have emerged that can replace CMOS devices. Among them, TFET (tunnelingfield effect transistor ) devices, unlike current injection mechanisms of conventional CMOS devices, exhibit good subthreshold swing, and some logic circuits implemented based on TFET devices also exhibit some characteristics that are superior to CMOS circuits. TFET devices are among the most promising devices for application in integrated circuit design in place of CMOS devices.
The full adder is used as a basic unit of an electronic system, can complete addition, can participate in operations such as subtraction, multiplication and division, and is widely applied to large-scale integrated circuit designs. The full adder is an important unit of a digital signal processor, a microprocessor and a singlechip system with higher performance requirements, and the influence of the performance of the full adder on the performance of the whole system is particularly important. One-bit full adders are widely used in the carry critical path of multi-bit adders, one of the important factors affecting the performance of multi-bit adders.
A conventional one-bit full adder circuit based on a CMOS device is shown in fig. 1. The one-bit full adder is composed of 22P-type CMOS transistors and 22N-type CMOS transistors. The one-bit full adder calculates output through a logic equation, adopts a static complementary gate-level circuit structure, and generates carry signals and summation signals by three logic blocks to generate six-level delay. More P-type CMOS transistors are stacked between the two output signals, and the load capacitance of the carry signal is larger. The situation leads the number of the CMOS transistors used by the one-bit full adder to be more, the circuit structure to be more complex, the circuit area and the power consumption to be larger, and the speed to be slower.
Disclosure of Invention
The invention aims to solve the technical problem of providing a one-bit full adder based on a three-input TFET device, which has the advantages of simpler circuit structure, smaller circuit area and power consumption and higher speed.
The technical scheme adopted for solving the technical problems is as follows: a one-bit full adder based on a three-input TFET device, which comprises a first TFET tube, a second TFET tube, a third TFET tube, a fourth TFET tube, a fifth TFET tube, a sixth TFET tube, a seventh TFET tube, an eighth TFET tube, a ninth TFET tube, a tenth TFET tube, an eleventh TFET tube, a twelfth TFET tube and a fourteenth TFET tube, wherein the first TFET tube, the third TFET tube, the fifth TFET tube, the seventh TFET tube, the ninth TFET tube, the eleventh TFET tube and the thirteenth TFET tube are respectively realized by adopting a P-type three-input TFET device, the second TFET tube, the fourth TFET tube, the sixth TFET tube, the eighth TFET tube, the tenth TFET tube, the twelfth TFET tube and the thirteenth TFET tube are respectively realized by adopting a N-type three-input TFET device, the N-type three-input TFET device is provided with a first grid electrode, a second grid electrode, a third grid electrode, a source electrode and a drain electrode, when any two of the first grid electrode, the second grid electrode and the third grid electrode of the N-type three-input TFET device are connected with input signals 1, when the other one of the first grid electrode, the second grid electrode and the third grid electrode is connected with the input signals 0 or the three connected input signals are all 1, the source electrode and the drain electrode of the N-type three-input TFET device are conducted, the P-type three-input TFET device is provided with the first grid electrode, the second grid electrode, the third grid electrode, the source electrode and the drain electrode, when any two of the first grid electrode, the second grid electrode and the third grid electrode of the P-type three-input TFET device are connected with the input signals 0, and when the other one of the first grid electrode, the second grid electrode and the third grid electrode is connected with the input signals 1 or the three connected with the input signals 0; the source of the first TFET tube, the source of the third TFET tube, the source of the fifth TFET tube, the source of the seventh TFET tube, the source of the ninth TFET tube, the source of the eleventh TFET tube and the source of the thirteenth TFET tube are all connected with a power supply, the source of the second TFET tube, the source of the fourth TFET tube, the source of the sixth TFET tube, the source of the eighth TFET tube, the source of the tenth TFET tube, the source of the twelfth TFET tube and the source of the fourteenth TFET tube are all grounded, the first grid electrode of the first TFET tube, the first grid electrode of the second TFET tube, the first grid electrode of the fifth TFET tube, the second grid electrode of the fifth TFET tube, the third grid electrode of the fifth TFET tube, the first grid electrode of the sixth TFET tube, the second grid electrode of the sixth TFET tube, the third grid electrode of the sixth TFET tube, the first grid electrode of the eleventh TFET tube and the second grid electrode of the twelfth TFET tube are connected and the connecting end is the first input end of the one-bit full adder, the first input end of the one-bit full adder is used for accessing a first input signal, the second grid electrode of the first TFET pipe, the second grid electrode of the second TFET pipe, the first grid electrode of the seventh TFET pipe, the second grid electrode of the eighth TFET pipe, the first grid electrode of the ninth TFET pipe, the second grid electrode of the ninth TFET pipe, the third grid electrode of the ninth TFET pipe, the first grid electrode of the tenth TFET pipe, the second grid electrode of the tenth TFET pipe and the third grid electrode of the tenth TFET pipe are connected, the connecting end of the first TFET pipe, the second input end of the one-bit full adder is used for accessing a second input signal, the third grid electrode of the first TFET tube, the third grid electrode of the second TFET tube, the second grid electrode of the seventh TFET tube, the third grid electrode of the eighth TFET tube, the second grid electrode of the eleventh TFET tube, the third grid electrode of the twelfth TFET tube, the second grid electrode of the thirteenth TFET tube and the second grid electrode of the fourteenth TFET tube are connected, the connecting end of the second grid electrode of the thirteenth TFET tube and the second grid electrode of the thirteenth TFET tube is the carry input end of the one-bit full adder, the carry input end of the one-bit full adder is used for accessing a carry signal output in low order, the drain electrode of the first TFET tube, the drain electrode of the second TFET tube, the first grid electrode of the third TFET tube, the second grid electrode of the third TFET tube, the first grid electrode of the fourth TFET tube, the second grid electrode of the fourth TFET tube and the third grid electrode of the fourth TFET tube are connected, the drain electrode of the third TFET tube is connected with the drain electrode of the fourth TFET tube, the connection end of the drain electrode of the fourth TFET tube is the carry output end of the one-bit full adder and is used for outputting a carry signal to high position, the drain electrode of the fifth TFET tube, the drain electrode of the sixth TFET tube, the third grid electrode of the seventh TFET tube and the first grid electrode of the eighth TFET tube are connected, the drain electrode of the seventh TFET tube, the drain electrode of the eighth TFET tube, the first grid electrode of the thirteenth TFET tube and the third grid electrode of the fourteenth TFET tube are connected, the drain electrode of the ninth TFET tube, the drain electrode of the tenth TFET tube, the third grid electrode of the eleventh TFET tube and the first grid electrode of the twelfth TFET tube are connected, the drain electrode of the eleventh TFET tube, the third grid electrode of the thirteenth TFET tube and the fourth TFET tube are connected, the drain electrode of the thirteenth TFET tube is connected with the drain electrode of the fourteenth TFET tube, the connection end of the drain electrode is the sum output end of the one-bit full adder, and the sum output end of the one-bit full adder is used for outputting a sum signal.
Compared with the prior art, the invention has the advantages that the one-bit full adder is constructed by the first TFET tube, the second TFET tube, the third TFET tube, the fourth TFET tube, the fifth TFET tube, the sixth TFET tube, the seventh TFET tube, the eighth TFET tube, the ninth TFET tube, the tenth TFET tube, the eleventh TFET tube, the twelfth TFET tube, the thirteenth TFET tube and the fourteenth TFET tube, the first TFET tube, the third TFET tube, the fifth TFET tube, the seventh TFET tube, the ninth TFET tube, the eleventh TFET tube and the thirteenth TFET tube are respectively realized by adopting P-type three-input TFET devices, the second TFET tube, the fourth TFET tube, the sixth TFET tube, the eighth TFET tube, the tenth TFET tube, the twelfth TFET tube and the fourteenth TFET tube are respectively realized by adopting N-type three-input TFET devices, the N-type three-input TFET device is provided with a first grid electrode, a second grid electrode, a third grid electrode, a source electrode and a drain electrode, when any two of the first grid electrode, the second grid electrode and the third grid electrode of the N-type three-input TFET device are connected with input signals of 1, and when the other one of the first grid electrode, the second grid electrode and the third grid electrode is connected with the input signals of 0, or when all the three connected input signals are 1, the source electrode and the drain electrode of the N-type three-input TFET device are connected with each other, the P-type three-input TFET device is provided with the first grid electrode, the second grid electrode, the third grid electrode, the source electrode and the drain electrode, and when any two of the first grid electrode, the second grid electrode and the third grid electrode of the P-type three-input TFET device are connected with the input signals of 0, and when the other one of the first grid electrode, the second grid electrode and the third grid electrode is connected with the input signals of 1, or the three connected input signals are all 0, the source electrode and the P-type three TFET device are connected with each other; when the first input signal A accessed by the first input end of the one-bit full adder, the second input signal B accessed by the second input end and the carry signal C accessed by the carry input end are both 1, the carry output end of the one-bit full adder is pulled high at the moment because the second TFET tube and the third TFET tube are conducted, the carry output end level signal of the one-bit full adder outputs high level 1, and the sum output end of the one-bit full adder is pulled high because the sixth TFET tube, the eighth TFET tube, the tenth TFET tube, the twelfth TFET tube and the thirteenth TFET tube are conducted at the moment, and the sum output end level signal of the one-bit full adder is pulled high, and the sum output end of the one-bit full adder outputs high level 1; when the first input signal A accessed by the first input end of the one-bit full adder, the second input signal B accessed by the second input end and the carry signal C accessed by the carry input end are both 0, the carry output end of the one-bit full adder is pulled down due to the conduction of the first TFET tube and the fourth TFET tube, the carry output end level signal of the one-bit full adder outputs low level 0, and the sum output end of the one-bit full adder is pulled down due to the conduction of the fifth TFET tube, the seventh TFET tube, the ninth TFET tube, the eleventh TFET tube and the fourteenth TFET tube, the sum output end level signal of the one-bit full adder is pulled down, and the sum output end of the one-bit full adder outputs low level 0; when the first input signal A accessed by the first input end of the one-bit full adder is 0, the second input signal B accessed by the second input end and the carry signal C accessed by the carry input end are 1, the carry output end of the one-bit full adder is pulled high because the second TFET tube and the third TFET tube are conducted, the carry output end of the one-bit full adder outputs high level 1, and the sum output end of the one-bit full adder is pulled low because the fifth TFET tube, the eighth TFET tube, the tenth TFET tube, the eleventh TFET tube and the fourteenth TFET tube are conducted at the moment, the sum output end level signal of the one-bit full adder is pulled low, and the sum output end of the one-bit full adder outputs low level 0; when the second input signal B accessed by the second input end of the one-bit full adder is 0, the first input signal A accessed by the first input end and the carry signal C accessed by the carry input end are 1, the carry output end of the one-bit full adder is pulled high because the second TFET tube and the third TFET tube are conducted, the carry output end of the one-bit full adder outputs high level 1, and the sum output end of the one-bit full adder is pulled low because the sixth TFET tube, the seventh TFET tube, the ninth TFET tube, the twelfth TFET tube and the fourteenth TFET tube are conducted at the moment, the sum output end level signal of the one-bit full adder is pulled low, and the sum output end of the one-bit full adder outputs low level 0; when the carry signal C accessed by the carry input end of the one-bit full adder is 0, the first input signal A accessed by the first input end and the second input signal B accessed by the second input end are 1, the carry output end of the one-bit full adder is pulled high because the second TFET tube and the third TFET tube are conducted, the carry output end of the one-bit full adder outputs high level 1, and the sum output end of the one-bit full adder is pulled low because the sixth TFET tube, the seventh TFET tube, the tenth TFET tube, the eleventh TFET tube and the fourteenth TFET tube are conducted at the moment, the sum output end level signal of the one-bit full adder is pulled low, and the sum output end of the one-bit full adder outputs low level 0; when a first input signal A accessed by a first input end of the one-bit full adder is 1, a second input signal B accessed by a second input end and a carry signal C accessed by a carry input end are 0, for the carry output end of the one-bit full adder, the carry output end level signal of the one-bit full adder is pulled down because a first TFET tube and a fourth TFET tube are conducted, the carry output end of the one-bit full adder outputs a low level 0, and for the sum output end of the one-bit full adder, the sum output end level signal of the one-bit full adder is pulled up because a sixth TFET tube, a seventh TFET tube, a ninth TFET tube, a twelfth TFET tube and a thirteenth TFET tube are conducted at the moment; when the second input signal B accessed by the second input end of the one-bit full adder is 1, the first input signal A accessed by the first input end and the carry signal C accessed by the carry input end are 0, the carry output end of the one-bit full adder is pulled down due to the conduction of the first TFET tube and the fourth TFET tube, the carry output end of the one-bit full adder outputs a low level 0, and the sum output end of the one-bit full adder is pulled up due to the conduction of the fifth TFET tube, the eighth TFET tube, the tenth TFET tube, the eleventh TFET tube and the thirteenth TFET tube, the sum output end of the one-bit full adder outputs a high level 0 due to the conduction of the first TFET tube and the fourth TFET tube; when the carry signal C accessed by the carry input end of the one-bit full adder is 1, the first input signal A accessed by the first input end and the second input signal B accessed by the second input end are 0, the carry output end of the one-bit full adder is pulled down because the first TFET tube and the fourth TFET tube are conducted, the carry output end of the one-bit full adder outputs a low level 0, and the sum output end of the one-bit full adder is pulled up because the fifth TFET tube, the eighth TFET tube, the ninth TFET tube, the twelfth TFET tube and the thirteenth TFET tube are conducted at the moment, the sum output end of the one-bit full adder is pulled up, and the sum output end of the one-bit full adder outputs a high level 0; therefore, the one-bit full adder can completely realize the corresponding logic function, realizes the full adder function through fourteen TFET tubes, has simpler circuit structure, smaller circuit area and power consumption and higher speed.
Drawings
FIG. 1 is a circuit diagram of a conventional one-bit full adder based on a CMOS device;
fig. 2 is a circuit diagram of a one-bit full adder based on a three-input TFET device of the present invention;
fig. 3 is a simulated waveform diagram of a bsiimg standard process based on a one-bit full adder of a three-input TFET device of the present invention at standard voltage (1 v).
Detailed Description
The invention is described in further detail below with reference to the embodiments of the drawings.
Examples: as shown in fig. 2, the one-bit full adder based on the three-input TFET device comprises a first TFET tube M1, a second TFET tube M2, a third TFET tube M3, a fourth TFET tube M4, a fifth TFET tube M5, a sixth TFET tube M6, a seventh TFET tube M7, an eighth TFET tube M8, a ninth TFET tube M9, a tenth TFET tube M10, an eleventh TFET tube M11, a twelfth TFET tube M12, a thirteenth TFET tube M13 and a fourteenth TFET tube M14, wherein the first TFET tube M1, the third TFET tube M3, the fifth TFET tube M5, the seventh TFET tube M7, the ninth TFET tube M9, the eleventh TFET tube M11 and the thirteenth TFET tube M13 are respectively implemented by P-type three-input TFET devices, the second TFET tube M2, the fourth TFET tube M4, the sixth TFET tube M6, the eighth TFET tube M8, the tenth TFET tube M10, the tenth TFET tube M14 are respectively implemented by P-type three-input TFET devices, the N-type three-input TFET device is provided with a first grid electrode, a second grid electrode, a third grid electrode, a source electrode and a drain electrode, when any two of the first grid electrode, the second grid electrode and the third grid electrode of the N-type three-input TFET device are 1, the other one of the first grid electrode, the second grid electrode and the third grid electrode is 0, or all of the three input signals are 1, the source electrode and the drain electrode of the N-type three-input TFET device are conducted, the P-type three-input TFET device is provided with the first grid electrode, the second grid electrode, the third grid electrode, the source electrode and the drain electrode, and when any two of the first grid electrode, the second grid electrode and the third grid electrode of the P-type three-input TFET device are 0, the other one of the first grid electrode, the second grid electrode and the third grid electrode is 1, or all of the three input signals are 0, the source electrode and the drain electrode of the P-type three-input TFET device are conducted; the source of the first TFET tube M1, the source of the third TFET tube M3, the source of the fifth TFET tube M5, the source of the seventh TFET tube M7, the source of the ninth TFET tube M9, the source of the eleventh TFET tube M11 and the source of the thirteenth TFET tube M13 are all connected with the power supply VDD, the source of the second TFET tube M2, the source of the fourth TFET tube M4, the source of the sixth TFET tube M6, the source of the eighth TFET tube M8, the source of the tenth TFET tube M10, the source of the twelfth TFET tube M12 and the source of the fourteenth TFET tube M14 are all grounded, the first gate of the first TFET tube M1, the first gate of the second TFET tube M2, the first gate of the fifth TFET tube M5, the second gate of the fifth TFET tube M5, the first gate of the sixth TFET tube M6, the second gate of the sixth TFET tube M6, the sixth TFET tube M12 and the fourth TFET tube M6 are all connected with the first gate of the eleventh TFET tube M12 and the tenth TFET tube 11, the first input end of the one-bit full adder is used for accessing a first input signal A, the second grid electrode of the first TFET pipe M1, the second grid electrode of the second TFET pipe M2, the first grid electrode of the seventh TFET pipe M7, the second grid electrode of the eighth TFET pipe M8, the first grid electrode of the ninth TFET pipe M9, the second grid electrode of the ninth TFET pipe M9, the first grid electrode of the tenth TFET pipe M10, the second grid electrode of the tenth TFET pipe M10 and the third grid electrode of the tenth TFET pipe M10 are connected, the connecting end of the first TFET pipe M1 and the third grid electrode of the tenth TFET pipe M10 is the second input end of the one-bit full adder, the second input end of the one-bit full adder is used for accessing a second input signal B, the third grid electrode of the first TFET pipe M1, the third grid electrode of the second TFET pipe M2, the second grid electrode of the seventh TFET pipe M7, the third grid electrode of the eighth TFET pipe M8, the third grid electrode of the eleventh TFET pipe M9, the third grid electrode of the tenth TFET pipe M11 and the third grid electrode of the twelfth TFET pipe M12 are connected, the second grid of the thirteenth TFET tube M13 is connected with the second grid of the fourteenth TFET tube M14, the connection end of the second grid is the carry input end of a one-bit full adder, the carry input end of the one-bit full adder is used for accessing the carry signal C output by low bits, the drain electrode of the first TFET tube M1, the drain electrode of the second TFET tube M2, the first grid of the third TFET tube M3, the second grid of the third TFET tube M3, the first grid of the fourth TFET tube M4, the second grid of the fourth TFET tube M4 and the third grid of the fourth TFET tube M4 are connected, the drain electrode of the third TFET tube M3 is connected with the drain electrode of the fourth TFET tube M4, the connection end of the one-bit full adder is used for outputting the carry signal CO to high bits, the drain of the fifth TFET pipe M5, the drain of the sixth TFET pipe M6, the third gate of the seventh TFET pipe M7, and the first gate of the eighth TFET pipe M8 are connected, the drain of the seventh TFET pipe M7, the drain of the eighth TFET pipe M8, the first gate of the thirteenth TFET pipe M13, and the third gate of the fourteenth TFET pipe M14 are connected, the drain of the ninth TFET pipe M9, the drain of the tenth TFET pipe M10, the third gate of the eleventh TFET pipe M11, and the first gate of the twelfth TFET pipe M12, the drain of the eleventh TFET pipe M11, the third gate of the thirteenth TFET pipe M13, and the first gate of the fourteenth TFET pipe M14 are connected, and the connection ends thereof are the sum output ends of a one-bit full adder, the sum output ends of the one-bit full adder being used for outputting the sum signal S.
In this embodiment, the N-type three-input TFET device is implemented by using an N-type three-input multiple-logic device disclosed in the chinese patent application with publication number CN110379851 and entitled three-input multiple-logic device based on TFET, where a first metal gate of the N-type three-input multiple-logic device is a first gate of the N-type three-input TFET device, a second metal gate is a second gate of the N-type three-input TFET device, a third metal gate is a third gate of the N-type three-input TFET device, a source region is a source of the N-type three-input TFET device, and a drain region is a drain of the N-type three-input TFET device; the P-type three-input TFET device is realized by adopting a P-type three-input multiple logic device disclosed in a Chinese patent application with a publication number of CN110379851 and a name of a three-input multiple logic device based on the TFET, wherein a first metal gate of the P-type three-input multiple logic device is a first gate of the P-type three-input TFET device, a second metal gate of the P-type three-input TFET device is a second gate of the P-type three-input TFET device, a third metal gate of the P-type three-input TFET device is a third gate of the P-type three-input TFET device, a source region is a source electrode of the P-type three-input TFET device, and a drain region is a drain electrode of the P-type three-input TFET device.
The one-bit full adder based on the three-input TFET device of the invention is simulated based on the BSIMIMG standard process under the standard voltage (1 v), and a simulation waveform diagram is shown in figure 3. In fig. 3, a V (a) curve represents a first input signal a, a V (B) curve represents a second input signal B, a V (CI) curve represents a carry signal C, a V (S) curve represents an output sum signal S, and a V (CO) curve represents an output carry signal CO. Analysis of fig. 3 shows that: when the three input signals of the first input signal A, the second input signal B and the carry signal C are all 0, the output sum signal S is 0, and the output carry signal CO is 0; when any two of the three input signals of the first input signal A, the second input signal B and the carry signal C are 0 and the other one is 1, the output sum signal S is 1, and the output carry signal CO is 0; when any two of the three input signals of the first input signal A, the second input signal B and the carry signal C are 1 and the other one is 0, the output sum signal S is 0, and the output carry signal CO is 1; when the three input signals of the first input signal a, the second input signal B and the carry signal C are all "1", the output sum signal S is "1", and the output carry signal CO is "1". It can be seen that the one-bit full adder based on the three-input TFET device has correct working logic.
Under the condition that the input frequency is 0.5MHz in the BSIMIMG standard process, the performance of the one-bit full adder based on the three-input TFET device (called the full adder of the invention for short) of the invention is compared with that of the one-bit full adder based on the CMOS device of the prior art shown in figure 1 (called the traditional logic full adder for short), and specific comparison data are shown in table 1.
TABLE 1
Analysis of the data in table 1 can yield:in contrast to the conventional logic full adder of the present invention,crystal bodyThe number of the pipes is reduced by 30, the delay is reduced by 63.33%, the average total power consumption is reduced by 49.96%, and the power consumption delay product is reduced by 36.78%.
Under the condition that the input frequency is 1MHz in the BSIMIMG standard process, the performance of the one-bit full adder based on the three-input TFET device (called the full adder of the invention for short) of the invention is compared with that of the one-bit full adder based on the CMOS device of the prior art shown in figure 1 (called the traditional logic full adder for short), and specific comparison data are shown in table 2.
TABLE 2
Analysis of the data in table 2 can yield: the book is provided withCompared with the traditional logic full adder,the number of transistors is reduced by 30, the delay is reduced by 58.33%, the average total power consumption is reduced by 51.60%, and the power consumption delay product is reduced by 32.73%.
Under the condition that the input frequency is 1MHz in the BSIMIMG standard process, the performance of the one-bit full adder based on the three-input TFET device (called the full adder of the invention for short) of the invention is compared with that of the one-bit full adder based on the CMOS device of the prior art shown in figure 1 (called the traditional logic full adder for short), and specific comparison data are shown in table 3.
TABLE 3 Table 3
Analysis of the data in table 3 can yield:in contrast to the conventional logic full adder of the present invention,the number of transistors is reduced by 30, the average total power consumption is reduced by 58.98%, and the power consumption delay product is reduced by 27.44%.
Under the condition that the input frequency is 10MHz in the BSIMIMG standard process, the performance of the one-bit full adder based on the three-input TFET device (called the full adder of the invention for short) of the invention is compared with that of the one-bit full adder based on the CMOS device of the prior art shown in figure 1 (called the traditional logic full adder for short), and specific comparison data are shown in table 4.
TABLE 4 Table 4
Analysis of the data in table 4 can yield:in contrast to the conventional logic full adder of the present invention,the number of transistors is reduced by 30, the average total power consumption is reduced by 60.03%, and the power consumption delay product is reduced by 20.63%.
Compared with the existing one-bit full adder based on the CMOS device, the one-bit full adder based on the three-input TFET device has the advantages that the number of transistors required by the circuit is reduced by 30, and the circuit power consumption and the power consumption delay product are obviously optimized under the condition of not affecting the circuit function.

Claims (1)

1. The one-bit full adder based on the three-input TFET device is characterized by comprising a first TFET tube, a second TFET tube, a third TFET tube, a fourth TFET tube, a fifth TFET tube, a sixth TFET tube, a seventh TFET tube, an eighth TFET tube, a ninth TFET tube, a tenth TFET tube, an eleventh TFET tube, a twelfth TFET tube, a thirteenth TFET tube and a fourteenth TFET tube, wherein the first TFET tube, the third TFET tube, the fifth TFET tube, the seventh TFET tube, the ninth TFET tube, the eleventh TFET tube and the thirteenth TFET tube are respectively realized by adopting a P-type three-input TFET device, the second TFET tube, the fourth TFET tube, the sixth TFET tube, the eighth TFET tube, the tenth TFET tube, the twelfth TFET tube and the thirteenth TFET tube are respectively realized by adopting a N-type three-input TFET device, the N-type three-input TFET device is provided with a first grid electrode, a second grid electrode, a third grid electrode, a source electrode and a drain electrode, when any two of the first grid electrode, the second grid electrode and the third grid electrode of the N-type three-input TFET device are connected with input signals 1, when the other one of the first grid electrode, the second grid electrode and the third grid electrode is connected with the input signals 0 or the three connected input signals are all 1, the source electrode and the drain electrode of the N-type three-input TFET device are conducted, the P-type three-input TFET device is provided with the first grid electrode, the second grid electrode, the third grid electrode, the source electrode and the drain electrode, when any two of the first grid electrode, the second grid electrode and the third grid electrode of the P-type three-input TFET device are connected with the input signals 0, and when the other one of the first grid electrode, the second grid electrode and the third grid electrode is connected with the input signals 1 or the three connected with the input signals 0;
the source of the first TFET tube, the source of the third TFET tube, the source of the fifth TFET tube, the source of the seventh TFET tube, the source of the ninth TFET tube, the source of the eleventh TFET tube and the source of the thirteenth TFET tube are all connected with a power supply, the source of the second TFET tube, the source of the fourth TFET tube, the source of the sixth TFET tube, the source of the eighth TFET tube, the source of the tenth TFET tube, the source of the twelfth TFET tube and the source of the fourteenth TFET tube are all grounded, the first grid electrode of the first TFET tube, the first grid electrode of the second TFET tube, the first grid electrode of the fifth TFET tube, the second grid electrode of the fifth TFET tube, the third grid electrode of the fifth TFET tube, the first grid electrode of the sixth TFET tube, the second grid electrode of the sixth TFET tube, the third grid electrode of the sixth TFET tube, the first grid electrode of the eleventh TFET tube and the second grid electrode of the twelfth TFET tube are connected and the connecting end is the first input end of the one-bit full adder, the first input end of the one-bit full adder is used for accessing a first input signal, the second grid electrode of the first TFET pipe, the second grid electrode of the second TFET pipe, the first grid electrode of the seventh TFET pipe, the second grid electrode of the eighth TFET pipe, the first grid electrode of the ninth TFET pipe, the second grid electrode of the ninth TFET pipe, the third grid electrode of the ninth TFET pipe, the first grid electrode of the tenth TFET pipe, the second grid electrode of the tenth TFET pipe and the third grid electrode of the tenth TFET pipe are connected, the connecting end of the first TFET pipe, the second input end of the one-bit full adder is used for accessing a second input signal, the third grid electrode of the first TFET tube, the third grid electrode of the second TFET tube, the second grid electrode of the seventh TFET tube, the third grid electrode of the eighth TFET tube, the second grid electrode of the eleventh TFET tube, the third grid electrode of the twelfth TFET tube, the second grid electrode of the thirteenth TFET tube and the second grid electrode of the fourteenth TFET tube are connected, the connecting end of the second grid electrode of the thirteenth TFET tube and the second grid electrode of the thirteenth TFET tube is the carry input end of the one-bit full adder, the carry input end of the one-bit full adder is used for accessing a carry signal output in low order, the drain electrode of the first TFET tube, the drain electrode of the second TFET tube, the first grid electrode of the third TFET tube, the second grid electrode of the third TFET tube, the first grid electrode of the fourth TFET tube, the second grid electrode of the fourth TFET tube and the third grid electrode of the fourth TFET tube are connected, the drain electrode of the third TFET tube is connected with the drain electrode of the fourth TFET tube, the connection end of the drain electrode of the fourth TFET tube is the carry output end of the one-bit full adder and is used for outputting a carry signal to high position, the drain electrode of the fifth TFET tube, the drain electrode of the sixth TFET tube, the third grid electrode of the seventh TFET tube and the first grid electrode of the eighth TFET tube are connected, the drain electrode of the seventh TFET tube, the drain electrode of the eighth TFET tube, the first grid electrode of the thirteenth TFET tube and the third grid electrode of the fourteenth TFET tube are connected, the drain electrode of the ninth TFET tube, the drain electrode of the tenth TFET tube, the third grid electrode of the eleventh TFET tube and the first grid electrode of the twelfth TFET tube are connected, the drain electrode of the eleventh TFET tube, the third grid electrode of the thirteenth TFET tube and the fourth TFET tube are connected, the drain electrode of the thirteenth TFET tube is connected with the drain electrode of the fourteenth TFET tube, the connection end of the drain electrode is the sum output end of the one-bit full adder, and the sum output end of the one-bit full adder is used for outputting a sum signal.
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