CN105958998A - One-bit full adder based on Fin FET mixed logic - Google Patents
One-bit full adder based on Fin FET mixed logic Download PDFInfo
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- CN105958998A CN105958998A CN201610259437.6A CN201610259437A CN105958998A CN 105958998 A CN105958998 A CN 105958998A CN 201610259437 A CN201610259437 A CN 201610259437A CN 105958998 A CN105958998 A CN 105958998A
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- finfet pipe
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention discloses a one-bit full adder based on Fin FET mixed logic. The one-bit full adder comprises a summing output circuit and a carry output circuit. The summing output circuit comprises first to fourteenth Fin FETs. The carry output circuit comprises fifteenth to twenty fourth Fin FETs. The one-bit full adder is low in power consumption and power consumption time delay product.
Description
Technical field
The present invention relates to a kind of one-bit full addres, especially relate to a kind of one-bit full addres based on FinFET mixed logic.
Background technology
Full adder is as a kind of elementary cell of electronic system, and it can not only complete addition, moreover it is possible to participate in subtraction, multiplication and
The computings such as division, are widely used in large-scale IC design.Full adder is the numeral that performance requirement is higher
The significant element of signal processor, microprocessor and Single Chip Microcomputer (SCM) system, the quality of full adder performance is to whole system performance
Affect particular importance.One-bit full addres is widely used in the carry critical path of multibit adder, is to affect multi digit addition
One of key factor of device.FinFET pipe (fin field-effect transistor, Fin Field-Effect Transistor) is a kind of mutual
Bu Shi metal-oxide-semiconductor (MOS) (CMOS) transistor, has the advantages such as high speed, low-power consumption and area are little.FinFET has managed at present
It is applied to the design field of one-bit full addres.
Existing based on FinFET with the one-bit full addres of the CPL logic of grid circuit structure diagram as depicted in figs. 1 and 2,
This one-bit full addres carry-out circuit composition sued for peace shown in output circuit and Fig. 2 as shown in Figure 1.Summation output electricity
The input signal that road is accessed first passes through module CPL1 and produces XOR/XNOR signal, then by two pull-up p-types FinFET
Pipe makes XOR/XNOR signal reach full swing, reconnects and negates generation and signal S output after module TG1 gates,
The input signal that carry-out circuit accesses first passes through module CPL2 and produces NOR/NAND signal, reconnects module TG2 and enters
High-order carry signal C of generation is negated after row gatingOOutput.But, existing based on FinFET with the CPL logic of grid
One-bit full addres has the problem that this one-bit full addres is by negating generation summing signal S and carry signal CO, need
Be equipped with the FinFET pipe forming inverter function, thus will necessarily increase crucial saltus step node, cause circuit power consumption and
The increase of time delay, power consumption and and power-consumption design the biggest.
Summary of the invention
The technical problem to be solved be to provide a kind of power consumption and power-consumption design the least based on FinFET
The one-bit full addres of mixed logic.
The present invention solves the technical scheme that above-mentioned technical problem used: a kind of based on FinFET mixed logic one
Full adder, including summation output circuit and carry-out circuit, described summation output circuit include a FinFET pipe,
2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET manage, the 5th FinFET pipe, the 6th FinFET manage,
7th FinFET pipe, the 8th FinFET pipe, the 9th FinFET manage, the tenth FinFET pipe, the 11st FinFET manage,
12nd FinFET pipe, the 13rd FinFET pipe and the 14th FinFET pipe, a described FinFET manages, institute
The 2nd FinFET pipe stated, the 5th described FinFET pipe, the 7th described FinFET pipe, the 9th described FinFET
Pipe, the 11st described FinFET pipe and the 13rd described FinFET pipe are managed for p-type FinFET, described the 3rd
FinFET pipe, the 4th described FinFET pipe, the 6th described FinFET pipe, the 8th described FinFET pipe, institute
The tenth FinFET pipe stated, the 12nd described FinFET pipe and the 14th described FinFET pipe are N-type FinFET
Pipe, the 7th described FinFET pipe and the number of the fin of the 8th described FinFET pipe are 2, a described FinFET
Pipe, described 2nd FinFET pipe, the 3rd described FinFET pipe, the 4th described FinFET pipe, described the
Five FinFET pipes, the 6th described FinFET pipe, the 9th described FinFET manage, the tenth described FinFET manages,
The 11st described FinFET pipe, the 12nd described FinFET pipe, the 13rd described FinFET manage and described
The number of the fin of the 14th FinFET pipe is 1；Described carry-out circuit include the 15th FinFET pipe, the 16th
FinFET pipe, the 17th FinFET pipe, the 18th FinFET pipe, the 19th FinFET pipe, the 20th FinFET
Pipe, the 21st FinFET pipe, the 22nd FinFET pipe, the 23rd FinFET pipe and the 24th FinFET
Pipe, the 15th described FinFET pipe, the 17th described FinFET pipe, the 19th described FinFET pipe, institute
The 21st FinFET pipe and the 23rd described FinFET pipe stated are managed for p-type FinFET, described the 16th
FinFET pipe, the 18th described FinFET pipe, the 20th described FinFET pipe, the 22nd described FinFET
Pipe and the 24th described FinFET pipe are managed for N-type FinFET；Described 15th FinFET pipe, described the
16 FinFET pipes, described 17th FinFET pipe, the 18th described FinFET pipe, the described the 19th
FinFET pipe, the 20th described FinFET pipe, the 21st described FinFET pipe, the 22nd described FinFET
The number of the fin of pipe, the 23rd described FinFET pipe and the 24th described FinFET pipe is 1；Described
The source electrode of one FinFET pipe, the front gate of the 2nd described FinFET pipe, the described backgate of the 2nd FinFET pipe, institute
The source electrode of the 3rd FinFET pipe stated, the front gate of the 4th described FinFET pipe, the back of the body of the 4th described FinFET pipe
Grid, the front gate of the 7th described FinFET pipe, the front gate of the 8th described FinFET pipe, the 15th described FinFET
The front gate of pipe, the front gate of the 16th described FinFET pipe, the front gate of the 17th described FinFET pipe and described
The front gate of 18 FinFET pipes connects and it connects the first input end that end is described one-bit full addres, described one
The first input end of full adder for accessing the first addend signal, the front gate of a described FinFET pipe, described the
The backgate of one FinFET pipe, the source electrode of the 2nd described FinFET pipe, the described backgate of the 3rd FinFET pipe, institute
The front gate of the 3rd FinFET pipe stated, the source electrode of the 4th described FinFET pipe, the back of the body of the 7th described FinFET pipe
Grid, the backgate of the 8th described FinFET pipe, the backgate of the 15th described FinFET pipe, the 16th described FinFET
The backgate of pipe, the backgate of the 17th described FinFET pipe and the back-gate connection of the 18th described FinFET pipe and its company
Connecing the end the second input for described one-bit full addres, the second input of described one-bit full addres is used for access second
Addend signal, the drain electrode of a described FinFET pipe, the described drain electrode of the 2nd FinFET pipe, the described the 5th
The front gate of FinFET pipe, the backgate of the 5th described FinFET pipe, the drain electrode of the 6th described FinFET pipe, described
The drain electrode of the 8th FinFET pipe, the source electrode of the 11st described FinFET pipe and the 12nd described FinFET pipe
Source electrode connect, the drain electrode of the 3rd described FinFET pipe, the described drain electrode of the 4th FinFET pipe, the described the 5th
The drain electrode of FinFET pipe, the front gate of the 6th described FinFET pipe, the backgate of the 6th described FinFET pipe, described
The drain electrode of the 7th FinFET pipe, the source electrode of the 9th described FinFET pipe and the source electrode of the tenth described FinFET pipe
Connect, the source electrode of the 5th described FinFET pipe, the source electrode of the 7th described FinFET pipe, the 13rd described FinFET
The source electrode of pipe, the source electrode of the 15th described FinFET pipe, the source electrode of the 17th described FinFET pipe and described
The source electrode of 23 FinFET pipes all accesses power supply, the source electrode of the 6th described FinFET pipe, the 8th described FinFET
The source electrode of pipe, the source electrode of the 14th described FinFET pipe, the source electrode of the 16th described FinFET pipe, described
The source electrode of 18 FinFET pipes and the source grounding of the 24th described FinFET pipe, the 9th described FinFET
The front gate of pipe, the backgate of the 9th described FinFET pipe, the described front gate of the 12nd FinFET pipe, the described the tenth
The backgate of two FinFET pipes, the front gate of the 19th described FinFET pipe, the backgate of the 19th described FinFET pipe,
The backgate of the 22nd described FinFET pipe and the front gate of the 22nd described FinFET pipe connect and its connection end is
The low order carry signal input part of described one-bit full addres, the low order carry signal input part of described one-bit full addres is used
In accessing low order carry signal, the front gate of the tenth described FinFET pipe, the described backgate of the tenth FinFET pipe, institute
The front gate of the 11st FinFET pipe stated, the backgate of the 11st described FinFET pipe, the 20th described FinFET
The front gate of pipe, the backgate of the 20th described FinFET pipe, the front gate of the 21st described FinFET pipe and described
The back-gate connection of the 21st FinFET pipe and the low order carry signal inversion that its connection end is described one-bit full addres are defeated
Entering end, the low order carry signal inversion input of described one-bit full addres is for accessing the anti-phase letter of low order carry signal
Number, the drain electrode of the 9th described FinFET pipe, the drain electrode of the tenth described FinFET pipe, the 11st described FinFET
The drain electrode of pipe, the drain electrode of the 12nd described FinFET pipe, the front gate of the 13rd described FinFET pipe, described
The backgate of 13 FinFET pipes, the front gate of the 14th described FinFET pipe and the back of the body of the 14th described FinFET pipe
Grid connect, the drain electrode of the 13rd described FinFET pipe and the drain electrode connection of the 14th described FinFET pipe and its connection
That end is described one-bit full addres and signal output part, the described drain electrode of the 15th FinFET pipe, the described the tenth
The drain electrode of six FinFET pipes, the drain electrode of the 19th described FinFET pipe and the drain electrode of the 20th described FinFET pipe
Connect, the drain electrode of the 17th described FinFET pipe, the described drain electrode of the 18th FinFET pipe, the described the 20th
The drain electrode of one FinFET pipe and the drain electrode of the 22nd described FinFET pipe connect, the 19th described FinFET pipe
Source electrode, the source electrode of the 20th described FinFET pipe, the source electrode of the 21st described FinFET pipe, described
The source electrode of 22 FinFET pipes, the front gate of the 23rd described FinFET pipe, the 23rd described FinFET
The backgate of pipe, the front gate of the 24th described FinFET pipe and the back-gate connection of the 24th described FinFET pipe,
The drain electrode of the 23rd described FinFET pipe and the drain electrode connection of the 24th described FinFET pipe and its connection end are
The high-order carry signal output end of described one-bit full addres, the high-order carry signal output end of described one-bit full addres is used
In the high-order carry signal of output.
A described FinFET pipe, the 2nd described FinFET pipe, the 3rd described FinFET pipe, the described the 4th
FinFET pipe, described 5th FinFET pipe, the 6th described FinFET pipe, the 9th described FinFET pipe, described
The tenth FinFET pipe, described 11st FinFET pipe, the 12nd described FinFET pipe, the described the 13rd
FinFET pipe, the 14th described FinFET pipe, the 15th described FinFET manage, the 18th described FinFET manages,
Described 19th FinFET pipe, the 20th described FinFET pipe, the 21st described FinFET pipe, described
22nd FinFET pipe, the 23rd described FinFET pipe and the 24th described FinFET pipe are Low threshold
FinFET manages, the 7th described FinFET pipe, the 8th described FinFET pipe, the 16th described FinFET pipe and institute
The 17th FinFET pipe stated is managed for high threshold FinFET.In this structure, high threshold FinFET pipe and Low threshold FinFET
Coordinate in order, it is to avoid the short-circuit dissipation of circuit, reduce circuit power consumption and power-consumption design further.
Compared with prior art, it is an advantage of the current invention that by the oneth FinFET manage, the 2nd FinFET manage, the 3rd
FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe, the 7th FinFET pipe, the 8th
FinFET pipe, the 9th FinFET pipe, the tenth FinFET manage, the 11st FinFET pipe, the 12nd FinFET manage,
13rd FinFET pipe and the summation output circuit of the 14th FinFET pipe structure one-bit full addres, a FinFET pipe,
2nd FinFET pipe, the 5th FinFET pipe, the 7th FinFET pipe, the 9th FinFET pipe, the 11st FinFET pipe
Manage for p-type FinFET with the 13rd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 6th FinFET
Pipe, the 8th FinFET pipe, the tenth FinFET pipe, the 12nd FinFET pipe and the 14th FinFET pipe are N-type FinFET
Pipe, the number of the fin of the 7th FinFET pipe and the 8th FinFET pipe is 2, a FinFET manages, the 2nd FinFET manages,
3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET manage, the 6th FinFET pipe, the 9th FinFET manage,
The number of the fin of the tenth FinFET pipe, the 11st FinFET pipe, the 12nd FinFET pipe and the 13rd FinFET pipe
It is 1；By the 15th FinFET manage, the 16th FinFET manage, the 17th FinFET manage, the 18th FinFET manage,
19th FinFET pipe, the 20th FinFET pipe, the 21st FinFET pipe, the 22nd FinFET pipe, the
23 FinFET pipes and the carry-out circuit of the 24th FinFET pipe structure one-bit full addres, the 15th FinFET
Pipe, the 17th FinFET pipe, the 19th FinFET pipe, the 21st FinFET pipe and the 23rd FinFET pipe
For p-type FinFET manage, the 16th FinFET pipe, the 18th FinFET pipe, the 20th FinFET pipe, the 20th
Two FinFET pipes and the 24th FinFET pipe are managed for N-type FinFET；15th FinFET pipe, the 16th FinFET
Pipe, the 17th FinFET pipe, the 18th FinFET pipe, the 19th FinFET pipe, the 20th FinFET pipe, the
21 FinFET pipes, the 22nd FinFET pipe, the 23rd FinFET pipe and the 24th FinFET pipe
The number of fin is 1；In the course of the work, ensure that M signal by the 7th FinFET pipe and the 8th FinFET pipe
XOR/XNOR output voltage reaches full swing, increases driving force, and M signal XOR/XNOR only needs to drive
The dynamic source electrode being followed by FinFET pipe, does not exist by power supply to ground between other 7th FinFET pipe and the 8th FinFET pipe
Between short-channel, it is to avoid the short-circuit dissipation of circuit, the thus output of the M signal of the one-bit full addres of the present invention
Load reduces, and power consumption reduces, and power consumption and power-consumption design are the least.
Accompanying drawing explanation
Fig. 1 be existing a kind of based on FinFET with grid CPL logic one-bit full addres summation output circuit structure
Figure；
Fig. 2 be existing a kind of based on FinFET with the structure of the output carry circuit of the one-bit full addres of grid CPL logic
Figure；
Fig. 3 is the structure chart of the summation output circuit of a kind of based on FinFET mixed logic the one-bit full addres of the present invention；
Fig. 4 is the structure chart of the carry-out circuit of a kind of based on FinFET mixed logic the one-bit full addres of the present invention；
Fig. 5 is under the conditions of superthreshold, the summation of a kind of based on FinFET mixed logic the one-bit full addres of the present invention
The analogous diagram of output circuit；
Fig. 6 is under the conditions of superthreshold, the carry of a kind of based on FinFET mixed logic the one-bit full addres of the present invention
The analogous diagram of output circuit.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
Embodiment one: as shown in Figure 3 and Figure 4, a kind of one-bit full addres based on FinFET mixed logic, including summation
Output circuit and carry-out circuit, summation output circuit include a FinFET pipe M1, the 2nd FinFET pipe M2,
3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th FinFET pipe M6,
Seven FinFET pipe M7, the 8th FinFET pipe M8, the 9th FinFET pipe M9, the tenth FinFET pipe M10,
11 FinFET pipe M11, the 12nd FinFET pipe M12, the 13rd FinFET pipe M13 and the 14th FinFET
Pipe M14, a FinFET pipe M1, the 2nd FinFET pipe M2, the 5th FinFET pipe M5, the 7th FinFET
Pipe M7, the 9th FinFET pipe M9, the 11st FinFET pipe M11 and the 13rd FinFET pipe M13 are p-type FinFET
Pipe, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 6th FinFET pipe M6, the 8th FinFET pipe M8,
Tenth FinFET pipe M10, the 12nd FinFET pipe M12 and the 14th FinFET pipe M14 are N-type FinFET
Pipe, the number of the fin of the 7th FinFET pipe M7 and the 8th FinFET pipe M8 is 2, a FinFET pipe M1, the
Two FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th
FinFET pipe M6, the 9th FinFET pipe M9, the tenth FinFET pipe M10, the 11st FinFET pipe M11,
12 FinFET pipe M12, the number of fin of the 13rd FinFET pipe M13 and the 14th FinFET pipe M14 are 1；
Carry-out circuit includes the 15th FinFET pipe M15, the 16th FinFET pipe M16, the 17th FinFET pipe
M17, the 18th FinFET pipe M18, the 19th FinFET pipe M19, the 20th FinFET pipe M20, the 20th
One FinFET pipe M21, the 22nd FinFET pipe M22, the 23rd FinFET pipe M23 and the 24th FinFET
Pipe M24, the 15th FinFET pipe M15, the 17th FinFET pipe M17, the 19th FinFET pipe M19,
21 FinFET pipe M21 and the 23rd FinFET pipe M23 are p-type FinFET pipe, the 16th FinFET
Pipe M16, the 18th FinFET pipe M18, the 20th FinFET pipe M20, the 22nd FinFET pipe M22 and
24th FinFET pipe M24 is N-type FinFET pipe；15th FinFET pipe M15, the 16th FinFET pipe
M16, the 17th FinFET pipe M17, the 18th FinFET pipe M18, the 19th FinFET pipe M19, the 20th
FinFET pipe M20, the 21st FinFET pipe M21, the 22nd FinFET pipe M22, the 23rd FinFET
The number of the fin of pipe M23 and the 24th FinFET pipe M24 is 1；The source electrode of the oneth FinFET pipe M1, second
The front gate of FinFET pipe M2, the backgate of the 2nd FinFET pipe M2, the source electrode of the 3rd FinFET pipe M3, the 4th
The front gate of FinFET pipe M4, the backgate of the 4th FinFET pipe M4, the front gate of the 7th FinFET pipe M7, the 8th
The front gate of FinFET pipe M8, the front gate of the 15th FinFET pipe M15, the front gate of the 16th FinFET pipe M16,
The front gate of the front gate of the 17th FinFET pipe M17 and the 18th FinFET pipe M18 connect and its connect end be one complete
Adding the first input end of device, the first input end of one-bit full addres is for accessing the first addend signal A, a FinFET
The front gate of pipe M1, the backgate of a FinFET pipe M1, the source electrode of the 2nd FinFET pipe M2, the 3rd FinFET
The backgate of pipe M3, the front gate of the 3rd FinFET pipe M3, the source electrode of the 4th FinFET pipe M4, the 7th FinFET
The backgate of pipe M7, the backgate of the 8th FinFET pipe M8, the backgate of the 15th FinFET pipe M15, the 16th FinFET
The backgate of pipe M16, the backgate of the 17th FinFET pipe M17 and the back-gate connection of the 18th FinFET pipe M18 and
It connects the second input that end is one-bit full addres, and the second input of one-bit full addres is for accessing the second addend signal
B, the drain electrode of a FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the front gate of the 5th FinFET pipe M5,
The backgate of the 5th FinFET pipe M5, the drain electrode of the 6th FinFET pipe M6, the drain electrode of the 8th FinFET pipe M8,
The source electrode of the 11st FinFET pipe M11 and the source electrode of the 12nd FinFET pipe M12 connect, the 3rd FinFET pipe M3
Drain electrode, the drain electrode of the 4th FinFET pipe M4, the drain electrode of the 5th FinFET pipe M5, the 6th FinFET pipe M6
Front gate, the backgate of the 6th FinFET pipe M6, the drain electrode of the 7th FinFET pipe M7, the 9th FinFET pipe M9
Source electrode and the tenth FinFET pipe M10 source electrode connect, the source electrode of the 5th FinFET pipe M5, the 7th FinFET pipe
The source electrode of M7, the source electrode of the 13rd FinFET pipe M13, the source electrode of the 15th FinFET pipe M15, the 17th FinFET
The source electrode of pipe M17 and the source electrode of the 23rd FinFET pipe M23 all access power supply, the source of the 6th FinFET pipe M6
Pole, the source electrode of the 8th FinFET pipe M8, the source electrode of the 14th FinFET pipe M14, the 16th FinFET pipe M16
Source electrode, the source electrode of the 18th FinFET pipe M18 and the source grounding of the 24th FinFET pipe M24, the 9th
The front gate of FinFET pipe M9, the backgate of the 9th FinFET pipe M9, the front gate of the 12nd FinFET pipe M12,
The backgate of 12 FinFET pipe M12, the front gate of the 19th FinFET pipe M19, the 19th FinFET pipe M19
The front gate of backgate, the backgate of the 22nd FinFET pipe M22 and the 22nd FinFET pipe M22 connects and it connects
End is the low order carry signal input part of one-bit full addres, and the low order carry signal input part of one-bit full addres is used for accessing low
Position carry signal, the front gate of the tenth FinFET pipe M10, the backgate of the tenth FinFET pipe M10, the 11st FinFET
The front gate of pipe M11, the backgate of the 11st FinFET pipe M11, the front gate of the 20th FinFET pipe M20, second
The backgate of ten FinFET pipe M20, the front gate of the 21st FinFET pipe M21 and the 21st FinFET pipe M21
Back-gate connection and its to connect end be the low order carry signal inversion input of one-bit full addres, the low level of one-bit full addres enters
Position signal inversion input for accessing the inversion signal of low order carry signal, the drain electrode of the 9th FinFET pipe M9, the
The drain electrode of ten FinFET pipe M10, the drain electrode of the 11st FinFET pipe M11, the leakage of the 12nd FinFET pipe M12
Pole, the front gate of the 13rd FinFET pipe M13, the backgate of the 13rd FinFET pipe M13, the 14th FinFET pipe
The front gate of M14 and the back-gate connection of the 14th FinFET pipe M14, the drain electrode and the tenth of the 13rd FinFET pipe M13
Four FinFET pipe M14 drain electrode connect and its connect end be one-bit full addres and signal output part, the 15th FinFET
The drain electrode of pipe M15, the drain electrode of the 16th FinFET pipe M16, the drain electrode and second of the 19th FinFET pipe M19
The drain electrode of ten FinFET pipe M20 connects, the drain electrode of the 17th FinFET pipe M17, the 18th FinFET pipe M18
Drain electrode, the drain electrode of the 21st FinFET pipe M21 and the 22nd FinFET pipe M22 drain electrode connect, the tenth
The source electrode of nine FinFET pipe M19, the source electrode of the 20th FinFET pipe M20, the 21st FinFET pipe M21
Source electrode, the source electrode of the 22nd FinFET pipe M22, the front gate of the 23rd FinFET pipe M23, the 23rd
The backgate of FinFET pipe M23, the front gate of the 24th FinFET pipe M24 and the 24th FinFET pipe M24's
Back-gate connection, the drain electrode of the 23rd FinFET pipe M23 and the drain electrode of the 24th FinFET pipe M24 connect and it
Connecting the high-order carry signal output end that end is one-bit full addres, the high-order carry signal output end of one-bit full addres is for defeated
Go out high-order carry signal.
Embodiment two: as shown in Figure 3 and Figure 4, a kind of one-bit full addres based on FinFET mixed logic, including summation
Output circuit and carry-out circuit, summation output circuit include a FinFET pipe M1, the 2nd FinFET pipe M2,
3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th FinFET pipe M6,
Seven FinFET pipe M7, the 8th FinFET pipe M8, the 9th FinFET pipe M9, the tenth FinFET pipe M10,
11 FinFET pipe M11, the 12nd FinFET pipe M12, the 13rd FinFET pipe M13 and the 14th FinFET
Pipe M14, a FinFET pipe M1, the 2nd FinFET pipe M2, the 5th FinFET pipe M5, the 7th FinFET
Pipe M7, the 9th FinFET pipe M9, the 11st FinFET pipe M11 and the 13rd FinFET pipe M13 are p-type FinFET
Pipe, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 6th FinFET pipe M6, the 8th FinFET pipe M8,
Tenth FinFET pipe M10, the 12nd FinFET pipe M12 and the 14th FinFET pipe M14 are N-type FinFET
Pipe, the number of the fin of the 7th FinFET pipe M7 and the 8th FinFET pipe M8 is 2, a FinFET pipe M1, the
Two FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th
FinFET pipe M6, the 9th FinFET pipe M9, the tenth FinFET pipe M10, the 11st FinFET pipe M11,
12 FinFET pipe M12, the number of fin of the 13rd FinFET pipe M13 and the 14th FinFET pipe M14 are 1；
Carry-out circuit includes the 15th FinFET pipe M15, the 16th FinFET pipe M16, the 17th FinFET pipe
M17, the 18th FinFET pipe M18, the 19th FinFET pipe M19, the 20th FinFET pipe M20, the 20th
One FinFET pipe M21, the 22nd FinFET pipe M22, the 23rd FinFET pipe M23 and the 24th FinFET
Pipe M24, the 15th FinFET pipe M15, the 17th FinFET pipe M17, the 19th FinFET pipe M19,
21 FinFET pipe M21 and the 23rd FinFET pipe M23 are p-type FinFET pipe, the 16th FinFET
Pipe M16, the 18th FinFET pipe M18, the 20th FinFET pipe M20, the 22nd FinFET pipe M22 and
24th FinFET pipe M24 is N-type FinFET pipe；15th FinFET pipe M15, the 16th FinFET pipe
M16, the 17th FinFET pipe M17, the 18th FinFET pipe M18, the 19th FinFET pipe M19, the 20th
FinFET pipe M20, the 21st FinFET pipe M21, the 22nd FinFET pipe M22, the 23rd FinFET
The number of the fin of pipe M23 and the 24th FinFET pipe M24 is 1；The source electrode of the oneth FinFET pipe M1, second
The front gate of FinFET pipe M2, the backgate of the 2nd FinFET pipe M2, the source electrode of the 3rd FinFET pipe M3, the 4th
The front gate of FinFET pipe M4, the backgate of the 4th FinFET pipe M4, the front gate of the 7th FinFET pipe M7, the 8th
The front gate of FinFET pipe M8, the front gate of the 15th FinFET pipe M15, the front gate of the 16th FinFET pipe M16,
The front gate of the front gate of the 17th FinFET pipe M17 and the 18th FinFET pipe M18 connect and its connect end be one complete
Adding the first input end of device, the first input end of one-bit full addres is for accessing the first addend signal A, a FinFET
The front gate of pipe M1, the backgate of a FinFET pipe M1, the source electrode of the 2nd FinFET pipe M2, the 3rd FinFET
The backgate of pipe M3, the front gate of the 3rd FinFET pipe M3, the source electrode of the 4th FinFET pipe M4, the 7th FinFET
The backgate of pipe M7, the backgate of the 8th FinFET pipe M8, the backgate of the 15th FinFET pipe M15, the 16th FinFET
The backgate of pipe M16, the backgate of the 17th FinFET pipe M17 and the back-gate connection of the 18th FinFET pipe M18 and
It connects the second input that end is one-bit full addres, and the second input of one-bit full addres is for accessing the second addend signal
B, the drain electrode of a FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the front gate of the 5th FinFET pipe M5,
The backgate of the 5th FinFET pipe M5, the drain electrode of the 6th FinFET pipe M6, the drain electrode of the 8th FinFET pipe M8,
The source electrode of the 11st FinFET pipe M11 and the source electrode of the 12nd FinFET pipe M12 connect, the 3rd FinFET pipe M3
Drain electrode, the drain electrode of the 4th FinFET pipe M4, the drain electrode of the 5th FinFET pipe M5, the 6th FinFET pipe M6
Front gate, the backgate of the 6th FinFET pipe M6, the drain electrode of the 7th FinFET pipe M7, the 9th FinFET pipe M9
Source electrode and the tenth FinFET pipe M10 source electrode connect, the source electrode of the 5th FinFET pipe M5, the 7th FinFET pipe
The source electrode of M7, the source electrode of the 13rd FinFET pipe M13, the source electrode of the 15th FinFET pipe M15, the 17th FinFET
The source electrode of pipe M17 and the source electrode of the 23rd FinFET pipe M23 all access power supply, the source of the 6th FinFET pipe M6
Pole, the source electrode of the 8th FinFET pipe M8, the source electrode of the 14th FinFET pipe M14, the 16th FinFET pipe M16
Source electrode, the source electrode of the 18th FinFET pipe M18 and the source grounding of the 24th FinFET pipe M24, the 9th
The front gate of FinFET pipe M9, the backgate of the 9th FinFET pipe M9, the front gate of the 12nd FinFET pipe M12,
The backgate of 12 FinFET pipe M12, the front gate of the 19th FinFET pipe M19, the 19th FinFET pipe M19
The front gate of backgate, the backgate of the 22nd FinFET pipe M22 and the 22nd FinFET pipe M22 connects and it connects
End is the low order carry signal input part of one-bit full addres, and the low order carry signal input part of one-bit full addres is used for accessing low
Position carry signal, the front gate of the tenth FinFET pipe M10, the backgate of the tenth FinFET pipe M10, the 11st FinFET
The front gate of pipe M11, the backgate of the 11st FinFET pipe M11, the front gate of the 20th FinFET pipe M20, second
The backgate of ten FinFET pipe M20, the front gate of the 21st FinFET pipe M21 and the 21st FinFET pipe M21
Back-gate connection and its to connect end be the low order carry signal inversion input of one-bit full addres, the low level of one-bit full addres enters
Position signal inversion input for accessing the inversion signal of low order carry signal, the drain electrode of the 9th FinFET pipe M9, the
The drain electrode of ten FinFET pipe M10, the drain electrode of the 11st FinFET pipe M11, the leakage of the 12nd FinFET pipe M12
Pole, the front gate of the 13rd FinFET pipe M13, the backgate of the 13rd FinFET pipe M13, the 14th FinFET pipe
The front gate of M14 and the back-gate connection of the 14th FinFET pipe M14, the drain electrode and the tenth of the 13rd FinFET pipe M13
Four FinFET pipe M14 drain electrode connect and its connect end be one-bit full addres and signal output part, the 15th FinFET
The drain electrode of pipe M15, the drain electrode of the 16th FinFET pipe M16, the drain electrode and second of the 19th FinFET pipe M19
The drain electrode of ten FinFET pipe M20 connects, the drain electrode of the 17th FinFET pipe M17, the 18th FinFET pipe M18
Drain electrode, the drain electrode of the 21st FinFET pipe M21 and the 22nd FinFET pipe M22 drain electrode connect, the tenth
The source electrode of nine FinFET pipe M19, the source electrode of the 20th FinFET pipe M20, the 21st FinFET pipe M21
Source electrode, the source electrode of the 22nd FinFET pipe M22, the front gate of the 23rd FinFET pipe M23, the 23rd
The backgate of FinFET pipe M23, the front gate of the 24th FinFET pipe M24 and the 24th FinFET pipe M24's
Back-gate connection, the drain electrode of the 23rd FinFET pipe M23 and the drain electrode of the 24th FinFET pipe M24 connect and it
Connecting the high-order carry signal output end that end is one-bit full addres, the high-order carry signal output end of one-bit full addres is for defeated
Go out high-order carry signal.
In the present embodiment, a FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th
FinFET pipe M4, the 5th FinFET pipe M5, the 6th FinFET pipe M6, the 9th FinFET pipe M9, the tenth FinFET
Pipe M10, the 11st FinFET pipe M11, the 12nd FinFET pipe M12, the 13rd FinFET pipe M13,
14 FinFET pipe M14, the 15th FinFET pipe M15, the 18th FinFET pipe M18, the 19th FinFET
Pipe M19, the 20th FinFET pipe M20, the 21st FinFET pipe M21, the 22nd FinFET pipe M22,
23rd FinFET pipe M23 and the 24th FinFET pipe M24 is that Low threshold FinFET manages and its threshold value is
0.1V, the 7th FinFET pipe M7, the 8th FinFET pipe M8, the 16th FinFET pipe M16 and the 17th FinFET
Pipe M17 is that high threshold FinFET manages and its threshold value is 0.6V.
In order to verify the superiority of a kind of based on FinFET mixed logic the one-bit full addres of the present invention, at BSIMIMG
Under standard technology, a kind of based on FinFET mixed logic the one-bit full addres of the present invention and existing based on FinFET with
The various performances of the one-bit full addres of the CPL logic of grid compare.Use circuit simulation tools HSPICE at circuit
Incoming frequency is two kinds of circuit structures to be carried out Comparative Simulation under conditions of 200MHz, 500MHz, 1GHz,
The supply voltage that BSIMIMG technology library is corresponding is 1V.Under the conditions of superthreshold 0.8v, the one of the present invention based on
The analogous diagram of the summation output circuit of the one-bit full addres of FinFET mixed logic is as it is shown in figure 5, at superthreshold 0.8v bar
Under part, the analogous diagram of the carry-out circuit of a kind of based on FinFET mixed logic the one-bit full addres of the present invention such as figure
Shown in 6.
Under the conditions of superthreshold, i.e. supply voltage is 0.8v, during circuit incoming frequency 200MGHZ, and the one of the present invention
One-bit full addres based on FinFET mixed logic and existing entirely add with of CPL logic of grid based on FinFET
The transistor size of device, time delay, average power consumption, power-consumption design are more as shown in table 1.
Table 1
As can be seen from Table 1: the summation output electricity of a kind of based on FinFET mixed logic the one-bit full addres of the present invention
Road with existing based on FinFET compared with the summation output circuit of the one-bit full addres of the CPL logic of grid, number of transistors
Mesh increases by 2, and time delay increases 8.8%, and average power consumption have dropped 69.4%, and power-consumption design have dropped 66.7%.This
Invention a kind of based on FinFET mixed logic one-bit full addres carry-out circuit and existing based on FinFET with
The carry-out circuit of the one-bit full addres of the CPL logic of grid is compared, and transistor size reduces 2, time delay liter
High by 14.9%, average power consumption have dropped 72.9%, and power-consumption design have dropped 62.1%.
Under the conditions of superthreshold, i.e. supply voltage is 0.8v, during circuit incoming frequency 500MGHZ, and the one of the present invention
One-bit full addres based on FinFET mixed logic and existing entirely add with of CPL logic of grid based on FinFET
The transistor size of device, time delay, average power consumption, power-consumption design are more as shown in table 2.
Table 2
As can be seen from Table 2: the summation output of a kind of based on FinFET mixed logic the one-bit full addres of the present invention
Circuit with existing based on FinFET compared with the summation output circuit of the one-bit full addres of the CPL logic of grid, transistor
Number increases by 2, and time delay adds 8.8%, and average power consumption have dropped 65.5%, and power-consumption design have dropped 62.5%.
The carry-out circuit of a kind of based on FinFET mixed logic the one-bit full addres of the present invention and existing based on FinFET
Compared with the carry-out circuit of the one-bit full addres of the CPL logic of grid, transistor size reduces 2, time delay
Increasing 14.9%, average power consumption have dropped 67.9%, and power-consumption design have dropped 56.4%.
Under the conditions of superthreshold, i.e. supply voltage is 0.8v, during circuit incoming frequency 1GHZ, the one of the present invention based on
The one-bit full addres of FinFET mixed logic and existing based on FinFET with the one-bit full addres of the CPL logic of grid
Transistor size, time delay, average power consumption, power-consumption design are more as shown in table 3.
Table 3
As can be seen from Table 3: the summation output electricity of a kind of based on FinFET mixed logic the one-bit full addres of the present invention
Road with existing based on FinFET compared with the summation output circuit of the one-bit full addres of the CPL logic of grid, number of transistors
Mesh adds 2, and time delay increases 8.8%, and average power consumption have dropped 59.9%, and power-consumption design have dropped 56.3%.
The carry-out circuit of a kind of based on FinFET mixed logic the one-bit full addres of the present invention and existing based on FinFET
Compared with the carry-out circuit of the one-bit full addres of the CPL logic of grid, transistor size reduces 4, time delay
Increasing 14.9%, average power consumption have dropped 60.4%, and power-consumption design have dropped 45.8%.
From above comparative result, on the premise of not affecting circuit performance, the present invention is a kind of to be mixed based on FinFET
Logical one-bit full addres with existing based on FinFET compared with the one-bit full addres of the CPL logic of grid, although brilliant
The quantity of body pipe keeps constant, and time delay has increased slightly, but power consumption and power-consumption design have obtained notable optimization.
Claims (2)
1. an one-bit full addres based on FinFET mixed logic, including summation output circuit and carry-out circuit, its
The summation output circuit being characterised by described include the oneth FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe,
4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET manage, the 7th FinFET pipe, the 8th FinFET manage,
9th FinFET pipe, the tenth FinFET pipe, the 11st FinFET pipe, the 12nd FinFET pipe, the 13rd FinFET
Pipe and the 14th FinFET pipe, a described FinFET pipe, the 2nd described FinFET pipe, the described the 5th
FinFET pipe, described 7th FinFET pipe, the 9th described FinFET pipe, the 11st described FinFET pipe and
The 13rd described FinFET pipe is managed for p-type FinFET, the 3rd described FinFET pipe, the 4th described FinFET
Pipe, described 6th FinFET pipe, the 8th described FinFET pipe, the tenth described FinFET pipe, described the
12 FinFET pipes and described 14th FinFET pipe are managed for N-type FinFET, the 7th described FinFET pipe with
The number of the fin of the 8th described FinFET pipe is 2, a described FinFET manages, the 2nd described FinFET manages,
Described 3rd FinFET pipe, the 4th described FinFET pipe, the 5th described FinFET pipe, the described the 6th
FinFET pipe, the 9th described FinFET pipe, the tenth described FinFET manage, the 11st described FinFET manages,
The fin of described 12nd FinFET pipe, the 13rd described FinFET pipe and the 14th described FinFET pipe
Number is 1；
Described carry-out circuit include the 15th FinFET pipe, the 16th FinFET pipe, the 17th FinFET pipe,
18th FinFET pipe, the 19th FinFET pipe, the 20th FinFET pipe, the 21st FinFET pipe, second
12 FinFET pipes, the 23rd FinFET pipe and the 24th FinFET pipe, described 15th FinFET pipe,
The 17th described FinFET pipe, the 19th described FinFET pipe, the 21st described FinFET manage and described
The 23rd FinFET pipe manage for p-type FinFET, described 16th FinFET manages, the 18th described FinFET
Pipe, the 20th described FinFET pipe, the 22nd described FinFET pipe and the 24th described FinFET pipe
Manage for N-type FinFET；Described 15th FinFET pipe, the 16th described FinFET pipe, the described the 17th
FinFET pipe, the 18th described FinFET pipe, the 19th described FinFET pipe, the 20th described FinFET
Pipe, the 21st described FinFET pipe, the 22nd described FinFET pipe, the 23rd described FinFET
The number of the fin of pipe and the 24th described FinFET pipe is 1；
The source electrode of a described FinFET pipe, the front gate of the 2nd described FinFET pipe, the 2nd described FinFET
The backgate of pipe, the source electrode of the 3rd described FinFET pipe, the described front gate of the 4th FinFET pipe, the described the 4th
The backgate of FinFET pipe, the front gate of the 7th described FinFET pipe, the front gate of the 8th described FinFET pipe, described
The front gate of the 15th FinFET pipe, the front gate of the 16th described FinFET pipe, described 17th FinFET pipe
Front gate and the front gate of the 18th described FinFET pipe connects and its to connect end be the first defeated of described one-bit full addres
Entering end, the first input end of described one-bit full addres is for accessing the first addend signal, and a described FinFET manages
Front gate, the backgate of a described FinFET pipe, the source electrode of the 2nd described FinFET pipe, the 3rd described FinFET
The backgate of pipe, the front gate of the 3rd described FinFET pipe, the described source electrode of the 4th FinFET pipe, the described the 7th
The backgate of FinFET pipe, the backgate of the 8th described FinFET pipe, the described backgate of the 15th FinFET pipe, institute
The backgate of the 16th FinFET pipe stated, the backgate of the 17th described FinFET pipe and the 18th described FinFET
The back-gate connection of pipe and the second input that its connection end is described one-bit full addres, the second of described one-bit full addres
Input for accessing the second addend signal, the drain electrode of a described FinFET pipe, the 2nd described FinFET pipe
Drain electrode, the described front gate of the 5th FinFET pipe, the backgate of the 5th described FinFET pipe, the 6th described FinFET
The drain electrode of pipe, the drain electrode of the 8th described FinFET pipe, the source electrode and the described the tenth of the 11st described FinFET pipe
The source electrode of two FinFET pipes connects, the drain electrode of the 3rd described FinFET pipe, the drain electrode of the 4th described FinFET pipe,
The drain electrode of the 5th described FinFET pipe, the front gate of the 6th described FinFET pipe, the 6th described FinFET pipe
Backgate, the drain electrode of the 7th described FinFET pipe, the source electrode of the 9th described FinFET pipe and the tenth described FinFET
The source electrode of pipe connects, the source electrode of the 5th described FinFET pipe, the source electrode of the 7th described FinFET pipe, described the
The source electrode of 13 FinFET pipes, the source electrode of the 15th described FinFET pipe, the source of the 17th described FinFET pipe
The source electrode of pole and the 23rd described FinFET pipe all accesses power supply, the source electrode of the 6th described FinFET pipe, described
The source electrode of the 8th FinFET pipe, the source electrode of the 14th described FinFET pipe, the 16th described FinFET pipe
Source electrode, the source electrode of the 18th described FinFET pipe and the source grounding of the 24th described FinFET pipe, described
The front gate of the 9th FinFET pipe, the backgate of the 9th described FinFET pipe, before the 12nd described FinFET pipe
Grid, the backgate of the 12nd described FinFET pipe, the described front gate of the 19th FinFET pipe, the described the 19th
Before the backgate of FinFET pipe, the backgate of the 22nd described FinFET pipe and the 22nd described FinFET pipe
Grid connect and its to connect end be the low order carry signal input part of described one-bit full addres, described one-bit full addres low
Position carry signal input is used for accessing low order carry signal, the described front gate of the tenth FinFET pipe, the described the tenth
The backgate of FinFET pipe, the front gate of the 11st described FinFET pipe, the backgate of the 11st described FinFET pipe,
The front gate of the 20th described FinFET pipe, the described backgate of the 20th FinFET pipe, the described the 21st
The front gate of FinFET pipe and the back-gate connection of the 21st described FinFET pipe and its connection end are that described one adds entirely
The low order carry signal inversion input of device, the low order carry signal inversion input of described one-bit full addres is used for accessing
The inversion signal of low order carry signal, the drain electrode of the 9th described FinFET pipe, the drain electrode of the tenth described FinFET pipe,
The drain electrode of the 11st described FinFET pipe, the drain electrode of the 12nd described FinFET pipe, the 13rd described FinFET
The front gate of pipe, the backgate of the 13rd described FinFET pipe, the front gate of the 14th described FinFET pipe and described
The back-gate connection of 14 FinFET pipes, the drain electrode of the 13rd described FinFET pipe and the 14th described FinFET pipe
Drain electrode connect and its connect end be described one-bit full addres and signal output part, described 15th FinFET pipe
Drain electrode, the drain electrode of the 16th described FinFET pipe, the drain electrode and described second of the 19th described FinFET pipe
The drain electrode of ten FinFET pipes connects, the drain electrode of the 17th described FinFET pipe, the 18th described FinFET pipe
The drain electrode of drain electrode, the drain electrode of the 21st described FinFET pipe and the 22nd described FinFET pipe connects, described
The source electrode of the 19th FinFET pipe, the source electrode of the 20th described FinFET pipe, the 21st described FinFET
The source electrode of pipe, the source electrode of the 22nd described FinFET pipe, the front gate of the 23rd described FinFET pipe, described
The backgate of the 23rd FinFET pipe, the front gate and the described the 24th of the 24th described FinFET pipe
The back-gate connection of FinFET pipe, the drain electrode of the 23rd described FinFET pipe and the 24th described FinFET pipe
Drain electrode connect and its to connect end be the high-order carry signal output end of described one-bit full addres, described one-bit full addres
High-order carry signal output end be used for exporting high-order carry signal.
A kind of one-bit full addres based on FinFET mixed logic the most according to claim 1, it is characterised in that
A described FinFET pipe, the 2nd described FinFET pipe, the 3rd described FinFET pipe, the described the 4th
FinFET pipe, the 5th described FinFET pipe, the 6th described FinFET pipe, the 9th described FinFET pipe, institute
The tenth FinFET pipe stated, described 11st FinFET pipe, the 12nd described FinFET pipe, the described the tenth
Three FinFET pipes, the 14th described FinFET pipe, the 15th described FinFET pipe, the 18th described FinFET
Pipe, the 19th described FinFET pipe, the 20th described FinFET manage, the 21st described FinFET manages,
The 22nd described FinFET pipe, the 23rd described FinFET pipe and the 24th described FinFET pipe are
Low threshold FinFET manages, the 7th described FinFET pipe, the 8th described FinFET pipe, the 16th described FinFET
Pipe and the 17th described FinFET pipe are managed for high threshold FinFET.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222202A (en) * | 2017-04-18 | 2017-09-29 | 宁波大学 | A kind of full adder based on FinFET |
| CN111654280A (en) * | 2020-05-08 | 2020-09-11 | 宁波大学 | One-bit full adder based on three-input TFET device |
| AT525255B1 (en) * | 2022-03-06 | 2023-02-15 | Harald Iglseder Dipl Ing | Flexible logic gate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013131717A1 (en) * | 2012-03-06 | 2013-09-12 | Soitec | Multiplexer, look-up table and fpga |
| CN104617916A (en) * | 2014-12-23 | 2015-05-13 | 宁波大学 | Master-slave flip-flop based on FinFET transistor |
| CN105045556A (en) * | 2015-07-09 | 2015-11-11 | 合肥工业大学 | Dynamic and static mixed adder |
-
2016
- 2016-04-22 CN CN201610259437.6A patent/CN105958998B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013131717A1 (en) * | 2012-03-06 | 2013-09-12 | Soitec | Multiplexer, look-up table and fpga |
| CN104617916A (en) * | 2014-12-23 | 2015-05-13 | 宁波大学 | Master-slave flip-flop based on FinFET transistor |
| CN105045556A (en) * | 2015-07-09 | 2015-11-11 | 合肥工业大学 | Dynamic and static mixed adder |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222202A (en) * | 2017-04-18 | 2017-09-29 | 宁波大学 | A kind of full adder based on FinFET |
| CN111654280A (en) * | 2020-05-08 | 2020-09-11 | 宁波大学 | One-bit full adder based on three-input TFET device |
| CN111654280B (en) * | 2020-05-08 | 2023-09-22 | 深圳市元视芯智能科技有限公司 | One-bit full adder based on three-input TFET device |
| AT525255B1 (en) * | 2022-03-06 | 2023-02-15 | Harald Iglseder Dipl Ing | Flexible logic gate |
| AT525255A4 (en) * | 2022-03-06 | 2023-02-15 | Harald Iglseder Dipl Ing | Flexible logic gate |
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| CN105958998B (en) | 2018-08-14 |
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