CN102299705B - Level switching nand circuit - Google Patents
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- CN102299705B CN102299705B CN201010205605.6A CN201010205605A CN102299705B CN 102299705 B CN102299705 B CN 102299705B CN 201010205605 A CN201010205605 A CN 201010205605A CN 102299705 B CN102299705 B CN 102299705B
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Abstract
The invention relates to a level switching nand circuit, which comprises a first N-type field effect tube, a second N-type field effect tube, a third N-type field effect tube, a fourth N-type field effect tube, a fifth N-type field effect tube, a first P-type field effect tube and a second P-type field effect tube in circuit connection with one another. In a level switching nand circuit unit, double functions of level switching and a nand gate are realized by adopting seven transistors, so that the circuit area is saved, and the product cost is lowered; an output end is provided with two N-type field effect tubes which are connected in series; the grids of the two N-type filed effect tubes are connected with two inputs respectively; VL (Voltage Low) is loaded on the grids; and high conduction capability is realized. The circuit has good compatibility with different processes, and can work at low voltage and low power consumption.
Description
Technical field
The present invention relates to a kind of level shifting circuit, be specifically related to a kind of NAND circuit with level conversion.
Background technology
At present, prior art one: a kind of circuit of typically realizing NOT-AND operation now and completing level conversion as shown in Figure 1, formed by two input nand gates 101 and level shifting circuit 102 cascades, VL (103) is lower supply voltage, the same with the supply voltage that in chip, other digital circuits are used, VH (104) is higher supply voltage; I1 (105) and I2 (106) are 2 input signals, and its voltage range is between 0～VL; Q (107) is output signal, and its voltage range is between 0～VH; Add level conversion with regard to having realized low voltage input signal I1 and I2 to the NOT-AND operation of High voltage output signal Q like this.
The pertinent literature of the prior art: 101 is most typical two input nand gates; 102 is typical level shifting circuits, can referenced patent CN200510029212.3 " level shifting circuit ".
Its shortcoming is, needed pipe number has 10, and carry out a large amount of repeated application in memory circuitry time, the needed pipe number of decoding array of N this unit composition is 10 × N, there is no area advantage.
Prior art two: another follow-on level conversion NAND circuit as shown in Figure 2; This circuit unit only has 5 pipes, has saved a lot of areas than prior art one; I1 is Q end output 0 when " 1 " simultaneously I2 is for " 1 ", and in other situations, Q exports the voltage of VH.Be when " 1 " while, I2 was for " 1 " at I1, node A210 voltage is first charged to the voltage (VT is N pipe threshold) of VL-VT by N pipe 204, then is moved to voltage VH on P pipe 208;
Its shortcoming is, when the N pipe threshold VT in a technique larger, and be accompanied by the reduction (due to the development trend of low-voltage and low-power dissipation on electronic market) of supply voltage VL, thereby node A voltage VL-VT brings following 2 problems by reducing: it is slack-off that 1, the not high enough N of making of node A voltage manages the speed that 206 ducting capacity deficiencies cause that Q point voltage declines, and also causes P to manage 208 ducting capacity deficiencies to cause the slack-off of node A rate of voltage rise and Q point voltage is low not; Thereby this circuit reduces the performance of memory circuitry because reversal rate slack-off will make the reading rate entirety of memory circuitry decline when driving the word line of memory circuitry; 2, when node A brownout because N manages 206 ducting capacity deficiencies and P pipe 207 cannot turn-off completely, Q names a person for a particular job and is maintained at an intermediate level between a 0～VH and cannot be pulled to 0V, and this intermediate level is low not with respect to VH, make P manage 208 ducting capacity not enough and cannot go up the voltage of drawknot point A, make node A voltage also be maintained at an intermediate level between a 0～VH, whole like this circuit will produce the functional issues that cannot overturn, and on VH, causes lasting quiescent current.
Summary of the invention
The invention provides a kind of level conversion NAND circuit, save circuit usable floor area, reduce costs, adapt to work under low-voltage environment, good to the compatibility of different process.
For achieving the above object, the invention provides a kind of level conversion NAND circuit, it is characterized in that, this circuit comprises the first N-type field effect transistor, the second N-type field effect transistor, the 3rd N-type field effect transistor, the 4th N-type field effect transistor, the 5th N-type field effect transistor, a P type field effect transistor and the 2nd P type field effect transistor that circuit connects;
Above-mentioned the first N-type fet gate meets first input end I1, and drain electrode meets signal input part I2, source electrode binding place A, substrate ground connection;
Above-mentioned the second N-type fet gate connects reverse input end
(this reverse input end
signal and the signal of the first output I1 anti-phase each other), drain electrode binding place A, source ground, substrate ground connection;
Above-mentioned the 3rd N-type fet gate binding place A, drain electrode connects output Q, source ground, substrate ground connection;
Above-mentioned the 4th N-type fet gate meets signal input part I2 or meets first input end I1, and drain electrode meets output Q, and source electrode connects the drain electrode of the 5th N-type field effect transistor, substrate ground connection;
Above-mentioned the 5th N-type fet gate meets first input end I1 or meets signal input part I2, and drain electrode connects the source electrode of the 4th N-type field effect transistor, source ground, substrate ground connection;
An above-mentioned P type fet gate binding place A, drain electrode meets output Q, and source electrode meets VH, and substrate meets VH;
Above-mentioned the 2nd P type fet gate meets output Q, drain electrode binding place A, and source electrode meets VH, and substrate meets VH.
Above-mentioned first input end I1, signal input part I2 and reverse input end
for the low pressure digital input signals of 0V～VL; This VL is the supply voltage of the low voltage value of digital circuit.
The High voltage output signal that above-mentioned output Q is 0V～VH; This VH is the supply voltage of high-voltage value, and its magnitude of voltage is higher than VL.
In this circuit, first input end I1, signal input part I2 and reverse input end enter end
logical zero be 0V voltage, logical one is lower VL magnitude of voltage; The logical zero of output Q is 0V voltage, and logical one is higher VH magnitude of voltage.
When first input end I1 is " 0 ", signal input part I2 is " 0 " or " 1 " situation, now reverse input end
for " 1 ", the second N-type field effect transistor 305 is moved node A to ground, and the 3rd N-type field effect transistor and the 5th N-type field effect transistor are turn-offed, and a P type field effect transistor will be moved " 1 " on output Q.
When first input end I1 is " 1 ", signal input part I2 is the situation of " 0 ", now the first N-type field effect transistor is moved node A to the voltage of signal input part I2, and the 3rd N-type field effect transistor and the 4th N-type field effect transistor are turn-offed, and a P type field effect transistor will be moved " 1 " on output Q.
Level conversion NAND circuit of the present invention compared to the prior art, its advantage is, level conversion NAND circuit of the present invention unit adopts seven transistors to realize the dual-use function of level conversion and NAND gate, need ten transistors when NAND gate being separated with level shifting circuit in prior art, save the area of circuit layout, improve the utilization of resources, reduce production costs;
Output of the present invention is provided with the 4th N-type field effect transistor and the 5th N-type field effect transistor of series connection, its grid connects respectively first input end I1 and I2, on grid, load VL, ducting capacity is strong, make level conversion NAND circuit of the present invention unit at work, because technological reason is causing the threshold value VT of N-type field effect transistor too high, or supply voltage VL is too low, can not affect the normal work of circuit, this circuit can be worked under low-voltage and low-power dissipation.
Accompanying drawing explanation
Fig. 1 is the typical NAND gate of prior art one and the circuit diagram of level shifting circuit;
Fig. 2 is the circuit diagram of follow-on level conversion NAND circuit of prior art two;
Fig. 3 is the circuit diagram of a kind of embodiment of level conversion NAND circuit of the present invention;
Fig. 4 is the circuit diagram of a kind of embodiment of level conversion NAND circuit of the present invention;
Fig. 5 is band level conversion of the present invention and circuit diagram non-decoding circuit.
Embodiment
Below in conjunction with accompanying drawing, further illustrate embodiments of the invention.
As shown in Figure 3, for a kind of embodiment of level conversion NAND circuit 507 of the present invention, this unit comprises five N-type field effect transistor and two P type field effect transistor, and it is respectively the first N-type field effect transistor 304, the second N-type field effect transistor 305, the 3rd N-type field effect transistor 306, the 4th N-type field effect transistor 310, the 5th N-type field effect transistor 311, a P type field effect transistor 307 and the 2nd P type field effect transistor 308.
The first N-type field effect transistor 304 grids meet first input end I1 (301), and drain electrode meets signal input part I2 (302), source electrode binding place A (312), substrate ground connection; The second N-type field effect transistor 305 grids connect reverse input end
(303), drain electrode binding place A (312), source ground, substrate ground connection; The 3rd N-type field effect transistor 306 grid binding place A (312), drain electrode connects output Q (309), source ground, substrate ground connection; The 4th N-type field effect transistor 310 grids meet signal input part I2 (302), and drain electrode meets output Q (309), and source electrode connects the drain electrode of the 5th N-type field effect transistor 311, substrate ground connection; The 5th N-type field effect transistor 311 grids meet first input end I1 (301), and drain electrode connects the source electrode of the 4th N-type field effect transistor 310, source ground, substrate ground connection; The one P type field effect transistor 307 grid binding place A (312), drain electrode meets output Q (309), and source electrode meets VH, and substrate meets VH; The 2nd P type field effect transistor 308 grids meet output Q (309), drain electrode binding place A (312), and source electrode meets VH, and substrate meets VH.
Wherein, first input end I1 (301), signal input part I2 (302) and reverse input end
(303) be the low pressure digital input signals of 0V～VL, the supply voltage of the low voltage value that VL is digital circuit.First input end I1 (301) and input
(303) in digital circuit logic, be the relation of paraphase each other, in practical application of the present invention, only have in fact two low pressure inputs, be first input end I1 (301) and signal input part I2 (302), first input end I1 (301) connects a phase inverter (not gate), is reverse input end
(303).And output Q (309) is the High voltage output signal of 0V～VH; VH is the supply voltage of high-voltage value, and its magnitude of voltage is higher than VL.
In this circuit, first input end I1 (301), signal input part I2 (302) and reverse input end enter end
(303) logical zero is 0V voltage, and logical one is lower VL magnitude of voltage; The logical zero of output Q (309) is 0V voltage, and logical one is higher VH magnitude of voltage.
When first input end I1 (301) is " 0 ", signal input part I2 (302) is " 0 " or " 1 " situation, now reverse input end
(303) be " 1 ", the second N-type field effect transistor 305 is moved node A (312) to ground, the 3rd N-type field effect transistor 306 and the 5th N-type field effect transistor 311 are turn-offed, and a P type field effect transistor 307 will be exported on Q (309) and move " 1 " to, i.e. VH magnitude of voltage.
When first input end I1 (301) is " 1 ", signal input part I2 (302) is the situation of " 0 ", now the first N-type field effect transistor 304 is moved node A (312) voltage of signal input part I2 (302) to, be 0V, the 3rd N-type field effect transistor 306 and the 4th N-type field effect transistor 310 are turn-offed, the one P type field effect transistor 307 will be exported on Q (309) and move " 1 " to, i.e. VH magnitude of voltage.
When first input end I1 (301) is " 1 ", signal input part I2 (302) is the situation of " 1 ": under the acting in conjunction of the 4th N-type field effect transistor 310 and the 5th N-type field effect transistor 311, solved the shortcoming of prior art two.Be " 1 " at first input end I1 (301), when signal input part I2 (302) is " 1 ", the 4th N-type field effect transistor 310 and the 5th all conductings of N-type field effect transistor 311, drag down the current potential of exporting Q (309); That add due to the grid of the 4th N-type field effect transistor 310 and the 5th N-type field effect transistor 311 is VL rather than VL-VT (VT is the threshold voltage of N-type field effect transistor), therefore their ducting capacity compared with strong and the current potential of output Q (309) can be drawn enough low; And the decline of the current potential of output Q (309) also makes the ducting capacity of the 2nd P type field effect transistor 308 strengthen, thereby node A (312) is drawn high; The first N-type field effect transistor 304 and the 2nd P type field effect transistor 308 improve node A (312) voltage, the 3rd N-type field effect transistor 306, the 4th N-type field effect transistor 310 and the 5th N-type field effect transistor 311 reduce output Q (309) voltage, under above acting in conjunction, output Q (309) can be turned to logical zero with very fast speed.Even because technological reason causes the threshold V T of N-type field effect transistor too high, or because supply voltage VL is too low, also can normally work with non-unit 507 with level conversion of the present invention.
As shown in Figure 4, for the another kind of embodiment of level conversion NAND circuit 507 of the present invention, this unit comprises these five N-type field effect transistor and two P type field effect transistor, and it is respectively the first N-type field effect transistor 304, the second N-type field effect transistor 305, the 3rd N-type field effect transistor 306, the 4th N-type field effect transistor 310, the 5th N-type field effect transistor 311, a P type field effect transistor 307 and the 2nd P type field effect transistor 308.
The grid of the first N-type field effect transistor 304 meets first input end I1 (301), and drain electrode meets signal input part I2 (302), source electrode binding place A (312), substrate ground connection.The grid of the second N-type field effect transistor 305 connects input
(303), drain electrode binding place A (312), source ground, the grid binding place A (312) of substrate ground connection the 3rd N-type field effect transistor 306, drain electrode connects output Q (309), source ground, substrate ground connection.The grid of the 4th N-type field effect transistor 310 meets first input end I1 (301), and drain electrode meets output Q (309), and source electrode connects the drain electrode of the 5th N-type field effect transistor 311, substrate ground connection; The grid of the 5th N-type field effect transistor 311 meets signal input part I2 (302), and drain electrode connects the source electrode of the 4th N-type field effect transistor 310, its source ground, substrate ground connection.The grid binding place A (312) of the one P type field effect transistor 307, drain electrode meets output Q (309), and source electrode meets VH, and substrate meets VH.The grid of the 2nd P type field effect transistor 308 meets output Q (309), drain electrode binding place A (312), and source electrode meets VH, and substrate meets VH.The difference of embodiment shown in unit and Fig. 3 of the present embodiment is, first input end I1 (301), signal input part I2 (302) exchange that the 4th N-type field effect transistor is connected with the grid of the 5th N-type field effect transistor.
Wherein, first input end I1 (301), signal input part I2 (302) and reverse input end
(303) be the low pressure digital input signals of 0V～VL, the supply voltage of the low voltage value that VL is digital circuit.First input end I1 (301) and reverse input end
(303) in digital circuit logic, be the relation of paraphase each other, in practical application of the present invention, only have in fact two low pressure inputs, be first input end I1 (301) and signal input part I2 (302), first input end I1 (301) connects a phase inverter (not gate), is reverse input end
(303).And output Q (309) is the High voltage output signal of 0V～VH; VH is the supply voltage of high-voltage value, and its magnitude of voltage is higher than VL.
In this circuit, first input end I1 (301), signal input part I2 (302) and reverse input end enter end
(303) logical zero is 0V voltage, and logical one is lower VL magnitude of voltage; The logical zero of output Q (309) is 0V voltage, and logical one is higher VH magnitude of voltage.
When first input end I1 (301) is " 0 ", signal input part I2 (302) is " 0 " or " 1 " situation, now reverse input end
(303) be " 1 ", the second N-type field effect transistor 305 is moved node A (312) to ground, the 3rd N-type field effect transistor 306 and the 5th N-type field effect transistor 310 are turn-offed, and a P type field effect transistor 307 will be exported on Q (309) and move " 1 " to, i.e. VH magnitude of voltage.
When first input end I1 (301) is " 1 ", signal input part I2 (302) is the situation of " 0 ", now the first N-type field effect transistor 304 is moved node A (312) voltage of signal input part I2 (302) to, be 0V, the 3rd N-type field effect transistor 306 and the 4th N-type field effect transistor 311 are turn-offed, the one P type field effect transistor 307 will be exported on Q (309) and move " 1 " to, i.e. VH magnitude of voltage.
When first input end I1 (301) is " 1 ", signal input part I2 (302) is the situation of " 1 ": under the acting in conjunction of the 4th N-type field effect transistor 310 and the 5th N-type field effect transistor 311, solved the shortcoming of prior art two.Be " 1 " at first input end I1 (301), when signal input part I2 (302) is " 1 ", the 4th N-type field effect transistor 310 and the 5th all conductings of N-type field effect transistor 311, drag down the current potential of exporting Q (309); That add due to the grid of the 4th N-type field effect transistor 310 and the 5th N-type field effect transistor 311 is VL rather than VL-VT (VT is the threshold voltage of N-type field effect transistor), therefore their ducting capacity compared with strong and the current potential of output Q (309) can be drawn enough low; And the decline of the current potential of output Q (309) also makes the ducting capacity of the 2nd P type field effect transistor 308 strengthen, thereby node A (312) is drawn high; The first N-type field effect transistor 304 and the 2nd P type field effect transistor 308 improve node A (312) voltage, the 3rd N-type field effect transistor 306, the 4th N-type field effect transistor 310 and the 5th N-type field effect transistor 311 reduce output Q (309) voltage, under above acting in conjunction, output Q (309) can be turned to logical zero with very fast speed.Even because technological reason causes the threshold V T of N-type field effect transistor too high, or because supply voltage VL is too low, also can normally work with non-unit 507 with level conversion of the present invention.
As shown in Figure 5, be a kind of with level conversion and non-decoding circuit, connected into by level conversion NAND circuit 507 circuit of the present invention.This comprises input module 501 with level conversion with non-decoding circuit, the decoding circuit array 502 being connected with the circuit of output terminal of input module 501, the output module 503 being connected with the circuit of output terminal of decoding circuit array 502, and phase inverter 504.
Decoding circuit array 502 comprises several level conversion NAND circuit 507 being connected in parallel.Input module 501 comprises some road I2 input (I2[1 as shown in Figure 5]～I2[N]), is the output of prime decoding circuit, and circuit is connected to the signal input part I2 (302) of each level conversion NAND circuit 507 respectively.Output module 503 comprises some road Q output (Q[1 as shown in Figure 5]～Q[N]), is the output Q (309) of each level conversion NAND circuit unit 507.
First input end I1[1] (505) be connected to the I1 end of each level conversion NAND circuit 507.Input
[1] (506) are first input end I1[1] (505) through the output of phase inverter 504 paraphase, is connected to each level conversion NAND circuit 507
end.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Read after foregoing those skilled in the art, for multiple modification of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (4)
1. a level conversion NAND circuit (507), it is characterized in that, this circuit comprises the first N-type field effect transistor (304), the second N-type field effect transistor (305), the 3rd N-type field effect transistor (306), the 4th N-type field effect transistor (310), the 5th N-type field effect transistor (311), a P type field effect transistor (307) and the 2nd P type field effect transistor (308) that circuit connects;
Described the first N-type field effect transistor (304) grid meets first input end I1 (301), and drain electrode meets signal input part I2 (302), source electrode binding place A (312), substrate ground connection;
Described the second N-type field effect transistor (305) grid connects reverse input end
(303), drain electrode binding place A (312), source ground, substrate ground connection; Described reverse input end
(303) signal of signal and the first output I1 (301) is anti-phase each other;
Described the 3rd N-type field effect transistor (306) grid binding place A (312), drain electrode connects output Q (309), source ground, substrate ground connection;
Described the 4th N-type field effect transistor (310) grid meets signal input part I2 (302), and drain electrode meets output Q (309), and source electrode connects the drain electrode of the 5th N-type field effect transistor (311), substrate ground connection;
Described the 5th N-type field effect transistor (311) grid meets first input end I1 (301), and drain electrode connects the source electrode of the 4th N-type field effect transistor (310), source ground, substrate ground connection;
Described P type field effect transistor (307) grid binding place A (312), drain electrode meets output Q (309), and source electrode meets VH, and substrate meets VH;
Described the 2nd P type field effect transistor (308) grid meets output Q (309), drain electrode binding place A (312), and source electrode meets VH, and substrate meets VH;
Described first input end I1 (301), signal input part I2 (302) and reverse input end
(303) be the low pressure digital input signals of 0V～VL; Described VL is the supply voltage of the low voltage value of digital circuit;
Described VH is the supply voltage of high-voltage value, and its magnitude of voltage is higher than VL.
2. level conversion NAND circuit as claimed in claim 1, is characterized in that, described output Q (309) is the High voltage output signal of 0V～VH.
3. a level conversion NAND circuit (507), it is characterized in that, this circuit comprises the first N-type field effect transistor (304), the second N-type field effect transistor (305), the 3rd N-type field effect transistor (306), the 4th N-type field effect transistor (310), the 5th N-type field effect transistor (311), a P type field effect transistor (307) and the 2nd P type field effect transistor (308) that circuit connects;
Described the first N-type field effect transistor (304) grid meets first input end I1 (301), and drain electrode meets signal input part I2 (302), source electrode binding place A (312), substrate ground connection;
Described the second N-type field effect transistor (305) grid connects reverse input end
(303), drain electrode binding place A (312), source ground, substrate ground connection; Described reverse input end
(303) signal of signal and the first output I1 (301) is anti-phase each other;
Described the 3rd N-type field effect transistor (306) grid binding place A (312), drain electrode connects output Q (309), source ground, substrate ground connection;
Described the 4th N-type field effect transistor (310) grid meets first input end I1 (301), and drain electrode meets output Q (309), and source electrode connects the drain electrode of the 5th N-type field effect transistor (311), substrate ground connection;
Described the 5th N-type field effect transistor (311) grid meets signal input part I2 (302), and drain electrode connects the source electrode of the 4th N-type field effect transistor (310), source ground, substrate ground connection;
Described P type field effect transistor (307) grid binding place A (312), drain electrode meets output Q (309), and source electrode meets VH, and substrate meets VH;
Described the 2nd P type field effect transistor (308) grid meets output Q (309), drain electrode binding place A (312), and source electrode meets VH, and substrate meets VH;
Described first input end I1 (301), signal input part I2 (302) and reverse input end
(303) be the low pressure digital input signals of 0V～VL; Described VL is the supply voltage of the low voltage value of digital circuit;
Described VH is the supply voltage of high-voltage value, and its magnitude of voltage is higher than VL.
4. level conversion NAND circuit as claimed in claim 3, is characterized in that, described output Q (309) is the High voltage output signal of 0V～VH.
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| CN106685391A (en) * | 2016-12-30 | 2017-05-17 | 合肥恒烁半导体有限公司 | Level converting circuit |
| CN107147387B (en) * | 2017-06-06 | 2020-07-31 | 上海华力微电子有限公司 | Level conversion NAND circuit |
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| CN1497853A (en) * | 2002-09-25 | 2004-05-19 | ��ʽ����뵼����Դ�о��� | Clock-controlled inverter, 'NAND' gate, 'NOR' gate and shift register |
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| JP2806335B2 (en) * | 1996-01-17 | 1998-09-30 | 日本電気株式会社 | Logic circuit and semiconductor integrated circuit using the same |
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