CN106847329B - A kind of three value 4-81 line address decoders realized using CNFET - Google Patents
A kind of three value 4-81 line address decoders realized using CNFET Download PDFInfo
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- CN106847329B CN106847329B CN201611252909.1A CN201611252909A CN106847329B CN 106847329 B CN106847329 B CN 106847329B CN 201611252909 A CN201611252909 A CN 201611252909A CN 106847329 B CN106847329 B CN 106847329B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention discloses a kind of three values, 4 81 line address decoders realized using CNFET, including ten three values, 29 line address decoders, three values, 29 line address decoder includes identical three values, the 13 line address decoder of two structures, identical three input nand gate of nine structures and the identical phase inverter of nine structures, three values, 13 line address decoder is managed including the first CNFET, 2nd CNFET is managed, 3rd CNFET is managed, 4th CNFET is managed, 5th CNFET is managed, 6th CNFET is managed, 7th CNFET is managed, 8th CNFET is managed, 9th CNFET is managed, tenth CNFET is managed and the 11st CNFET pipes；Advantage is that power consumption is relatively low, and delay is smaller.
Description
Technical field
The present invention relates to a kind of 4-81 lines address decoders, more particularly, to a kind of three value 4-81 realized using CNFET
Line address decoder.
Background technology
Static RAM (Static Random Access Memory, SRAM) read or write speed is fast, common to deal with
Interface circuit between device and memory, the cache as processor.With super large-scale integration (Very Large
Scale Integration, VLSI) development, processor clock frequency increase, higher want is proposed to SRAM read or write speeds
It asks.Important component part of the address decoder as SRAM, address decoder delay account for the very big by one of SRAM read-write delays
Part, therefore the read or write speed of SRAM and power consumption and the performance of address decoder have prodigious relationship.High performance address decoder
Design to improve SRAM read or write speed reduce power consumption play a significantly greater role.
Traditional address decoder is designed using CMOS technology, and with feature size downsizing to nanometer scale, interconnection line is parasitic
The problems such as gate delay that effect is brought, interconnection crosstalk, is increasingly severe, and the operating rate of address decoder encounters prodigious choose
War.And the carbon nanotube (Carbon Nanotube, CNT) of quasi- one-dimentional structure with ballistic transport characteristic, chemical property because stablizing
The features such as convenient with grid voltage modulation, there is the possibility instead of CMOS technology.Carbon nanometer field can be made using CNTs as conducting channel
Effect transistor (Carbon Nanotube Field Effect Transistor, CNFET).Document DENG J, WONG H S
P.A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors
Including Nonidealities and Its Application-Part I:Model of the Intrinsic
Channel Region[J].IEEE Transactions on Electron Devices,2007,54(12):3186-
3194. studies have shown that the interelectrode capacity of carbon nano field-effect transistor is only the 4% of MOSFET interelectrode capacities, therefore utilizes CNFET
The address decoder of design has smaller delay, and the operating rate of address decoder can be improved.In Binary Logic System, n is defeated
Enter address decoder, can control 2 in sramnThe read-write operation of a sram cell.And in multi-value logic system, n inputs ground
Location decoder can control more sram cells.Such as the three-valued logic of minimum basis, logic value is " 0 ", " 1 " and " 2 "；Three values
N input address decoder in sram, can control 3nThe read-write operation of a SRAM, to improve the decoding effect of address decoder
Rate.When controlling the sram cell of same number, the number of pins of encapsulation can be reduced using three value address decoders.
In view of this, design that a kind of power consumption is relatively low, the smaller three value 4-81 line address decoding utensils realized using CNFET of delay
It is significant.
Invention content
Technical problem to be solved by the invention is to provide a kind of power consumption is relatively low, delay is smaller to be realized using CNFET
Three value 4-81 line address decoders.
Technical solution is used by the present invention solves above-mentioned technical problem：A kind of three value 4-81 realized using CNFET
Line address decoder, including ten three value 2-9 line address decoders, the three value 2-9 line address decoders have Enable Pin,
First input end, the second input terminal, the first output end, second output terminal, third output end, the 4th output end, the 5th output end,
6th output end, the 7th output end, the 8th output end and the 9th output end；Three value 2-9 line address decoders point described in ten
Not Wei the one or three value 2-9 lines address decoder, the two or three value 2-9 lines address decoder, the three or three value 2-9 lines address decoder,
Four or three value 2-9 lines address decoder, the five or three value 2-9 lines address decoder, the six or three value 2-9 lines address decoder, the 7th
Three value 2-9 lines address decoders, the eight or three value 2-9 lines address decoder, the 9th 3 value 2-9 lines address decoder and the 13rd value
2-9 line address decoders；The first output end and the two or the three value 2-9 of one or the three value 2-9 line address decoders
The Enable Pin of line address decoder connects, the second output terminal of the one or the three value 2-9 line address decoders and described the
The Enable Pins of three or three value 2-9 line address decoders connects, the third output end of the one or the three value 2-9 line address decoders and
The Enable Pin of four or the three value 2-9 line address decoders connects, and the 4th of the one or the three value 2-9 line address decoders the
Output end is connected with the Enable Pin of the five or the three value 2-9 line address decoders, the one or the three value 2-9 line address decodings
5th output end of device is connected with the Enable Pin of the six or the three value 2-9 line address decoders, the one or the three value 2-9 lines
6th output end of address decoder is connected with the Enable Pin of the seven or the three value 2-9 line address decoders, and described first
7th output end of three value 2-9 line address decoders is connected with the Enable Pin of the eight or the three value 2-9 line address decoders, institute
8th output end of the one or the three value 2-9 line address decoders stated and enabling for the 9th 3 value 2-9 line address decoders
End connection, the 9th output end and the 13rd value 2-9 line address decodings of the one or the three value 2-9 line address decoders
The Enable Pin of device connects, first input end, the three or the three value 2-9 lines of the two or the three value 2-9 line address decoders
The first input end of address decoder, the first input end of the four or the three value 2-9 line address decoders, the described the 5th 3
The first input end, described of the first input end of value 2-9 line address decoders, the six or the three value 2-9 line address decoders
The first input ends of the seven or three value 2-9 line address decoders, the eight or the three value 2-9 line address decoders the first input
End, the first input end of the 9th 3 value 2-9 line address decoders and the 13rd value 2-9 line address decoders
The first input end that first input end connects and its connecting pin is the three value 4-81 line address decoders, the described the 2nd 3
The second input terminal, described of second input terminal of value 2-9 line address decoders, the three or the three value 2-9 line address decoders
The second input terminal of the four or three value 2-9 line address decoders, the five or the three value 2-9 line address decoders the second input
End, the second input terminal of the six or the three value 2-9 line address decoders, the seven or the three value 2-9 line address decoders
Second input terminal, the second input terminal of the eight or the three value 2-9 line address decoders, the 9th 3 value 2-9 lines address
Second input terminal of decoder is connected with the second input terminal of the 13rd value 2-9 line address decoders and its connecting pin is
Second input terminal of the three value 4-81 line address decoders, the first of the one or the three value 2-9 line address decoders are defeated
Enter the third input terminal that end is the three value 4-81 line address decoders, the one or the three value 2-9 line address decoders
Second input terminal is the 4th input terminal of the three value 4-81 line address decoders, and the one or the three value 2-9 lines address is translated
The Enable Pin of code device is the Enable Pin of the three value 4-81 line address decoders；
The three value 2-9 line address decoders include the identical three values 1-3 lines address decoder of two structures, nine knots
Identical three input nand gate of structure and the identical phase inverter of nine structures；The three value 1-3 line address decoders have input
End, the first output end, second output terminal and third output end, three input nand gates have first input end, second defeated
Enter end, third input terminal and output end；The three value 1-3 line address decoders are managed including the first CNFET, the 2nd CNFET is managed,
3rd CNFET pipes, the 4th CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 7th CNFET pipes, the 8th CNFET pipes, the 9th
CNFET pipes, the tenth CNFET pipes and the 11st CNFET pipes；3rd CNFET is managed, the 4th CNFET is managed, is described
7th CNFET pipes, the 8th CNFET pipes and the tenth CNFET pipes are that p-type CNFET is managed, and described first
CNFET pipes, the 2nd CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 9th CNFET
Pipe and the 11st CNFET pipes are N-type CNFET pipes；Grid, the 4th CNFET of the first CNFET pipes
The source electrode of pipe, the source electrode of the 7th CNFET pipes, the source electrode of the 8th CNFET pipes and the tenth CNFET pipes
Source electrode accesses the first power supply, and the drain electrode of the first CNFET pipes accesses second source, and the second source is described
The half of first power supply；The grid of the 8th CNFET pipes, the grid of the 9th CNFET pipes, the described the tenth
The grid of CNFET pipes is connected with the grid of the 11st CNFET pipes and its connecting pin is that the three value 1-3 lines addresses are translated
The input terminal of code device；The grid of 2nd CNFET pipes, the grid of the 3rd CNFET pipes, the 8th CNFET
The drain electrode of pipe and the drain electrode of the 9th CNFET pipes connect and its connecting pin is the three value 1-3 line address decoders
First output end；The source electrode of 2nd CNFET pipes, the source electrode of the 5th CNFET pipes, the 6th CNFET pipes
Source electrode, the 9th CNFET pipes source electrode and the 11st CNFET pipes source grounding；Described the 6th
The grid of CNFET pipes, the 7th CNFET pipes grid, the tenth CNFET pipes drain electrode and the described the 11st
The drain electrode of CNFET pipes connects, the grid of the 4th CNFET pipes, the grid of the 5th CNFET pipes, the described the 6th
The drain electrode of CNFET pipes and the drain electrode of the 7th CNFET pipes connect and its connecting pin is the three value 1-3 line address decodings
The third output end of device；The source electrodes of the first CNFET pipes, the draining of the 2nd CNFET pipes, the third
The drain electrode of CNFET pipes and the drain electrode of the 5th CNFET pipes connect and its connecting pin is the three value 1-3 line address decodings
The second output terminal of device；The source electrode of the 3rd CNFET pipes is connected with the drain electrode of the 4th CNFET pipes；Described in two
Three value 1-3 line address decoders be respectively the one or three value 1-3 lines address decoder and the two or three value 1-3 line address decoders,
Three input nand gates described in nine be respectively the one or three input nand gate, the two or three input nand gate, the three or three input with it is non-
Door, the four or three input nand gate, the five or three input nand gate, the six or three input nand gate, the seven or three input nand gate, the eight or three
Input nand gate and the 9th 3 input nand gate, the phase inverter described in nine are respectively the first phase inverter, the second phase inverter, third
Phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter and the 9th phase inverter；Institute
The input terminal for the one or the three value 1-3 line address decoders stated is the first input end of the three value 2-9 line address decoders, institute
The input terminal for the two or the three value 1-3 line address decoders stated is the second input terminal of the three value 2-9 line address decoders, institute
First output end of the one or the three value 1-3 line address decoders stated is inputted with the second of the one or three input nand gate respectively
Second input terminal at end, the second input terminal of the two or three input nand gate and the three or three input nand gate connects
It connects；The second output terminal of one or the three value 1-3 line address decoders respectively with the four or three input nand gate
Second input of two input terminals, the second input terminal of the five or three input nand gate and the six or three input nand gate
End connection；The third output end of one or the three value 1-3 line address decoders respectively with the seven or three input nand gate
The second input terminal, the eight or three input nand gate the second input terminal and the 9th 3 input nand gate second
Input terminal connects；First output end of the two or the three value 1-3 line address decoders respectively with described one or three input with
The third input terminal of NOT gate, the third input terminal of the four or three input nand gate and the seven or three input nand gate
Third input terminal connects；The second output terminal of two or the three value 1-3 line address decoders is defeated with described the two or three respectively
Enter the third input terminal of NAND gate, the third input terminal of the five or three input nand gate and the described the 8th 3 input with it is non-
The third input terminal connection of door；The third output end of two or the three value 1-3 line address decoders respectively with the third
The third input terminal of three input nand gates, the third input terminal of the six or three input nand gate and the described the 9th 3 input
The third input terminal of NAND gate connects；The first input end of one or three input nand gate, the described the 2nd 3 input with
The first input end of NOT gate, the first input end of the three or three input nand gate, the four or three input nand gate
First input end, the first input end of the five or three input nand gate, the six or three input nand gate it is first defeated
Enter end, the first input end of the seven or three input nand gate, the eight or three input nand gate first input end and
The first input end of 9th 3 input nand gate connects and its connecting pin is the three value 2-9 line address decoders
Enable Pin；The output end of one or three input nand gate is connected with the input terminal of first phase inverter, and described
The output end of two or three input nand gates is connected with the input terminal of second phase inverter, the three or three input nand gate
Output end is connected with the input terminal of the third phase inverter, the output end of the four or three input nand gate and described
The input terminal of four phase inverters connects, the input terminal of the output end and the 5th phase inverter of the five or three input nand gate
Connection, the output end of the six or three input nand gate are connected with the input terminal of the hex inverter, and the described the 7th
The output end of three input nand gates is connected with the input terminal of the 7th phase inverter, the eight or three input nand gate it is defeated
Outlet is connected with the input terminal of the 8th phase inverter, the output end and the described the 9th of the 9th 3 input nand gate
The input terminal of phase inverter connects；The output end of first phase inverter is the first of the three value 2-9 line address decoders
Output end, the output end of second phase inverter is the second output terminal of the three value 2-9 line address decoders, described
The output end of third phase inverter is the third output end of the three value 2-9 line address decoders, the 4th phase inverter
Output end is the 4th output end of the three value 2-9 line address decoders, and the output end of the 5th phase inverter is described
Three value 2-9 line address decoders the 5th output end, the output end of the hex inverter is for the three value 2-9 lines
6th output end of location decoder, the output end of the 7th phase inverter are the of the three value 2-9 line address decoders
Seven output ends, the output end of the 8th phase inverter is the 8th output end of the three value 2-9 line address decoders, described
The 9th phase inverter output end be the three value 2-9 line address decoders the 9th output end.
The threshold voltage of the first CNFET pipes is 0.428v, the threshold voltage of the 2nd CNFET pipes and described
The threshold voltages of the 5th CNFET pipes be 0.557v, the threshold voltage and the described the 4th of the 3rd CNFET pipes
The threshold voltage of CNFET pipes is -0.557v, the threshold voltages of the 6th CNFET pipes and the 9th CNFET pipes
Threshold voltage is 0.289v, and the threshold voltage of the 7th CNFET pipes and the threshold voltage of the 8th CNFET pipes are equal
Threshold voltage for -0.557v, the tenth CNFET pipes is -0.289v, the threshold voltage of the 11st CNFET pipes
For 0.557v.
The caliber of the first CNFET pipes is 1.018nm, the caliber of the 2nd CNFET pipes, the third
The caliber of CNFET pipes, the caliber of the 4th CNFET pipes, the caliber of the 5th CNFET pipes, the 7th CNFET
The caliber of the caliber of pipe, the caliber of the 8th CNFET pipes and the 11st CNFET pipes is 0.783nm, described
The caliber of the caliber of 6th CNFET pipes and the 9th CNFET pipes is 1.487nm, the caliber of the tenth CNFET pipes
For 1.488nm.The circuit can further decrease power consumption and delay using lower supply voltage come driving circuit.
First power supply is 0.9v, and the second source is 0.45v.The circuit is using the first power supply and the second electricity
Source obtains three value output response signals, improves the stability of circuit.
Three input nand gates include the 12nd CNFET pipes, the 13rd CNFET pipes, the 14th CNFET pipes, the tenth
Five CNFET pipes, the 16th CNFET pipes, the 17th CNFET pipes and the 18th CNFET pipes；12nd CNFET is managed, is described
The 16th CNFET pipes and the 17th CNFET pipes be p-type CNFET pipe, it is the 13rd CNFET pipes, described
14th CNFET pipes, the 15th CNFET pipes and the 18th CNFET pipes are N-type CNFET pipes；Described
The source electrode of 12 CNFET pipes, the source electrode of the 16th CNFET pipes, the source electrode of the 17th CNFET pipes and described
The grid of 18th CNFET pipes accesses first power supply, the drain electrode accesses of the 18th CNFET pipes it is described the
Two power supplys；The grid of the 12nd CNFET pipes is connected with the grid of the 13rd CNFET pipes and its connecting pin is institute
The first input end for three input nand gates stated, the draining of the 12nd CNFET pipes, the 13rd CNFET pipes
Drain electrode, the draining of the 16th CNFET pipes, the drain electrode of the 17th CNFET pipes and the 18th CNFET pipe
Source electrode connection and its connecting pin be three input nand gates output end, the source electrode of the 13rd CNFET pipes and
The drain electrode of the 14th CNFET pipes connects, the source electrode of the 14th CNFET pipes and the 15th CNFET pipes
Drain electrode connection, the grid of the 14th CNFET pipes is connected with the grid of the 16th CNFET pipes and its connecting pin
Source electrode for the second input terminal of three input nand gates, the 15th CNFET pipes is grounded, and the described the 15th
The grid of CNFET pipes is connected with the grid of the 17th CNFET pipes and its connecting pin is three input nand gates
Third input terminal.The circuit can further decrease power consumption and delay using lower supply voltage come driving circuit.
The caliber of 12nd CNFET pipes, the caliber of the 13rd CNFET pipes, the 14th CNFET
The caliber and the described the 17th of the caliber of pipe, the caliber of the 15th CNFET pipes, the 16th CNFET pipes
The caliber of CNFET pipes is 0.783nm, and the caliber of the 18th CNFET pipes is 1.018nm.The circuit can utilize more
Low supply voltage carrys out driving circuit, further decreases power consumption and delay.
The phase inverter includes the 19th CNFET pipes, the 20th CNFET pipes and the 21st CNFET pipes, and described the
19 CNFET pipes are p-type CNFET pipes, and the 20th CNFET pipes and the 21st CNFET pipes are N-type
CNFET is managed；The grid of the source electrode of the 19th CNFET pipes and the 21st CNFET pipes accesses described the
The drain electrode of one power supply, the 21st CNFET pipes accesses the second source, the grid of the 19th CNFET pipes
The input terminal that pole is connected with the grid of the 20th CNFET pipes and its connecting pin is the phase inverter, the described the tenth
The draining of nine CNFET pipes, the drain electrode of the 20th CNFET pipes is connected with the source electrode of the 21st CNFET pipes and
Its connecting pin is the output end of the phase inverter, the source electrode ground connection of the 20th CNFET pipes.The circuit utilizes CNFET
The multi-Vt characteristic of pipe, it is convenient that grid voltage is adjusted, and improves stability.
The caliber of the 19th CNFET pipes and the caliber of the 20th CNFET pipes are 0.783nm, described
The 21st CNFET pipes caliber be 1.018nm.The circuit utilizes the multi-Vt characteristic of CNFET pipes, grid voltage to adjust just
Victory improves stability.
Compared with the prior art, the advantages of the present invention are as follows realize three value 4- by ten three value 2-9 line address decoders
81 line address decoders, three value 2-9 line address decoders include the identical three values 1-3 lines address decoder of two structures, nine
Identical three input nand gate of structure and the identical phase inverter of nine structures, three value 1-3 line address decoders include the first CNFET
Pipe, the 2nd CNFET pipes, the 3rd CNFET pipes, the 4th CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 7th CNFET pipes, the
Eight CNFET pipes, the 9th CNFET pipes, the tenth CNFET pipes and the 11st CNFET pipes；With existing two-value 6-64 line address decoders
It compares, the three value 4-81 line address decoders of the invention realized using CNFET can control more sram cells, decoding efficiency
Height, while coding chip packaging pin number is also reduced, power consumption at least reduces 37.1%, at least reduces 41.1%, and power consumption is relatively low,
Delay is smaller.
Description of the drawings
Fig. 1 is the structure chart for the three value 4-81 line address decoders of the present invention realized using CNFET；
Fig. 2 is three value 2-9 line address decoders in the three value 4-81 line address decoders of the present invention realized using CNFET
Structure chart；
Fig. 3 is the circuit diagram of the three value 1-3 line address decoders of the present invention；
Fig. 4 (a) is the electricity of three input nand gates of the three value 4-81 line address decoders of the present invention realized using CNFET
Lu Tu；
Fig. 4 (b) is the symbol of three input nand gates of the three value 4-81 line address decoders of the present invention realized using CNFET
Number figure；
Fig. 5 (a) is the circuit diagram of the phase inverter for the three value 4-81 line address decoders of the present invention realized using CNFET；
Fig. 5 (b) is the graphical diagram of the phase inverter for the three value 4-81 line address decoders of the present invention realized using CNFET；
Fig. 6 is address decoder input and output port number purpose relation curve.
Specific implementation mode
Below in conjunction with attached drawing embodiment, present invention is further described in detail.
Embodiment：As shown in Figure 1, Figure 2 and Figure 3, a kind of three value 4-81 line address decoders realized using CNFET, packet
Ten three value 2-9 line address decoders are included, three value 2-9 line address decoders have Enable Pin, first input end, the second input
End, the first output end, second output terminal, third output end, the 4th output end, the 5th output end, the 6th output end, the 7th output
End, the 8th output end and the 9th output end；Ten three value 2-9 line address decoders are respectively the one or three value 2-9 line address decodings
Device A1, the two or three value 2-9 line address decoders A2, the three or three value 2-9 line address decoders A3, the four or three value 2-9 lines address are translated
Code device A4, the five or three value 2-9 line address decoders A5, the six or three value 2-9 line address decoders A6, the seven or three value 2-9 lines address
Decoder A7, the eight or three value 2-9 line address decoders A8, the 9th 3 value 2-9 line address decoder A9 and the 13rd value 2-9 lines
Location decoder A10；The first output end and the two or three value 2-9 line address decoders A2 of one or three value 2-9 line address decoders A1
Enable Pin connection, the second output terminal and the three or three value 2-9 line address decoders A3 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the third output end and the four or three value 2-9 line address decoders A4 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the 4th output end and the five or three value 2-9 line address decoders A5 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the 5th output end and the six or three value 2-9 line address decoders A6 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the 6th output end and the seven or three value 2-9 line address decoders A7 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the 7th output end and the eight or three value 2-9 line address decoders A8 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the 8th output end and the 9th 3 value 2-9 line address decoders A9 of the one or three value 2-9 line address decoders A1
Enable Pin connection, the 9th output end and the 13rd value 2-9 line address decoders of the one or three value 2-9 line address decoders A1
The Enable Pin of A10 connects, first input end, the three or the three value 2-9 line address decoders of the two or three value 2-9 line address decoders A2
First input end, the five or the three value 2-9 line address decoders of the first input end of A3, the four or three value 2-9 line address decoders A4
First input end, the seven or the three value 2-9 line address decoders of the first input end of A5, the six or three value 2-9 line address decoders A6
First input end, the 9th 3 value 2-9 line address decoders of the first input end of A7, the eight or three value 2-9 line address decoders A8
The first input end of the first input end of A9 and the 13rd value 2-9 line address decoders A10 connect and its connecting pin is three value 4-
The first input end of 81 line address decoders, the second input terminal, the three or the three value 2-9 of the two or three value 2-9 line address decoders A2
The second input terminal, the five or the three value 2-9 of the second input terminal of line address decoder A3, the four or three value 2-9 line address decoders A4
The second input terminal, the seven or the three value 2-9 of the second input terminal of line address decoder A5, the six or three value 2-9 line address decoders A6
The second input terminal, the 9th 3 value 2-9 of the second input terminal of line address decoder A7, the eight or three value 2-9 line address decoders A8
The second input terminal of the second input terminal of line address decoder A9 and the 13rd value 2-9 line address decoders A10 connect and it connects
Connect the second input terminal that end is three value 4-81 line address decoders, the first input end of the one or three value 2-9 line address decoders A1
The second input terminal for the third input terminal of three value 4-81 line address decoders, the one or three value 2-9 line address decoders A1 is three
The Enable Pin of 4th input terminal of value 4-81 line address decoders, the one or three value 2-9 line address decoders A1 is three value 4-81 lines
The Enable Pin of address decoder；Three value 2-9 line address decoders include the identical three values 1-3 lines address decoder of two structures,
Identical three input nand gate of nine structures and the identical phase inverter of nine structures；Three value 1-3 line address decoders have input
End, the first output end, second output terminal and third output end, three input nand gates have first input end, the second input terminal, the
Three input terminals and output end；Three value 1-3 line address decoders include the first CNFET pipes T1, the 2nd CNFET pipes T2, the 3rd CNFET
Pipe T3, the 4th CNFET pipes T4, the 5th CNFET pipes T5, the 6th CNFET pipes T6, the 7th CNFET pipes T7, the 8th CNFET pipes T8,
Nine CNFET pipes T9, the tenth CNFET pipes T10 and the 11st CNFET pipes T11；3rd CNFET pipes T3, the 4th CNFET pipes T4, the 7th
CNFET pipes T7, the 8th CNFET pipes T8 and the tenth CNFET pipes T10 are p-type CNFET pipes, the first CNFET pipes T1, the 2nd CNFET
Pipe T2, the 5th CNFET pipes T5, the 6th CNFET pipes T6, the 9th CNFET pipes T9 and the 11st CNFET pipes T11 are N-type CNFET
Pipe；Source electrode, the 8th CNFET pipes T8 of the grid of first CNFET pipes T1, the source electrode of the 4th CNFET pipes T4, the 7th CNFET pipes T7
Source electrode and the source electrode of the tenth CNFET pipes T10 access the first power supply Vdd, the drain electrode of the first CNFET pipes T1 accesses second source
Vdd1, second source Vdd1 are the half of the first power supply Vdd；The grid of 8th CNFET pipes T8, the grid of the 9th CNFET pipes T9,
The grid of tenth CNFET pipes T10 and the grid of the 11st CNFET pipes T11 connect and its connecting pin is three value 1-3 line address decodings
The input terminal of device；The drain electrode and the 9th of the grid of 2nd CNFET pipes T2, the grid, the 8th CNFET pipes T8 of the 3rd CNFET pipes T3
The drain electrode connection of CNFET pipes T9 and the first output end that its connecting pin is three value 1-3 line address decoders；2nd CNFET pipes T2
Source electrode, the source electrode of the 5th CNFET pipes T5, the source electrode of the 6th CNFET pipes T6, the 9th CNFET pipes T9 source electrode and the 11st
The source grounding of CNFET pipes T11；The grid of 6th CNFET pipes T6, grid, the tenth CNFET pipes T10 of the 7th CNFET pipes T7
Drain electrode connected with the drain electrode of the 11st CNFET pipes T11, the grid of the 4th CNFET pipes T4, the grid of the 5th CNFET pipes T5,
The drain electrode of six CNFET pipes T6 and the drain electrode connection of the 7th CNFET pipes T7 and its connecting pin is three value 1-3 line address decoders the
Three output ends；The drain electrode of the source electrode, the 2nd CNFET pipes T2 of first CNFET pipes T1, the drain electrode and the 5th of the 3rd CNFET pipes T3
The drain electrode connection of CNFET pipes T5 and the second output terminal that its connecting pin is three value 1-3 line address decoders；3rd CNFET pipes T3
Source electrode and the 4th CNFET pipes T4 drain electrode connection；Two three value 1-3 line address decoders are respectively the one or three value 1-3 lines
Location decoder U1 and the two or three value 1-3 lines address decoder U2, nine three input nand gates are respectively the one or three input nand gate
G1, the two or three input nand gate G2, the three or three input nand gate G3, the four or three input nand gate G4, the five or three input nand gate
G5, the six or three input nand gate G6, the seven or three input nand gate G7, the eight or three input nand gate G8 and the 9th 3 input nand gate
G9, nine phase inverters are respectively the first phase inverter F1, the second phase inverter F2, third phase inverter F3, the 4th phase inverter F4, the 5th anti-
Phase device F5, hex inverter F6, the 7th phase inverter F7, the 8th phase inverter F8 and the 9th phase inverter F9；One or three value 1-3 lines address
The input terminal of decoder U1 is the first input end of three value 2-9 line address decoders, the two or three value 1-3 line address decoders U2's
Input terminal is the second input terminal of three value 2-9 line address decoders, the first output end of the one or three value 1-3 line address decoders U1
It is defeated with the second input terminal of the one or three input nand gate G1, the second input terminal of the two or three input nand gate G2 and the three or three respectively
Enter the second input terminal connection of NAND gate G3；The second output terminal of one or three value 1-3 line address decoders U1 is respectively with the four or three
The second input terminal of input nand gate G4, the second input terminal of the five or three input nand gate G5 and the six or three input nand gate G6
Second input terminal connects；The third output end of one or three value 1-3 line address decoders U1 respectively with the seven or three input nand gate G7
The second input terminal, the eight or three input nand gate G8 the second input terminal and the 9th 3 input nand gate G9 the second input terminal connect
It connects；The first output end of two or three value 1-3 line address decoders U2 respectively with the third input terminal of the one or three input nand gate G1,
The third input terminal connection of the third input terminal and the seven or three input nand gate G7 of four or three input nand gate G4；Two or three value 1-
The second output terminal of 3 line address decoder U2 respectively with the third input terminal of the two or three input nand gate G2, the five or three input with
The third input terminal connection of the third input terminal and the eight or three input nand gate G8 of NOT gate G5；Two or three value 1-3 line address decodings
The third output end of the device U2 third with the third input terminal of the three or three input nand gate G3, the six or three input nand gate G6 respectively
The third input terminal of input terminal and the 9th 3 input nand gate G9 connect；The first input end of one or three input nand gate G1,
The first input end of two or three input nand gate G2, first input end, the four or three input nand gate of the three or three input nand gate G3
The first input end of G4, the first input end of the five or three input nand gate G5, the six or three input nand gate G6 first input end,
The first input end of seven or three input nand gate G7, the first input end of the eight or three input nand gate G8 and the 9th 3 input with it is non-
The first input end connection of door G9 and the Enable Pin that its connecting pin is three value 2-9 line address decoders；One or three input nand gate
The input terminal of the output end of G1 and the first phase inverter F1 connect, the output end of the two or three input nand gate G2 and the second phase inverter F2
Input terminal connection, the output end of the three or three input nand gate G3 connect with the input terminal of third phase inverter F3, and the four or three inputs
The input terminal of the output end of NAND gate G4 and the 4th phase inverter F4 connect, and the output end of the five or three input nand gate G5 and the 5th is instead
The input terminal of phase device F5 connects, the input terminal connection of the output end and hex inverter F6 of the six or three input nand gate G6, and the 7th
The connection of the input terminal of the output end of three input nand gate G7 and the 7th phase inverter F7, the output end of the eight or three input nand gate G8 and
The input terminal of 8th phase inverter F8 connects, and the output end of the 9th 3 input nand gate G9 and the input terminal of the 9th phase inverter F9 connect
It connects；The output end of first phase inverter F1 is the first output end of three value 2-9 line address decoders, the output end of the second phase inverter F2
Output end for the second output terminal of three value 2-9 line address decoders, third phase inverter F3 is three value 2-9 line address decoders
Third output end, the output end of the 4th phase inverter F4 are the 4th output end of three value 2-9 line address decoders, the 5th phase inverter F5
Output end be three value 2-9 line address decoders the 5th output end, the output end of hex inverter F6 is three value 2-9 lines addresses
6th output end of decoder, the output end of the 7th phase inverter F7 are the 7th output end of three value 2-9 line address decoders, the 8th
The output end of phase inverter F8 is the 8th output end of three value 2-9 line address decoders, and the output end of the 9th phase inverter F9 is three values
9th output end of 2-9 line address decoders.
In the present embodiment, the threshold voltage of the first CNFET pipes T1 is 0.428v, the threshold voltage of the 2nd CNFET pipes T2 and
The threshold voltage of 5th CNFET pipes T5 is 0.557v, the threshold of the threshold voltage and the 4th CNFET pipes T4 of the 3rd CNFET pipes T3
Threshold voltage is -0.557v, and the threshold voltage of the 6th CNFET pipes T6 and the threshold voltage of the 9th CNFET pipes T9 are 0.289v,
The threshold voltage of 7th CNFET pipes T7 and the threshold voltage of the 8th CNFET pipes T8 are -0.557v, the tenth CNFET pipes T10's
Threshold voltage is -0.289v, and the threshold voltage of the 11st CNFET pipes T11 is 0.557v.
In the present embodiment, the caliber of the first CNFET pipes T1 is 1.018nm, caliber, the 3rd CNFET of the 2nd CNFET pipes T2
The caliber of pipe T3, the caliber of the 4th CNFET pipes T4, the caliber of the 5th CNFET pipes T5, the caliber of the 7th CNFET pipes T7, the 8th
The caliber of the caliber of CNFET pipes T8 and the 11st CNFET pipes T11 are 0.783nm, the caliber and the 9th of the 6th CNFET pipes T6
The caliber of CNFET pipes T9 is 1.487nm, and the caliber of the tenth CNFET pipes T10 is 1.488nm.
In the present embodiment, the first power supply Vdd is 0.9v, and second source Vdd1 is 0.45v.
As shown in Fig. 4 (a) and Fig. 4 (b), in the present embodiment, three input nand gates include the 12nd CNFET pipes T12, the tenth
Three CNFET pipes T13, the 14th CNFET pipes T14, the 15th CNFET pipes T15, the 16th CNFET pipes T16, the 17th CNFET pipes
T17 and the 18th CNFET pipes T18；12nd CNFET pipes T12, the 16th CNFET pipes T16 and the 17th CNFET pipes T17 are
P-type CNFET pipes, the 13rd CNFET pipes T13, the 14th CNFET pipes T14, the 15th CNFET pipes T15 and the 18th CNFET pipes
T18 is N-type CNFET pipes；The source electrode of 12nd CNFET pipes T12, the source electrode of the 16th CNFET pipes T16, the 17th CNFET pipes
The grid of the source electrode of T17 and the 18th CNFET pipes T18 access the first power supply Vdd, the drain electrode access of the 18th CNFET pipes T18
Second source Vdd1；The grid of 12nd CNFET pipes T12 and the grid of the 13rd CNFET pipes T13 connect and its connecting pin is three
The first input end of input nand gate, the drain electrode of the 12nd CNFET pipes T12, the drain electrode of the 13rd CNFET pipes T13, the 16th
The drain electrode of CNFET pipes T16, the drain electrode of the 17th CNFET pipes T17 is connected with the source electrode of the 18th CNFET pipes T18 and its connecting pin
Drain electrode for the output end of three input nand gates, the source electrode and the 14th CNFET pipes T14 of the 13rd CNFET pipes T13 connects, the
The drain electrode connection of the source electrode and the 15th CNFET pipes T15 of 14 CNFET pipes T14, the grid and the tenth of the 14th CNFET pipes T14
The second input terminal that the grid of six CNFET pipes T16 connects and its connecting pin is three input nand gates, the 15th CNFET pipes T15's
Source electrode ground connection, the grid of the 15th CNFET pipes T15 and the grid of the 17th CNFET pipes T17 connect and its connecting pin is three inputs
The third input terminal of NAND gate.
In the present embodiment, the caliber of the 12nd CNFET pipes T12, caliber, the 14th CNFET of the 13rd CNFET pipes T13
The caliber of pipe T14, the caliber of the 15th CNFET pipes T15, the caliber of the 16th CNFET pipes T16 and the 17th CNFET pipes T17
Caliber is 0.783nm, and the caliber of the 18th CNFET pipes T18 is 1.018nm.
As shown in Fig. 5 (a) and Fig. 5 (b), in the present embodiment, phase inverter includes the 19th CNFET pipes T19, the 20th
CNFET pipes T20 and the 21st CNFET pipe T21, the 19th CNFET pipes T19 is p-type CNFET pipes, the 20th CNFET pipes T20
It is N-type CNFET pipes with the 21st CNFET pipes T21；The source electrode and the 21st CNFET pipes T21 of 19th CNFET pipes T19
Grid access the first power supply Vdd, the 21st CNFET pipes T21 drain electrode access second source Vdd1, the 19th CNFET
The input terminal that the grid of the grid of pipe T19 and the 20th CNFET pipes T20 connect and its connecting pin is phase inverter, the 19th CNFET
The drain electrode of pipe T19, the drain electrode of the 20th CNFET pipes T20 is connected with the source electrode of the 21st CNFET pipes T21 and its connecting pin is
The output end of phase inverter, the source electrode ground connection of the 20th CNFET pipes T20.
In the present embodiment, the caliber of the 19th CNFET pipes T19 and the caliber of the 20th CNFET pipes T20 are 0.783nm,
The caliber of 21st CNFET pipes T21 is 1.018nm.
The three value 4-81 lines addresses of the present invention realized using CNFET are translated using Stanford University's 32nm master patterns library
Code device is emulated, and is verified its logic function and is analyzed power consumption and delay.Master pattern library considers CNT electricity under non-ideal condition
The influences of the factors to circuit such as lotus screen effect, ghost effect, the resistance of source/drain and grid and capacitance, therefore simulation result
It is accurate reliable.The major parameter of CNFET is as shown in table 1 in simulation process, the power supply Vdd=0.9V and Vddl=0.45V of use.
Table 1CNFET model major parameters
When enable signal EN be low level when, no matter input signal C3C2C1C0For which kind of state, output signal is all " 0 ",
The three value 4-81 line address decoders of the present invention realized using CNFET are in off working state；Enable signal EN high level has
Effect, when enable signal EN is high level, the three value 4-81 line address decoders of the invention realized using CNFET are in work
State；In the three value 4-81 line address decoders of the present invention realized using CNFET, L is exportediWherein i takes 0~80 integer；
It is assumed that output high level is Li, then have (C3C2C1C0)T to D=i, (C3C2C1C0)T to DIndicate that 4 ternary codes are converted to
Decimal code as a result, the present invention using CNFET realize three value 4-81 line address decoder logic functions it is correct.
Relationship between traditional address decoder and the input of three value address decoders and output port number is as shown in Figure 6.
Analysis chart 6 it is found that with input terminal quantity n variation, three value address decoder output ends be in 3nExponential increase；With input terminal
N increases, and three value address decoder decoding efficiencies are higher and higher, and decoding efficiency is traditional two-value decoder efficiency (1.5)nTimes.
The three value 4-81 line address decoders of the present invention realized using CNFET compare two-value address decoder, and identical bits input three values
Address decoder can control more sram cells.Therefore the decoding efficiency of the address decoder designed herein is high, while also subtracting
Few coding chip packaging pin number.
The three value 4-81 lines address decoders of the present invention realized using CNFET are translated with existing 6-64 lines two-value address
The power consumption of code device (conventional decoder and Block decoder) is compared, and two-value address decoder is compared, and of the invention utilizes CNFET
The power consumption for the three value 4-81 line address decoders realized at least reduces 37.1%.Therefore, three realized using CNFET of the invention
Value 4-81 line address decoder performances are greatly improved, so as to improve the performance of SRAM.
2 address decoder power consumption of table
SRAM is mainly made of SRAM array and its peripheral circuit, decoder and sense amplifier pair as peripheral circuit
The raising of SRAM performances plays a significantly greater role.During SRAM data read-write operation, address decoder delay accounts for total delay
More than half, therefore reduce address decoder power consumption can reduce SRAM power consumptions.It is differed in address decoder output end number
When little, table 3 is the utilization of existing 6-64 lines two-value address decoder (conventional decoder and Block decoder) and the present invention
The comparison for the three value 4-81 line address decoders delay that CNFET is realized.As can be drawn from Table 3, utilization CNFET of the invention is realized
Three value 4-81 line address decoders compared to existing two-value address decoder delay at least reduce 41.1%.The utilization of the present invention
The three value 4-81 line address decoders delay that CNFET is realized is reduced, so as to improve the performance of SRAM.
The comparison of 3 three value address decoder of table and the delay of two-value address decoder.
Claims (8)
1. a kind of three value 4-81 line address decoders realized using CNFET, it is characterised in that including ten three value 2-9 lines addresses
Decoder, the three value 2-9 line address decoders have Enable Pin, first input end, the second input terminal, the first output end,
Second output terminal, third output end, the 4th output end, the 5th output end, the 6th output end, the 7th output end, the 8th output end
With the 9th output end；Three value 2-9 line address decoders described in ten are respectively the one or three value 2-9 lines address decoder, second
Three value 2-9 lines address decoders, the three or three value 2-9 lines address decoder, the four or three value 2-9 lines address decoder, the five or three value
2-9 lines address decoder, the six or three value 2-9 lines address decoder, the seven or three value 2-9 lines address decoder, the eight or three value 2-9 lines
Address decoder, the 9th 3 value 2-9 lines address decoder and the 13rd value 2-9 line address decoders；One or the three value 2-9
First output end of line address decoder is connected with the Enable Pin of the two or the three value 2-9 line address decoders, and described
The second output terminal of one or three value 2-9 line address decoders is connected with the Enable Pin of the three or the three value 2-9 line address decoders,
One or the three third output end of value 2-9 line address decoders and making for the four or the three value 2-9 line address decoders
The connection of energy end, the 4th output end of the one or the three value 2-9 line address decoders and the five or the three value 2-9 lines address are translated
The Enable Pin connection of code device, the 5th output end and the six or the three value 2-9 of the one or the three value 2-9 line address decoders
The Enable Pin of line address decoder connects, the 6th output end of the one or the three value 2-9 line address decoders and described the
The Enable Pins of seven or three value 2-9 line address decoders connects, the 7th output end of the one or the three value 2-9 line address decoders and
The Enable Pin of eight or the three value 2-9 line address decoders connects, and the 8th of the one or the three value 2-9 line address decoders the
Output end is connected with the Enable Pin of the 9th 3 value 2-9 line address decoders, the one or the three value 2-9 line address decodings
9th output end of device is connected with the Enable Pin of the 13rd value 2-9 line address decoders, the two or the three value 2-9 lines
The first input end of address decoder, the first input end of the three or the three value 2-9 line address decoders, the described the 4th 3
The first input end, described of the first input end of value 2-9 line address decoders, the five or the three value 2-9 line address decoders
The first input ends of the six or three value 2-9 line address decoders, the seven or the three value 2-9 line address decoders the first input
End, the first input end of the eight or the three value 2-9 line address decoders, the 9th 3 value 2-9 line address decoders
First input end is connected with the first input end of the 13rd value 2-9 line address decoders and its connecting pin is described three
The first input end of value 4-81 line address decoders, it is the second input terminal of the two or the three value 2-9 line address decoders, described
The second input terminal of the three or three value 2-9 line address decoders, the four or the three value 2-9 line address decoders the second input
End, the second input terminal of the five or the three value 2-9 line address decoders, the six or the three value 2-9 line address decoders
Second input terminal, the second input terminal of the seven or the three value 2-9 line address decoders, the eight or the three value 2-9 lines address
Second input terminal of decoder, the second input terminal of the 9th 3 value 2-9 line address decoders and the 13rd value
It is second defeated that second input terminal of 2-9 line address decoders connects and its connecting pin is the three value 4-81 line address decoders
Enter end, the first input end of the one or the three value 2-9 line address decoders is the three value 4-81 line address decoders
Second input terminal of third input terminal, the one or the three value 2-9 line address decoders is that the three value 4-81 lines addresses are translated
The Enable Pin of 4th input terminal of code device, the one or the three value 2-9 line address decoders is the three value 4-81 lines addresses
The Enable Pin of decoder；
The three value 2-9 line address decoders include the identical three values 1-3 lines address decoder of two structures, nine structure phases
Same three input nand gates and the identical phase inverter of nine structures；The three value 1-3 line address decoders have input terminal, the
One output end, second output terminal and third output end, three input nand gates have first input end, the second input terminal,
Third input terminal and output end；The three value 1-3 line address decoders include the first CNFET pipes, the 2nd CNFET pipes, third
CNFET pipes, the 4th CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 7th CNFET pipes, the 8th CNFET pipes, the 9th CNFET
Pipe, the tenth CNFET pipes and the 11st CNFET pipes；The described 3rd CNFET pipes, the 4th CNFET pipes, the described the 7th
CNFET pipes, the 8th CNFET pipes and the tenth CNFET pipes are that p-type CNFET is managed, the first CNFET pipes,
2nd CNFET is managed, the 5th CNFET pipes, the 6th CNFET pipes, the 9th CNFET are managed and described
The 11st CNFET pipes be N-type CNFET pipe；The grid of the first CNFET pipes, the source of the 4th CNFET pipes
Pole, the source electrode of the 7th CNFET pipes, the source electrode of the source electrode of the 8th CNFET pipes and the tenth CNFET pipes are equal
The first power supply is accessed, the drain electrode of the first CNFET pipes accesses second source, and the voltage of the second source is described
The half of the voltage of first power supply；The grid of the 8th CNFET pipes, the grid of the 9th CNFET pipes, described
The grid of ten CNFET pipes is connected with the grid of the 11st CNFET pipes and its connecting pin is the three value 1-3 lines addresses
The input terminal of decoder；The grid of the 2nd CNFET pipes, the grid of the 3rd CNFET pipes, the described the 8th
The drain electrode of CNFET pipes and the drain electrode of the 9th CNFET pipes connect and its connecting pin is the three value 1-3 line address decodings
First output end of device；The source electrode of the 2nd CNFET pipes, the source electrode of the 5th CNFET pipes, the described the 6th
The source electrode of CNFET pipes, the 9th CNFET pipes source electrode and the 11st CNFET pipes source grounding；Described
The grid of 6th CNFET pipes, the 7th CNFET pipes grid, the tenth CNFET pipes drain electrode and the described the tenth
The drain electrodes of one CNFET pipes connects, the grid of the 4th CNFET pipes, the grid of the 5th CNFET pipes, described the
The drain electrode of six CNFET pipes and the drain electrode of the 7th CNFET pipes connect and its connecting pin is that the three value 1-3 lines addresses are translated
The third output end of code device；The source electrodes of the first CNFET pipes, the draining of the 2nd CNFET pipes, the third
The drain electrode of CNFET pipes and the drain electrode of the 5th CNFET pipes connect and its connecting pin is the three value 1-3 line address decodings
The second output terminal of device；The source electrode of the 3rd CNFET pipes is connected with the drain electrode of the 4th CNFET pipes；Described in two
Three value 1-3 line address decoders be respectively the one or three value 1-3 lines address decoder and the two or three value 1-3 line address decoders,
Three input nand gates described in nine be respectively the one or three input nand gate, the two or three input nand gate, the three or three input with it is non-
Door, the four or three input nand gate, the five or three input nand gate, the six or three input nand gate, the seven or three input nand gate, the eight or three
Input nand gate and the 9th 3 input nand gate, the phase inverter described in nine are respectively the first phase inverter, the second phase inverter, third
Phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter and the 9th phase inverter；Institute
The input terminal for the one or the three value 1-3 line address decoders stated is the first input end of the three value 2-9 line address decoders, institute
The input terminal for the two or the three value 1-3 line address decoders stated is the second input terminal of the three value 2-9 line address decoders, institute
First output end of the one or the three value 1-3 line address decoders stated is inputted with the second of the one or three input nand gate respectively
Second input terminal at end, the second input terminal of the two or three input nand gate and the three or three input nand gate connects
It connects；The second output terminal of one or the three value 1-3 line address decoders respectively with the four or three input nand gate
Second input of two input terminals, the second input terminal of the five or three input nand gate and the six or three input nand gate
End connection；The third output end of one or the three value 1-3 line address decoders respectively with the seven or three input nand gate
The second input terminal, the eight or three input nand gate the second input terminal and the 9th 3 input nand gate second
Input terminal connects；First output end of the two or the three value 1-3 line address decoders respectively with described one or three input with
The third input terminal of NOT gate, the third input terminal of the four or three input nand gate and the seven or three input nand gate
Third input terminal connects；The second output terminal of two or the three value 1-3 line address decoders is defeated with described the two or three respectively
Enter the third input terminal of NAND gate, the third input terminal of the five or three input nand gate and the described the 8th 3 input with it is non-
The third input terminal connection of door；The third output end of two or the three value 1-3 line address decoders respectively with the third
The third input terminal of three input nand gates, the third input terminal of the six or three input nand gate and the described the 9th 3 input
The third input terminal of NAND gate connects；The first input end of one or three input nand gate, the described the 2nd 3 input with
The first input end of NOT gate, the first input end of the three or three input nand gate, the four or three input nand gate
First input end, the first input end of the five or three input nand gate, the six or three input nand gate it is first defeated
Enter end, the first input end of the seven or three input nand gate, the eight or three input nand gate first input end and
The first input end of 9th 3 input nand gate connects and its connecting pin is the three value 2-9 line address decoders
Enable Pin；The output end of one or three input nand gate is connected with the input terminal of first phase inverter, and described
The output end of two or three input nand gates is connected with the input terminal of second phase inverter, the three or three input nand gate
Output end is connected with the input terminal of the third phase inverter, the output end of the four or three input nand gate and described
The input terminal of four phase inverters connects, the input terminal of the output end and the 5th phase inverter of the five or three input nand gate
Connection, the output end of the six or three input nand gate are connected with the input terminal of the hex inverter, and the described the 7th
The output end of three input nand gates is connected with the input terminal of the 7th phase inverter, the eight or three input nand gate it is defeated
Outlet is connected with the input terminal of the 8th phase inverter, the output end and the described the 9th of the 9th 3 input nand gate
The input terminal of phase inverter connects；The output end of first phase inverter is the first of the three value 2-9 line address decoders
Output end, the output end of second phase inverter is the second output terminal of the three value 2-9 line address decoders, described
The output end of third phase inverter is the third output end of the three value 2-9 line address decoders, the 4th phase inverter
Output end is the 4th output end of the three value 2-9 line address decoders, and the output end of the 5th phase inverter is described
Three value 2-9 line address decoders the 5th output end, the output end of the hex inverter is for the three value 2-9 lines
6th output end of location decoder, the output end of the 7th phase inverter are the of the three value 2-9 line address decoders
Seven output ends, the output end of the 8th phase inverter is the 8th output end of the three value 2-9 line address decoders, described
The 9th phase inverter output end be the three value 2-9 line address decoders the 9th output end.
2. a kind of 4-81 line address decoders realized using CNFET according to claim 1, it is characterised in that described
The threshold voltage of first CNFET pipes is 0.428v, the threshold voltage of the 2nd CNFET pipes and the 5th CNFET pipes
Threshold voltage be 0.557v, the threshold voltage of the threshold voltage and the 4th CNFET pipes of the 3rd CNFET pipes
It is -0.557v, the threshold voltage of the 6th CNFET pipes and the threshold voltage of the 9th CNFET pipes are
0.289v, the threshold voltage of the 7th CNFET pipes and the threshold voltage of the 8th CNFET pipes are -0.557v, institute
The threshold voltage for the tenth CNFET pipes stated is -0.289v, and the threshold voltage of the 11st CNFET pipes is 0.557v.
3. a kind of 4-81 line address decoders realized using CNFET according to claim 1, it is characterised in that described
The caliber of first CNFET pipes is 1.018nm, the caliber of the 2nd CNFET pipes, the caliber of the 3rd CNFET pipes, institute
The caliber, described of the caliber for the 4th CNFET pipes stated, the caliber of the 5th CNFET pipes, the 7th CNFET pipes
The caliber of the caliber of 8th CNFET pipes and the 11st CNFET pipes is 0.783nm, the pipe of the 6th CNFET pipes
The caliber of diameter and the 9th CNFET pipes is 1.487nm, and the caliber of the tenth CNFET pipes is 1.488nm.
4. a kind of three value 4-81 line address decoders realized using CNFET according to claim 1, it is characterised in that institute
The first power supply stated is 0.9v, and the second source is 0.45v.
5. a kind of three value 4-81 line address decoders realized using CNFET according to claim 1, it is characterised in that institute
Three input nand gates stated include the 12nd CNFET pipes, the 13rd CNFET pipes, the 14th CNFET is managed, the 15th CNFET is managed,
16th CNFET pipes, the 17th CNFET pipes and the 18th CNFET pipes；The described 12nd CNFET pipes, the described the 16th
CNFET is managed and the 17th CNFET pipes are p-type CNFET pipes, the 13rd CNFET pipes, the described the 14th
CNFET pipes, the 15th CNFET pipes and the 18th CNFET pipes are N-type CNFET pipes；Described the 12nd
The source electrode and the described the tenth of the source electrode of CNFET pipes, the source electrode of the 16th CNFET pipes, the 17th CNFET pipes
The grid of eight CNFET pipes accesses first power supply, and second that the drain electrode access of the 18th CNFET pipes is described is electric
Source；The grid of the 12nd CNFET pipes is connected with the grid of the 13rd CNFET pipes and its connecting pin is described
The first input end of three input nand gates, the draining of the 12nd CNFET pipes, the drain electrode of the 13rd CNFET pipes,
The draining of the 16th CNFET pipes, the source of the drain electrode and the 18th CNFET pipes of the 17th CNFET pipes
The output end that pole connects and its connecting pin is three input nand gates, the source electrode of the 13rd CNFET pipes and described
The 14th CNFET pipes drain electrode connection, the leakage of the source electrode and the 15th CNFET pipes of the 14th CNFET pipes
Pole connects, and the grid of the 14th CNFET pipes is connected with the grid of the 16th CNFET pipes and its connecting pin is institute
Second input terminal of three input nand gates stated, the source electrode ground connection of the 15th CNFET pipes, the 15th CNFET
The third that the grid of pipe is connected with the grid of the 17th CNFET pipes and its connecting pin is three input nand gates is defeated
Enter end.
6. a kind of three value 4-81 line address decoders realized using CNFET according to claim 5, it is characterised in that institute
The caliber for the 12nd CNFET pipes stated, the caliber of the 13rd CNFET pipes, the 14th CNFET pipes caliber,
The pipe of the caliber of the 15th CNFET pipes, the caliber and the 17th CNFET pipes of the 16th CNFET pipes
Diameter is 0.783nm, and the caliber of the 18th CNFET pipes is 1.018nm.
7. a kind of three value 4-81 line address decoders realized using CNFET according to claim 1, it is characterised in that institute
The phase inverter stated includes the 19th CNFET pipes, the 20th CNFET pipes and the 21st CNFET pipes, the 19th CNFET
Pipe is p-type CNFET pipes, and the 20th CNFET pipes and the 21st CNFET pipes are N-type CNFET pipes；It is described
The source electrode of the 19th CNFET pipes and the grid of the 21st CNFET pipes access first power supply, it is described
Second source described in the drain electrode access of 21st CNFET pipes, the grid and described second of the 19th CNFET pipes
The input terminal that the grid of ten CNFET pipes connects and its connecting pin is the phase inverter, the leakage of the 19th CNFET pipes
The drain electrode of pole, the 20th CNFET pipes is connected with the source electrode of the 21st CNFET pipes and its connecting pin is described
Phase inverter output end, the 20th CNFET pipes source electrode ground connection.
8. a kind of three value 4-81 line address decoders realized using CNFET according to claim 7, it is characterised in that institute
The caliber for the 19th CNFET pipes stated and the caliber of the 20th CNFET pipes are 0.783nm, and the described the 21st
The caliber of CNFET pipes is 1.018nm.
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| US5822231A (en) * | 1996-10-31 | 1998-10-13 | Samsung Electronics Co., Ltd. | Ternary based shifter that supports multiple data types for shift functions |
| JP4204153B2 (en) * | 1999-11-12 | 2009-01-07 | 新日本無線株式会社 | Encoding method in ternary arithmetic circuit, ternary encoded data addition method, ternary encoded data subtraction method, and ternary arithmetic circuit |
| CN103595399A (en) * | 2013-10-25 | 2014-02-19 | 宁波大学 | Three-valued NOR gate based on CNFETs |
| CN103618542A (en) * | 2013-10-25 | 2014-03-05 | 宁波大学 | A three-valued inverter based on CNFETs |
| CN103905032A (en) * | 2014-03-12 | 2014-07-02 | 宁波大学 | Carbon nanometer field effect transistor encoder |
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| US5822231A (en) * | 1996-10-31 | 1998-10-13 | Samsung Electronics Co., Ltd. | Ternary based shifter that supports multiple data types for shift functions |
| JP4204153B2 (en) * | 1999-11-12 | 2009-01-07 | 新日本無線株式会社 | Encoding method in ternary arithmetic circuit, ternary encoded data addition method, ternary encoded data subtraction method, and ternary arithmetic circuit |
| CN103595399A (en) * | 2013-10-25 | 2014-02-19 | 宁波大学 | Three-valued NOR gate based on CNFETs |
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