CN106847329A - The line address decoder of three value 4 81 that a kind of utilization CNFET is realized - Google Patents

The line address decoder of three value 4 81 that a kind of utilization CNFET is realized Download PDF

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Publication number
CN106847329A
CN106847329A CN201611252909.1A CN201611252909A CN106847329A CN 106847329 A CN106847329 A CN 106847329A CN 201611252909 A CN201611252909 A CN 201611252909A CN 106847329 A CN106847329 A CN 106847329A
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China
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value
input
cnfet pipes
line address
cnfet
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CN106847329B (en
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汪鹏君
龚道辉
陈伟伟
康耀鹏
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Ningbo University
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Ningbo University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses the line address decoder of three value 4 81 that a kind of utilization CNFET is realized, including ten line address decoders of three value 29, the line address decoder of three value 29 includes two line address decoders of three value of structure identical 13, nine input nand gates of structure identical three and nine structure identical phase inverters, the line address decoder of three value 13 is managed including a CNFET, 2nd CNFET is managed, 3rd CNFET is managed, 4th CNFET is managed, 5th CNFET is managed, 6th CNFET is managed, 7th CNFET is managed, 8th CNFET is managed, 9th CNFET is managed, tenth CNFET is managed and the 11st CNFET pipes；Advantage is relatively low power consumption, and time delay is smaller.

Description

The three value 4-81 line address decoders that a kind of utilization CNFET is realized
Technical field
The present invention relates to a kind of 4-81 lines address decoder, more particularly, to the three value 4-81 that a kind of utilization CNFET is realized Line address decoder.
Background technology
SRAM (Static Random Access Memory, SRAM) read or write speed is fast, conventional to deal with Interface circuit between device and internal memory, as the cache of processor.With super large-scale integration (Very Large Scale Integration, VLSI) development, processor clock frequency increases, SRAM read or write speeds are proposed it is higher will Ask.Address decoder as SRAM important part, its address decoder time delay account for SRAM read-write time delay it is very big by one Part, therefore the read or write speed and power consumption of SRAM have very big relation with the performance of address decoder.High performance address decoder Design to improve SRAM read or write speed reduction power consumption play a significantly greater role.
Traditional address decoder is designed using CMOS technology, and with feature size downsizing to nanometer scale, interconnection line is parasitic The problems such as gate delay, interconnection crosstalk that effect is brought, is increasingly severe, and the operating rate of address decoder runs into very big choosing War.And the CNT (Carbon Nanotube, CNT) of quasi- one-dimentional structure is because with ballistic transport characteristic, stable chemical nature The features such as convenient with grid voltage modulation, with the possibility for replacing CMOS technology.Carbon nanometer field can be obtained using CNTs as conducting channel Effect transistor (Carbon Nanotube Field Effect Transistor, CNFET).Document DENG J, WONG H S P.A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part I:Model of the Intrinsic Channel Region[J].IEEE Transactions on Electron Devices,2007,54(12):3186- 3194. researchs show that the interelectrode capacity of carbon nano field-effect transistor is only the 4% of MOSFET interelectrode capacities, therefore utilizes CNFET The address decoder of design has smaller time delay, can improve the operating rate of address decoder.In Binary Logic System, n is defeated Enter address decoder, 2 are can control in sramnThe read-write operation of individual sram cell.And in multi-value logic system, n inputs ground Location decoder can control more sram cells.Such as the three-valued logic of minimum basis, its logic value is " 0 ", " 1 " and " 2 "；Three values N input address decoder in sram, can control 3nThe read-write operation of individual SRAM, so as to the decoding that improve address decoder is imitated Rate.When the sram cell of same number is controlled, the number of pins of encapsulation can be reduced using three value address decoders.
In view of this, a kind of power consumption of design is relatively low, the three value 4-81 line address decoding utensils that the less utilization CNFET of time delay is realized It is significant.
The content of the invention
The technical problems to be solved by the invention are to provide that a kind of power consumption is relatively low, and the less utilization CNFET of time delay is realized Three value 4-81 line address decoders.
The present invention solve the technical scheme that is used of above-mentioned technical problem for：The three value 4-81 that a kind of utilization CNFET is realized Line address decoder, including ten three value 2-9 line address decoders, three described value 2-9 line address decoders have Enable Pin, First input end, the second input, the first output end, the second output end, the 3rd output end, the 4th output end, the 5th output end, 6th output end, the 7th output end, the 8th output end and the 9th output end；Three value 2-9 lines address decoders point described in ten Not Wei the one or three value 2-9 lines address decoder, the two or three value 2-9 lines address decoder, the three or three value 2-9 lines address decoder, Four or three value 2-9 lines address decoder, the five or three value 2-9 lines address decoder, the six or three value 2-9 lines address decoder, the 7th Three value 2-9 lines address decoders, the eight or three value 2-9 lines address decoder, the 9th 3 value 2-9 lines address decoder and the 13rd value 2-9 line address decoders；First output end and the two or three described value 2-9 of the one or three described value 2-9 line address decoders The Enable Pin connection of line address decoder, the second output end of described the one or three value 2-9 line address decoders and described the The Enable Pin connection of three or three value 2-9 line address decoders, the 3rd output end of described the one or three value 2-9 line address decoders with The Enable Pin connection of the four or three described value 2-9 line address decoders, the 4th of described the one or three value 2-9 line address decoders the The Enable Pin connection of output end and the five or three described value 2-9 line address decoders, the one or three described value 2-9 line address decodings The Enable Pin connection of the 5th output end of device and the six or three described value 2-9 line address decoders, the one or three described value 2-9 lines The Enable Pin connection of the 6th output end of address decoder and the seven or three described value 2-9 line address decoders, described first The Enable Pin connection of the 7th output end and the eight or three described value 2-9 line address decoders of three value 2-9 line address decoders, institute 8th output end and the enable of the 9th 3 described value 2-9 line address decoders of the one or the three value 2-9 line address decoders stated End connection, the 9th output end and the 13rd described value 2-9 line address decodings of described the one or three value 2-9 line address decoders The Enable Pin connection of device, first input end, the three or the three described value 2-9 lines of described the two or three value 2-9 line address decoders First input end, the described the 5th 3 of the first input end of address decoder, the four or three described value 2-9 line address decoders It is the first input end of value 2-9 line address decoders, the first input end of the six or three described value 2-9 line address decoders, described The first input end of the seven or three value 2-9 line address decoders, the first input of the eight or three described value 2-9 line address decoders End, the first input end of the 9th 3 described value 2-9 line address decoders and the 13rd described value 2-9 line address decoders First input end is connected and its connection end is the first input end of three described value 4-81 line address decoders, the described the 2nd 3 It is second input of value 2-9 line address decoders, the second input of the three or three described value 2-9 line address decoders, described The second input of the four or three value 2-9 line address decoders, the second input of the five or three described value 2-9 line address decoders End, the second input of described six or three value 2-9 line address decoders, the seven or three described value 2-9 line address decoders Second input, the second input of the eight or three described value 2-9 line address decoders, the 9th 3 described value 2-9 lines address Second input of the second input of decoder and the 13rd described value 2-9 line address decoders is connected and its connection end is Second input of three described value 4-81 line address decoders, the first of the one or three described value 2-9 line address decoders is defeated It is the 3rd input of three described value 4-81 line address decoders to enter end, described the one or three value 2-9 line address decoders Second input is the 4th input of three described value 4-81 line address decoders, and the one or three described value 2-9 lines address is translated The Enable Pin of code device is the Enable Pin of three described value 4-81 line address decoders；
Three described value 2-9 lines address decoders include two value 1-3 lines address decoders of structure identical three, nine knots The input nand gate of structure identical three and nine structure identical phase inverters；Three described value 1-3 lines address decoders have input End, the first output end, the second output end and the 3rd output end, three described input nand gates have first input end, second defeated Enter end, the 3rd input and output end；Three described value 1-3 lines address decoders are managed including a CNFET, the 2nd CNFET is managed, 3rd CNFET pipes, the 4th CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 7th CNFET pipes, the 8th CNFET pipes, the 9th CNFET pipes, the tenth CNFET pipes and the 11st CNFET pipes；The 3rd described CNFET is managed, the 4th described CNFET is managed, described 7th CNFET pipes, described the 8th CNFET pipes and the tenth described CNFET pipes are p-type CNFET pipes, described first CNFET pipes, described the 2nd CNFET pipes, described the 5th CNFET pipes, described the 6th CNFET pipes, the 9th described CNFET Pipe and the 11st described CNFET pipes are N-type CNFET pipes；The grid of a described CNFET pipes, the 4th described CNFET The source electrode of pipe, the source electrode of the 7th described CNFET pipes, the source electrode of the 8th described CNFET pipes and the tenth described CNFET pipes Source electrode accesses the first power supply, and the drain electrode of a described CNFET pipes accesses second source, and described second source is described The half of the first power supply；The grid of the 8th described CNFET pipes, grid, the described the tenth of the 9th described CNFET pipes The grid of the grid of CNFET pipes and the 11st described CNFET pipes is connected and its connection end is that three described value 1-3 lines addresses are translated The input of code device；The grid of the 2nd described CNFET pipes, the grid of the 3rd described CNFET pipes, the 8th described CNFET The drain electrode of pipe and the drain electrode of the 9th described CNFET pipes are connected and its connection end is three described value 1-3 line address decoders First output end；The source electrode of the 2nd described CNFET pipes, the source electrode of the 5th described CNFET pipes, described the 6th CNFET pipes Source electrode, the source electrode of the 9th described CNFET pipes and the 11st described CNFET pipes source grounding；Described the 6th The grid of CNFET pipes, the grid of the 7th described CNFET pipes, the drain electrode and the described the 11st of the tenth described CNFET pipes The drain electrode connection of CNFET pipes, grid, grid, the described the 6th of the 5th described CNFET pipes of described the 4th CNFET pipes The drain electrode of CNFET pipes and the drain electrode of the 7th described CNFET pipes are connected and its connection end is three described value 1-3 line address decodings 3rd output end of device；The source electrode of a described CNFET pipes, drain electrode, the described the 3rd of the 2nd described CNFET pipes The drain electrode of CNFET pipes and the drain electrode of the 5th described CNFET pipes are connected and its connection end is three described value 1-3 line address decodings Second output end of device；The drain electrode connection of the source electrode and the 4th described CNFET pipes of the 3rd described CNFET pipes；Described in two Three value 1-3 line address decoders be respectively the one or three value 1-3 lines address decoder and the two or three value 1-3 line address decoders, Three input nand gates described in nine be respectively the one or three input nand gate, the two or three input nand gate, the three or three input with it is non- Door, the four or three input nand gate, the five or three input nand gate, the six or three input nand gate, the seven or three input nand gate, the eight or three Input nand gate and the 9th 3 input nand gate, the phase inverter described in nine are respectively the first phase inverter, the second phase inverter, the 3rd Phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter and the 9th phase inverter；Institute The input of the one or the three value 1-3 line address decoders stated is the first input end of three described value 2-9 line address decoders, institute The input of the two or the three value 1-3 line address decoders stated is the second input of three described value 2-9 line address decoders, institute First output end of the one or the three value 1-3 line address decoders stated respectively with the second of the one or three described input nand gate the input Second input at end, the second input of the two or three described input nand gate and the three or three described input nand gate connects Connect；Second output end of the one or three described value 1-3 line address decoders is respectively with the of the four or three described input nand gate Second input of two inputs, the second input of the five or three described input nand gate and the six or three described input nand gate End connection；3rd output end of the one or three described value 1-3 line address decoders respectively with the seven or three described input nand gate The second input, the second of the second input of the eight or three described input nand gate and the 9th 3 described input nand gate Input is connected；First output end of the two or three described value 1-3 line address decoders respectively with described one or three input with 3rd input of not gate, the 3rd input of the four or three described input nand gate and the seven or three described input nand gate 3rd input is connected；Second output end of the two or three described value 1-3 line address decoders is defeated with the described 2nd 3 respectively Enter the 3rd input of NAND gate, the 3rd input of the five or three described input nand gate and the eight or three described input with it is non- The 3rd input connection of door；3rd output end of the two or three described value 1-3 line address decoders is respectively with the described the 3rd 3rd input of three input nand gates, the 3rd input of the six or three described input nand gate and the described the 9th 3 are input into The 3rd input connection of NAND gate；The first input end of the one or three described input nand gate, described two or three input with The first input end of not gate, the first input end of the three or three described input nand gate, the four or three described input nand gate First input end, the first input end of the five or three described input nand gate, the six or three described input nand gate it is first defeated Enter end, the first input end of described seven or three input nand gate, the first input end of the eight or three described input nand gate and The first input end of the 9th 3 described input nand gate is connected and its connection end is three described value 2-9 line address decoders Enable Pin；The input connection of the output end of the one or three described input nand gate and the first described phase inverter, described the The input connection of the output end of two or three input nand gates and the second described phase inverter, described the three or three input nand gate The input connection of output end and the 3rd described phase inverter, the output end of described the four or three input nand gate and described the The input connection of four phase inverters, the output end and the input of the 5th described phase inverter of described the five or three input nand gate Connection, the described output end of the six or three input nand gate and the input of described hex inverter is connected, and the described the 7th The input connection of the output end of three input nand gates and the 7th described phase inverter, described the eight or three input nand gate it is defeated The input for going out end and the 8th described phase inverter is connected, the output end and the described the 9th of described the 9th 3 input nand gate The input connection of phase inverter；The output end of the first described phase inverter is the first of three described value 2-9 line address decoders Output end, the output end of the second described phase inverter is the second output end of three described value 2-9 line address decoders, described The output end of the 3rd phase inverter is the 3rd output end of three described value 2-9 line address decoders, described the 4th phase inverter Output end is the 4th output end of three described value 2-9 line address decoders, and the output end of the 5th described phase inverter is described Three value 2-9 line address decoders the 5th output end, the output end of described hex inverter is described three value 2-9 lines 6th output end of location decoder, the output end of the 7th described phase inverter is the of three described value 2-9 line address decoders Seven output ends, the output end of the 8th described phase inverter is the 8th output end of three described value 2-9 line address decoders, described The 9th phase inverter output end be three described value 2-9 line address decoders the 9th output end.
The threshold voltage of a described CNFET pipes is 0.428v, the threshold voltage of described the 2nd described CNFET pipes 0.557v is with the threshold voltage of the 5th described CNFET pipes, the threshold voltage and described of described the 3rd CNFET pipes The threshold voltage of four CNFET pipes is -0.557v, the threshold voltage and described the 9th CNFET pipes of described the 6th CNFET pipes Threshold voltage be 0.289v, the threshold voltage and the threshold voltage of the 8th described CNFET pipes of described the 7th CNFET pipes - 0.557v is, the threshold voltage of the tenth described CNFET pipes is -0.289v, and the threshold value of the 11st described CNFET pipes is electric It is 0.557v to press.
The caliber of a described CNFET pipes is 1.018nm, caliber, the described the 3rd of described the 2nd CNFET pipes The caliber of CNFET pipes, the caliber of the 4th described CNFET pipes, the caliber of the 5th described CNFET pipes, the 7th described CNFET The caliber of the caliber of pipe, the caliber of the 8th described CNFET pipes and the 11st described CNFET pipes is 0.783nm, described The caliber of the caliber of the 6th CNFET pipes and the 9th described CNFET pipes is 1.487nm, the caliber of described the tenth CNFET pipes It is 1.488nm.The circuit can further reduce power consumption and time delay using lower supply voltage come drive circuit.
The first described power supply is 0.9v, and described second source is 0.45v.The circuit is using the first power supply and the second electricity Source obtains three value output response signals, improves the stability of circuit.
Three described input nand gates include the 12nd CNFET pipes, the 13rd CNFET pipes, the 14th CNFET pipes, the tenth Five CNFET pipes, the 16th CNFET pipes, the 17th CNFET pipes and the 18th CNFET pipes；It is described 12nd CNFET pipes, described The 16th CNFET pipes and the 17th described CNFET pipes be p-type CNFET pipes, it is described 13rd CNFET pipes, described 14th CNFET pipes, described the 15th CNFET pipes and the 18th described CNFET pipes are N-type CNFET pipes；Described The source electrode of 12 CNFET pipes, the source electrode of the 16th described CNFET pipes, the source electrode of the 17th described CNFET pipes and described The grid of the 18th CNFET pipes accesses the first described power supply, the drain electrode of the 18th described CNFET pipes access described in the Two power supplys；The grid connection of the grid of the 12nd described CNFET pipes and the 13rd described CNFET pipes and its connection end is institute The first input end of three input nand gates stated, the drain electrode of described the 12nd CNFET pipes, the 13rd described CNFET pipes Drain electrode, the drain electrode of the 16th described CNFET pipes, the drain electrode of the 17th described CNFET pipes and described the 18th CNFET pipes Source electrode connection and its connection end be three described input nand gates output end, the source electrode of described the 13rd CNFET pipes and The drain electrode connection of the 14th described CNFET pipes, the source electrode of described the 14th CNFET pipes and described the 15th CNFET pipes Drain electrode connection, the grid connection of the grid and the 16th described CNFET pipes of described the 14th CNFET pipes and its connection end It is the second input of three described input nand gates, the source ground of described the 15th CNFET pipes, the described the 15th The grid of the grid of CNFET pipes and the 17th described CNFET pipes is connected and its connection end is three described input nand gates 3rd input.The circuit can further reduce power consumption and time delay using lower supply voltage come drive circuit.
The caliber of the 12nd described CNFET pipes, the caliber of the 13rd described CNFET pipes, the 14th described CNFET The caliber of pipe, the caliber of the 15th described CNFET pipes, the caliber and the described the 17th of the 16th described CNFET pipes The caliber of CNFET pipes is 0.783nm, and the caliber of the 18th described CNFET pipes is 1.018nm.The circuit can be using more Low supply voltage carrys out drive circuit, further reduces power consumption and time delay.
Described phase inverter includes the 19th CNFET pipes, the 20th CNFET pipes and the 21st CNFET pipes, described the 19 CNFET pipes are managed for p-type CNFET, and described the 20th CNFET pipes and the 21st described CNFET pipes are N-type CNFET is managed；The grid of the source electrode of the 19th described CNFET pipes and the 21st described CNFET pipes accesses described the One power supply, the drain electrode of described the 21st CNFET pipes access described in second source, the grid of described the 19th CNFET pipes The grid of pole and the 20th described CNFET pipes is connected and its connection end is the input of described phase inverter, the described the tenth The drain electrode of nine CNFET pipes, the drain electrode of the 20th described CNFET pipes and the 21st described CNFET pipes source electrode connection and Its connection end is the output end of described phase inverter, the source ground of described the 20th CNFET pipes.The circuit utilizes CNFET The multi-Vt characteristic of pipe, grid voltage regulation is convenient, improves stability.
The caliber of the 19th described CNFET pipes and the caliber of the 20th described CNFET pipes are 0.783nm, described The 21st CNFET pipes caliber be 1.018nm.The circuit utilizes the multi-Vt characteristic of CNFET pipes, grid voltage to adjust just Victory, improves stability.
Compared with prior art, the advantage of the invention is that realizing three value 4- by ten three value 2-9 line address decoders 81 line address decoders, three value 2-9 lines address decoders include two value 1-3 lines address decoders of structure identical three, nine The input nand gate of structure identical three and nine structure identical phase inverters, three value 1-3 lines address decoders include a CNFET Pipe, the 2nd CNFET pipes, the 3rd CNFET pipes, the 4th CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 7th CNFET pipes, the Eight CNFET pipes, the 9th CNFET pipes, the tenth CNFET pipes and the 11st CNFET pipes；With existing two-value 6-64 line address decoders Compare, the three value 4-81 line address decoders that utilization CNFET of the invention is realized can control more sram cells, decoding efficiency Height, while also reducing coding chip packaging pin number, power consumption at least reduces 37.1%, at least reduces 41.1%, and power consumption is relatively low, Time delay is smaller.
Brief description of the drawings
Fig. 1 is the structure chart of the three value 4-81 line address decoders that utilization CNFET of the invention is realized；
Fig. 2 is three value 2-9 line address decoders in the three value 4-81 line address decoders that utilization CNFET of the invention is realized Structure chart；
Fig. 3 is the circuit diagram of three values 1-3 line address decoders of the invention；
Fig. 4 (a) is the electricity of three input nand gates of the three value 4-81 line address decoders that utilization CNFET of the invention is realized Lu Tu；
Fig. 4 (b) is the symbol of three input nand gates of the three value 4-81 line address decoders that utilization CNFET of the invention is realized Number figure；
Fig. 5 (a) is the circuit diagram of the phase inverter of the three value 4-81 line address decoders that utilization CNFET of the invention is realized；
Fig. 5 (b) is the graphical diagram of the phase inverter of the three value 4-81 line address decoders that utilization CNFET of the invention is realized；
Fig. 6 is address decoder input and output port number purpose relation curve.
Specific embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment one：As shown in Figure 1, Figure 2 and Figure 3, the three value 4-81 line address decoders that a kind of utilization CNFET is realized, Including ten three value 2-9 line address decoders, three value 2-9 line address decoders have Enable Pin, first input end, the second input End, the first output end, the second output end, the 3rd output end, the 4th output end, the 5th output end, the 6th output end, the 7th output End, the 8th output end and the 9th output end；Ten three value 2-9 line address decoders are respectively the one or three value 2-9 line address decodings Device A1, the two or three value 2-9 line address decoders A2, the three or three value 2-9 line address decoders A3, the four or three value 2-9 lines address are translated Code device A4, the five or three value 2-9 line address decoders A5, the six or three value 2-9 line address decoders A6, the seven or three value 2-9 lines address Decoder A7, the eight or three value 2-9 line address decoders A8, the 9th 3 value 2-9 line address decoder A9 and the 13rd value 2-9 lines ground Location decoder A10；First output end and the two or three value 2-9 line address decoders A2 of the one or three value 2-9 line address decoders A1 Enable Pin connection, second output end and the three or three value 2-9 line address decoders A3 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 3rd output end and the four or three value 2-9 line address decoders A4 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 4th output end and the five or three value 2-9 line address decoders A5 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 5th output end and the six or three value 2-9 line address decoders A6 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 6th output end and the seven or three value 2-9 line address decoders A7 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 7th output end and the eight or three value 2-9 line address decoders A8 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 8th output end and the 9th 3 value 2-9 line address decoders A9 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 9th output end and the 13rd value 2-9 line address decoders of the one or three value 2-9 line address decoders A1 The Enable Pin connection of A10, first input end, the three or the three value 2-9 line address decoders of the two or three value 2-9 line address decoders A2 First input end, the five or the three value 2-9 line address decoders of the first input end of A3, the four or three value 2-9 line address decoders A4 First input end, the seven or the three value 2-9 line address decoders of the first input end of A5, the six or three value 2-9 line address decoders A6 First input end, the 9th 3 value 2-9 line address decoders of the first input end of A7, the eight or three value 2-9 line address decoders A8 The first input end of the first input end of A9 and the 13rd value 2-9 line address decoders A10 is connected and its connection end is three value 4- The first input end of 81 line address decoders, the second input, the three or the three value 2-9 of the two or three value 2-9 line address decoders A2 Second input, the five or the three value 2-9 of second input of line address decoder A3, the four or three value 2-9 line address decoders A4 Second input, the seven or the three value 2-9 of second input of line address decoder A5, the six or three value 2-9 line address decoders A6 Second input, the 9th 3 value 2-9 of second input of line address decoder A7, the eight or three value 2-9 line address decoders A8 The second input connection of second input of line address decoder A9 and the 13rd value 2-9 line address decoders A10 and its company It is the second input of three value 4-81 line address decoders, the first input end of the one or three value 2-9 line address decoders A1 to connect end It is the 3rd input of three value 4-81 line address decoders, second input of the one or three value 2-9 line address decoders A1 is three 4th input of value 4-81 line address decoders, the Enable Pin of the one or three value 2-9 line address decoders A1 is three value 4-81 lines The Enable Pin of address decoder；Three value 2-9 lines address decoders include two value 1-3 lines address decoders of structure identical three, Nine input nand gates of structure identical three and nine structure identical phase inverters；Three value 1-3 lines address decoders have input End, the first output end, the second output end and the 3rd output end, three input nand gates have first input end, the second input, Three inputs and output end；Three value 1-3 lines address decoders include a CNFET pipes T1, the 2nd CNFET pipes T2, the 3rd CNFET Pipe T3, the 4th CNFET pipes T4, the 5th CNFET pipes T5, the 6th CNFET pipes T6, the 7th CNFET pipes T7, the 8th CNFET pipes T8, Nine CNFET pipes T9, the tenth CNFET pipes T10 and the 11st CNFET pipes T11；3rd CNFET pipes T3, the 4th CNFET pipes T4, the 7th CNFET pipes T7, the 8th CNFET pipes T8 and the tenth CNFET pipes T10 are p-type CNFET pipes, a CNFET pipes T1, the 2nd CNFET Pipe T2, the 5th CNFET pipes T5, the 6th CNFET pipes T6, the 9th CNFET pipes T9 and the 11st CNFET pipes T11 are N-type CNFET Pipe；The grid of the first CNFET pipes T1, the source electrode of the 4th CNFET pipes T4, the source electrode of the 7th CNFET pipes T7, the 8th CNFET pipes T8 Source electrode and the source electrode of the tenth CNFET pipes T10 access the first power supply Vdd, the drain electrode of a CNFET pipes T1 accesses second source Vdd1, second source Vdd1 are the half of the first power supply Vdd；The grid of the 8th CNFET pipes T8, the grid of the 9th CNFET pipes T9, The grid of the tenth CNFET pipes T10 and the grid of the 11st CNFET pipes T11 are connected and its connection end is three value 1-3 line address decodings The input of device；The grid of the 2nd CNFET pipes T2, the grid of the 3rd CNFET pipes T3, the drain electrode and the 9th of the 8th CNFET pipes T8 The drain electrode of CNFET pipes T9 is connected and its connection end is the first output end of three value 1-3 line address decoders；2nd CNFET pipes T2 Source electrode, the source electrode of the 5th CNFET pipes T5, the source electrode of the 6th CNFET pipes T6, the source electrode and the 11st of the 9th CNFET pipes T9 The source grounding of CNFET pipes T11；The grid of the 6th CNFET pipes T6, the grid of the 7th CNFET pipes T7, the tenth CNFET pipes T10 Drain electrode and the drain electrode of the 11st CNFET pipes T11 connect, the grid of the 4th CNFET pipes T4, the grid of the 5th CNFET pipes T5, the The drain electrode of six CNFET pipes T6 and the drain electrode connection of the 7th CNFET pipes T7 and its connection end is the of three value 1-3 line address decoders Three output ends；The source electrode of the first CNFET pipes T1, the drain electrode of the 2nd CNFET pipes T2, the drain electrode and the 5th of the 3rd CNFET pipes T3 The drain electrode of CNFET pipes T5 is connected and its connection end is the second output end of three value 1-3 line address decoders；3rd CNFET pipes T3 Source electrode and the 4th CNFET pipes T4 drain electrode connection；Two three value 1-3 line address decoders are respectively the one or three value 1-3 lines ground Location decoder U1 and the two or three value 1-3 lines address decoder U2, nine three input nand gates are respectively the one or three input nand gate G1, the two or three input nand gate G2, the three or three input nand gate G3, the four or three input nand gate G4, the five or three input nand gate G5, the six or three input nand gate G6, the seven or three input nand gate G7, the eight or three input nand gate G8 and the 9th 3 input nand gate G9, nine phase inverters are respectively the first phase inverter F1, the second phase inverter F2, the 3rd phase inverter F3, the 4th phase inverter F4, the 5th anti- Phase device F5, hex inverter F6, the 7th phase inverter F7, the 8th phase inverter F8 and the 9th phase inverter F9；One or three value 1-3 lines address The input of decoder U1 is the first input end of three value 2-9 line address decoders, the two or three value 1-3 line address decoders U2's Input is the second input of three value 2-9 line address decoders, first output end of the one or three value 1-3 line address decoders U1 The second input respectively with the one or three input nand gate G1, second input of the two or three input nand gate G2 and the three or three are defeated Enter the second input connection of NAND gate G3；Second output end of the one or three value 1-3 line address decoders U1 is respectively with the four or three Second input of input nand gate G4, second input of the five or three input nand gate G5 and the six or three input nand gate G6's Second input is connected；3rd output end of the one or three value 1-3 line address decoders U1 respectively with the seven or three input nand gate G7 The second input, second input of the eight or three input nand gate G8 and the 9th 3 input nand gate G9 the second input connect Connect；First output end of the two or three value 1-3 line address decoders U2 the 3rd input respectively with the one or three input nand gate G1, The 3rd input connection of the 3rd input and the seven or three input nand gate G7 of the four or three input nand gate G4；Two or three value 1- Second output end of 3 line address decoder U2 the 3rd input respectively with the two or three input nand gate G2, the five or three input with The 3rd input connection of the 3rd input and the eight or three input nand gate G8 of not gate G5；Two or three value 1-3 line address decodings 3rd output end of device U2 the 3rd input, the 3rd of the six or three input nand gate G6 the respectively with the three or three input nand gate G3 The 3rd input connection of input and the 9th 3 input nand gate G9；The first input end of the one or three input nand gate G1, The first input end of two or three input nand gate G2, the first input end of the three or three input nand gate G3, the four or three input nand gate The first input end of G4, the first input end of the five or three input nand gate G5, the first input end of the six or three input nand gate G6, The first input end of the seven or three input nand gate G7, the first input end of the eight or three input nand gate G8 and the 9th 3 input with it is non- The first input end of door G9 is connected and its connection end is the Enable Pin of three value 2-9 line address decoders；One or three input nand gate The input connection of the output end of G1 and the first phase inverter F1, the output end of the two or three input nand gate G2 and the second phase inverter F2 Input connection, the input connection of the output end of the three or three input nand gate G3 and the 3rd phase inverter F3, the four or three input The input connection of the output end of NAND gate G4 and the 4th phase inverter F4, the output end of the five or three input nand gate G5 and the 5th anti- The input connection of phase device F5, the input connection of the output end and hex inverter F6 of the six or three input nand gate G6, the 7th The input connection of the output end of three input nand gate G7 and the 7th phase inverter F7, the output end of the eight or three input nand gate G8 and The input connection of the 8th phase inverter F8, the output end of the 9th 3 input nand gate G9 and the input of the 9th phase inverter F9 connect Connect；The output end of the first phase inverter F1 is the first output end of three value 2-9 line address decoders, the output end of the second phase inverter F2 It is the second output end of three value 2-9 line address decoders, the output end of the 3rd phase inverter F3 is three value 2-9 line address decoders 3rd output end, the output end of the 4th phase inverter F4 is the 4th output end of three value 2-9 line address decoders, the 5th phase inverter F5 Output end be three value 2-9 line address decoders the 5th output end, the output end of hex inverter F6 is three value 2-9 lines addresses 6th output end of decoder, the output end of the 7th phase inverter F7 is the 7th output end of three value 2-9 line address decoders, the 8th The output end of phase inverter F8 is the 8th output end of three value 2-9 line address decoders, and the output end of the 9th phase inverter F9 is three values 9th output end of 2-9 line address decoders.
Embodiment two：As shown in Figure 1, Figure 2 and Figure 3, the three value 4-81 line address decoders that a kind of utilization CNFET is realized, Including ten three value 2-9 line address decoders, three value 2-9 line address decoders have Enable Pin, first input end, the second input End, the first output end, the second output end, the 3rd output end, the 4th output end, the 5th output end, the 6th output end, the 7th output End, the 8th output end and the 9th output end；Ten three value 2-9 line address decoders are respectively the one or three value 2-9 line address decodings Device A1, the two or three value 2-9 line address decoders A2, the three or three value 2-9 line address decoders A3, the four or three value 2-9 lines address are translated Code device A4, the five or three value 2-9 line address decoders A5, the six or three value 2-9 line address decoders A6, the seven or three value 2-9 lines address Decoder A7, the eight or three value 2-9 line address decoders A8, the 9th 3 value 2-9 line address decoder A9 and the 13rd value 2-9 lines ground Location decoder A10；First output end and the two or three value 2-9 line address decoders A2 of the one or three value 2-9 line address decoders A1 Enable Pin connection, second output end and the three or three value 2-9 line address decoders A3 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 3rd output end and the four or three value 2-9 line address decoders A4 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 4th output end and the five or three value 2-9 line address decoders A5 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 5th output end and the six or three value 2-9 line address decoders A6 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 6th output end and the seven or three value 2-9 line address decoders A7 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 7th output end and the eight or three value 2-9 line address decoders A8 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 8th output end and the 9th 3 value 2-9 line address decoders A9 of the one or three value 2-9 line address decoders A1 Enable Pin connection, the 9th output end and the 13rd value 2-9 line address decoders of the one or three value 2-9 line address decoders A1 The Enable Pin connection of A10, first input end, the three or the three value 2-9 line address decoders of the two or three value 2-9 line address decoders A2 First input end, the five or the three value 2-9 line address decoders of the first input end of A3, the four or three value 2-9 line address decoders A4 First input end, the seven or the three value 2-9 line address decoders of the first input end of A5, the six or three value 2-9 line address decoders A6 First input end, the 9th 3 value 2-9 line address decoders of the first input end of A7, the eight or three value 2-9 line address decoders A8 The first input end of the first input end of A9 and the 13rd value 2-9 line address decoders A10 is connected and its connection end is three value 4- The first input end of 81 line address decoders, the second input, the three or the three value 2-9 of the two or three value 2-9 line address decoders A2 Second input, the five or the three value 2-9 of second input of line address decoder A3, the four or three value 2-9 line address decoders A4 Second input, the seven or the three value 2-9 of second input of line address decoder A5, the six or three value 2-9 line address decoders A6 Second input, the 9th 3 value 2-9 of second input of line address decoder A7, the eight or three value 2-9 line address decoders A8 The second input connection of second input of line address decoder A9 and the 13rd value 2-9 line address decoders A10 and its company It is the second input of three value 4-81 line address decoders, the first input end of the one or three value 2-9 line address decoders A1 to connect end It is the 3rd input of three value 4-81 line address decoders, second input of the one or three value 2-9 line address decoders A1 is three 4th input of value 4-81 line address decoders, the Enable Pin of the one or three value 2-9 line address decoders A1 is three value 4-81 lines The Enable Pin of address decoder；Three value 2-9 lines address decoders include two value 1-3 lines address decoders of structure identical three, Nine input nand gates of structure identical three and nine structure identical phase inverters；Three value 1-3 lines address decoders have input End, the first output end, the second output end and the 3rd output end, three input nand gates have first input end, the second input, Three inputs and output end；Three value 1-3 lines address decoders include a CNFET pipes T1, the 2nd CNFET pipes T2, the 3rd CNFET Pipe T3, the 4th CNFET pipes T4, the 5th CNFET pipes T5, the 6th CNFET pipes T6, the 7th CNFET pipes T7, the 8th CNFET pipes T8, Nine CNFET pipes T9, the tenth CNFET pipes T10 and the 11st CNFET pipes T11；3rd CNFET pipes T3, the 4th CNFET pipes T4, the 7th CNFET pipes T7, the 8th CNFET pipes T8 and the tenth CNFET pipes T10 are p-type CNFET pipes, a CNFET pipes T1, the 2nd CNFET Pipe T2, the 5th CNFET pipes T5, the 6th CNFET pipes T6, the 9th CNFET pipes T9 and the 11st CNFET pipes T11 are N-type CNFET Pipe；The grid of the first CNFET pipes T1, the source electrode of the 4th CNFET pipes T4, the source electrode of the 7th CNFET pipes T7, the 8th CNFET pipes T8 Source electrode and the source electrode of the tenth CNFET pipes T10 access the first power supply Vdd, the drain electrode of a CNFET pipes T1 accesses second source Vdd1, second source Vdd1 are the half of the first power supply Vdd；The grid of the 8th CNFET pipes T8, the grid of the 9th CNFET pipes T9, The grid of the tenth CNFET pipes T10 and the grid of the 11st CNFET pipes T11 are connected and its connection end is three value 1-3 line address decodings The input of device；The grid of the 2nd CNFET pipes T2, the grid of the 3rd CNFET pipes T3, the drain electrode and the 9th of the 8th CNFET pipes T8 The drain electrode of CNFET pipes T9 is connected and its connection end is the first output end of three value 1-3 line address decoders；2nd CNFET pipes T2 Source electrode, the source electrode of the 5th CNFET pipes T5, the source electrode of the 6th CNFET pipes T6, the source electrode and the 11st of the 9th CNFET pipes T9 The source grounding of CNFET pipes T11；The grid of the 6th CNFET pipes T6, the grid of the 7th CNFET pipes T7, the tenth CNFET pipes T10 Drain electrode and the drain electrode of the 11st CNFET pipes T11 connect, the grid of the 4th CNFET pipes T4, the grid of the 5th CNFET pipes T5, the The drain electrode of six CNFET pipes T6 and the drain electrode connection of the 7th CNFET pipes T7 and its connection end is the of three value 1-3 line address decoders Three output ends；The source electrode of the first CNFET pipes T1, the drain electrode of the 2nd CNFET pipes T2, the drain electrode and the 5th of the 3rd CNFET pipes T3 The drain electrode of CNFET pipes T5 is connected and its connection end is the second output end of three value 1-3 line address decoders；3rd CNFET pipes T3 Source electrode and the 4th CNFET pipes T4 drain electrode connection；Two three value 1-3 line address decoders are respectively the one or three value 1-3 lines ground Location decoder U1 and the two or three value 1-3 lines address decoder U2, nine three input nand gates are respectively the one or three input nand gate G1, the two or three input nand gate G2, the three or three input nand gate G3, the four or three input nand gate G4, the five or three input nand gate G5, the six or three input nand gate G6, the seven or three input nand gate G7, the eight or three input nand gate G8 and the 9th 3 input nand gate G9, nine phase inverters are respectively the first phase inverter F1, the second phase inverter F2, the 3rd phase inverter F3, the 4th phase inverter F4, the 5th anti- Phase device F5, hex inverter F6, the 7th phase inverter F7, the 8th phase inverter F8 and the 9th phase inverter F9；One or three value 1-3 lines address The input of decoder U1 is the first input end of three value 2-9 line address decoders, the two or three value 1-3 line address decoders U2's Input is the second input of three value 2-9 line address decoders, first output end of the one or three value 1-3 line address decoders U1 The second input respectively with the one or three input nand gate G1, second input of the two or three input nand gate G2 and the three or three are defeated Enter the second input connection of NAND gate G3；Second output end of the one or three value 1-3 line address decoders U1 is respectively with the four or three Second input of input nand gate G4, second input of the five or three input nand gate G5 and the six or three input nand gate G6's Second input is connected；3rd output end of the one or three value 1-3 line address decoders U1 respectively with the seven or three input nand gate G7 The second input, second input of the eight or three input nand gate G8 and the 9th 3 input nand gate G9 the second input connect Connect；First output end of the two or three value 1-3 line address decoders U2 the 3rd input respectively with the one or three input nand gate G1, The 3rd input connection of the 3rd input and the seven or three input nand gate G7 of the four or three input nand gate G4；Two or three value 1- Second output end of 3 line address decoder U2 the 3rd input respectively with the two or three input nand gate G2, the five or three input with The 3rd input connection of the 3rd input and the eight or three input nand gate G8 of not gate G5；Two or three value 1-3 line address decodings 3rd output end of device U2 the 3rd input, the 3rd of the six or three input nand gate G6 the respectively with the three or three input nand gate G3 The 3rd input connection of input and the 9th 3 input nand gate G9；The first input end of the one or three input nand gate G1, The first input end of two or three input nand gate G2, the first input end of the three or three input nand gate G3, the four or three input nand gate The first input end of G4, the first input end of the five or three input nand gate G5, the first input end of the six or three input nand gate G6, The first input end of the seven or three input nand gate G7, the first input end of the eight or three input nand gate G8 and the 9th 3 input with it is non- The first input end of door G9 is connected and its connection end is the Enable Pin of three value 2-9 line address decoders；One or three input nand gate The input connection of the output end of G1 and the first phase inverter F1, the output end of the two or three input nand gate G2 and the second phase inverter F2 Input connection, the input connection of the output end of the three or three input nand gate G3 and the 3rd phase inverter F3, the four or three input The input connection of the output end of NAND gate G4 and the 4th phase inverter F4, the output end of the five or three input nand gate G5 and the 5th anti- The input connection of phase device F5, the input connection of the output end and hex inverter F6 of the six or three input nand gate G6, the 7th The input connection of the output end of three input nand gate G7 and the 7th phase inverter F7, the output end of the eight or three input nand gate G8 and The input connection of the 8th phase inverter F8, the output end of the 9th 3 input nand gate G9 and the input of the 9th phase inverter F9 connect Connect；The output end of the first phase inverter F1 is the first output end of three value 2-9 line address decoders, the output end of the second phase inverter F2 It is the second output end of three value 2-9 line address decoders, the output end of the 3rd phase inverter F3 is three value 2-9 line address decoders 3rd output end, the output end of the 4th phase inverter F4 is the 4th output end of three value 2-9 line address decoders, the 5th phase inverter F5 Output end be three value 2-9 line address decoders the 5th output end, the output end of hex inverter F6 is three value 2-9 lines addresses 6th output end of decoder, the output end of the 7th phase inverter F7 is the 7th output end of three value 2-9 line address decoders, the 8th The output end of phase inverter F8 is the 8th output end of three value 2-9 line address decoders, and the output end of the 9th phase inverter F9 is three values 9th output end of 2-9 line address decoders.
In the present embodiment, the threshold voltage of a CNFET pipes T1 is 0.428v, the threshold voltage of the 2nd CNFET pipes T2 and The threshold voltage of the 5th CNFET pipes T5 is 0.557v, the threshold voltage of the 3rd CNFET pipes T3 and the threshold of the 4th CNFET pipes T4 Threshold voltage is -0.557v, and the threshold voltage of the 6th CNFET pipes T6 and the threshold voltage of the 9th CNFET pipes T9 are 0.289v, The threshold voltage of the 7th CNFET pipes T7 and the threshold voltage of the 8th CNFET pipes T8 are -0.557v, the tenth CNFET pipes T10's Threshold voltage is -0.289v, and the threshold voltage of the 11st CNFET pipes T11 is 0.557v.
In the present embodiment, the caliber of a CNFET pipes T1 is 1.018nm, caliber, the 3rd CNFET of the 2nd CNFET pipes T2 The caliber of pipe T3, the caliber of the 4th CNFET pipes T4, the caliber of the 5th CNFET pipes T5, caliber, the 8th of the 7th CNFET pipes T7 The caliber of the caliber of CNFET pipes T8 and the 11st CNFET pipes T11 is 0.783nm, the caliber and the 9th of the 6th CNFET pipes T6 The caliber of CNFET pipes T9 is 1.487nm, and the caliber of the tenth CNFET pipes T10 is 1.488nm.
In the present embodiment, the first power supply Vdd is 0.9v, and second source Vdd1 is 0.45v.
As shown in Fig. 4 (a) and Fig. 4 (b), in the present embodiment, three input nand gates include the 12nd CNFET pipes T12, the tenth Three CNFET pipes T13, the 14th CNFET pipes T14, the 15th CNFET pipes T15, the 16th CNFET pipes T16, the 17th CNFET pipes T17 and the 18th CNFET pipes T18；12nd CNFET pipes T12, the 16th CNFET pipes T16 and the 17th CNFET pipes T17 are P-type CNFET is managed, the 13rd CNFET pipes T13, the 14th CNFET pipes T14, the 15th CNFET pipes T15 and the 18th CNFET pipe T18 is N-type CNFET pipes；The source electrode of the 12nd CNFET pipes T12, the source electrode of the 16th CNFET pipes T16, the 17th CNFET pipes The grid of the source electrode of T17 and the 18th CNFET pipes T18 accesses the first power supply Vdd, and the drain electrode of the 18th CNFET pipes T18 is accessed Second source Vdd1；The grid of the 12nd CNFET pipes T12 and the grid of the 13rd CNFET pipes T13 are connected and its connection end is three The first input end of input nand gate, the drain electrode of the 12nd CNFET pipes T12, drain electrode, the 16th of the 13rd CNFET pipes T13 The source electrode connection of the drain electrode of CNFET pipes T16, the drain electrode of the 17th CNFET pipes T17 and the 18th CNFET pipes T18 and its connection end It is the output end of three input nand gates, the drain electrode of the source electrode and the 14th CNFET pipes T14 of the 13rd CNFET pipes T13 is connected, the The drain electrode connection of the source electrode and the 15th CNFET pipes T15 of 14 CNFET pipes T14, the grid and the tenth of the 14th CNFET pipes T14 The grid of six CNFET pipes T16 is connected and its connection end is the second input of three input nand gates, the 15th CNFET pipes T15's Source ground, the grid of the 15th CNFET pipes T15 and the grid of the 17th CNFET pipes T17 are connected and its connection end is three inputs 3rd input of NAND gate.
In the present embodiment, the caliber of the 12nd CNFET pipes T12, caliber, the 14th CNFET of the 13rd CNFET pipes T13 The caliber of pipe T14, the caliber of the 15th CNFET pipes T15, the caliber of the 16th CNFET pipes T16 and the 17th CNFET pipes T17's Caliber is 0.783nm, and the caliber of the 18th CNFET pipes T18 is 1.018nm.
As shown in Fig. 5 (a) and Fig. 5 (b), in the present embodiment, phase inverter includes the 19th CNFET pipes T19, the 20th CNFET pipes T20 and the 21st CNFET pipe T21, the 19th CNFET pipes T19 is managed for p-type CNFET, the 20th CNFET pipes T20 N-type CNFET is with the 21st CNFET pipes T21 to manage；The source electrode and the 21st CNFET pipes T21 of the 19th CNFET pipes T19 Grid access the first power supply Vdd, the 21st CNFET pipes T21 drain electrode access second source Vdd1, the 19th CNFET The grid of the grid of pipe T19 and the 20th CNFET pipes T20 is connected and its connection end is the input of phase inverter, the 19th CNFET The source electrode of the drain electrode of pipe T19, the drain electrode of the 20th CNFET pipes T20 and the 21st CNFET pipes T21 is connected and its connection end is The output end of phase inverter, the source ground of the 20th CNFET pipes T20.
In the present embodiment, the caliber of the 19th CNFET pipes T19 and the caliber of the 20th CNFET pipes T20 are 0.783nm, The caliber of the 21st CNFET pipes T21 is 1.018nm.
Translate the three value 4-81 lines addresses realized to utilization CNFET of the invention using Stanford University's 32nm master patterns storehouse Code device is emulated, and is verified its logic function and is analyzed power consumption and time delay.Master pattern storehouse considers CNT electricity under non-ideal condition Influence of the factors such as the resistance and electric capacity of lotus screen effect, ghost effect, source/drain and grid to circuit, therefore simulation result It is accurate reliable.The major parameter of CNFET is as shown in table 1 in simulation process, the power supply Vdd=0.9V and Vddl=0.45V of use.
Table 6CNFET model major parameters
When it is low level to enable signal EN, no matter input signal C3C2C1C0It is which kind of state, output signal is all " 0 ", The three value 4-81 lines address decoders that utilization CNFET of the invention is realized are in off working state；Enabling signal EN high level has Effect, when it is high level to enable signal EN, the three value 4-81 lines address decoders that utilization CNFET of the invention is realized are in work State；In the three value 4-81 line address decoders that utilization CNFET of the invention is realized, L is exportediWherein i takes 0~80 integer； It is assumed that output high level is Li, then have (C3C2C1C0)T to D=i, (C3C2C1C0)T toDRepresent that 4 ternary codes are converted to ten The result of ary codes, the three value 4-81 line address decoder logic functions that utilization CNFET of the invention is realized are correct.
Relation between traditional address decoder and three value address decoder inputs and output port number is as shown in Figure 6. Analysis chart 6 understands, with the change of input quantity n, three value address decoder output ends are in 3nExponential increase；With input N increases, three value address decoder decoding efficiency more and more highers, and decoding efficiency is traditional two-value decoder efficiency (1.5)nTimes. The three value 4-81 lines address decoders that utilization CNFET of the invention is realized compare two-value address decoder, and identical bits input three is worth Address decoder can control more sram cells.The decoding efficiency of the address decoder for therefore designing herein is high, while also subtracting Few coding chip packaging pin number.
The three value 4-81 lines address decoders that utilization CNFET of the invention is realized are translated with existing 6-64 lines two-value address The power consumption of code device (conventional decoder and Block decoder) is contrasted, compared to two-value address decoder, utilization CNFET of the invention The power consumption of the three value 4-81 line address decoders realized at least reduces 37.1%.Therefore, the three of utilization CNFET realizations of the invention Value 4-81 line address decoder performances are greatly improved, such that it is able to improve the performance of SRAM.
The address decoder power consumption of table 2
SRAM is main to be made up of SRAM array and its peripheral circuit, used as the decoder and sense amplifier pair of peripheral circuit The raising of SRAM performances plays a significantly greater role.During SRAM data read-write operation, address decoder time delay accounts for total time delay More than half, therefore reduce address decoder power consumption can reduce SRAM power consumptions.In address decoder output end number difference When less, table 3 is existing 6-64 lines two-value address decoder (conventional decoder and Block decoder) and utilization of the invention The contrast of the three value 4-81 line address decoder time delays that CNFET is realized.As can be drawn from Table 3, utilization CNFET of the invention is realized Three value 4-81 lines address decoders at least reduce 41.1% compared to existing two-value address decoder time delay.Utilization of the invention The three value 4-81 line address decoders time delays that CNFET is realized are reduced, such that it is able to improve the performance of SRAM.
Table 3 three is worth the contrast of address decoder and two-value address decoder time delay.

Claims (8)

1. the three value 4-81 line address decoders that a kind of utilization CNFET is realized, it is characterised in that including ten three value 2-9 lines addresses Decoder, three described value 2-9 line address decoders have Enable Pin, first input end, the second input, the first output end, Second output end, the 3rd output end, the 4th output end, the 5th output end, the 6th output end, the 7th output end, the 8th output end With the 9th output end；Three value 2-9 line address decoders described in ten are respectively the one or three value 2-9 lines address decoder, second Three value 2-9 lines address decoders, the three or three value 2-9 lines address decoder, the four or three value 2-9 lines address decoder, the five or three value 2-9 lines address decoder, the six or three value 2-9 lines address decoder, the seven or three value 2-9 lines address decoder, the eight or three value 2-9 lines Address decoder, the 9th 3 value 2-9 lines address decoder and the 13rd value 2-9 line address decoders；The one or three described value 2-9 The Enable Pin connection of the first output end of line address decoder and the two or three described value 2-9 line address decoders, described the The Enable Pin connection of the second output end of one or three value 2-9 line address decoders and the three or three described value 2-9 line address decoders, The one or three described the 3rd output end of value 2-9 line address decoders and making for the four or three described value 2-9 line address decoders Can end connection, the 4th output end of described the one or three value 2-9 line address decoders and the five or three described value 2-9 lines address are translated The Enable Pin connection of code device, the 5th output end and the six or three described value 2-9 of described the one or three value 2-9 line address decoders The Enable Pin connection of line address decoder, the 6th output end of described the one or three value 2-9 line address decoders and described the The Enable Pin connection of seven or three value 2-9 line address decoders, the 7th output end of described the one or three value 2-9 line address decoders with The Enable Pin connection of the eight or three described value 2-9 line address decoders, the 8th of described the one or three value 2-9 line address decoders the The Enable Pin connection of output end and the 9th 3 described value 2-9 line address decoders, the one or three described value 2-9 line address decodings The Enable Pin connection of the 9th output end of device and the 13rd described value 2-9 line address decoders, the two or three described value 2-9 lines First input end, the described the 4th 3 of the first input end of address decoder, the three or three described value 2-9 line address decoders It is the first input end of value 2-9 line address decoders, the first input end of the five or three described value 2-9 line address decoders, described The first input end of the six or three value 2-9 line address decoders, the first input of the seven or three described value 2-9 line address decoders End, the first input end of described eight or three value 2-9 line address decoders, the 9th 3 described value 2-9 line address decoders The first input end of first input end and the 13rd described value 2-9 line address decoders is connected and its connection end is described three The first input end of value 4-81 line address decoders, it is the second input of described the two or three value 2-9 line address decoders, described The second input of the three or three value 2-9 line address decoders, the second input of the four or three described value 2-9 line address decoders End, the second input of described five or three value 2-9 line address decoders, the six or three described value 2-9 line address decoders Second input, the second input of the seven or three described value 2-9 line address decoders, the eight or three described value 2-9 lines address Second input of decoder, the second input of the 9th 3 described value 2-9 line address decoders and the 13rd described value The second input connection of 2-9 line address decoders and its connection end are the second defeated of three described value 4-81 line address decoders Enter end, the first input end of the one or three described value 2-9 line address decoders is three described value 4-81 line address decoders 3rd input, the second input of the one or three described value 2-9 line address decoders is that three described value 4-81 lines addresses are translated 4th input of code device, the Enable Pin of the one or three described value 2-9 line address decoders is three described value 4-81 lines addresses The Enable Pin of decoder；
Three described value 2-9 lines address decoders include two the value 1-3 lines address decoders of structure identical three, nine structure phases Same three input nand gates and nine structure identical phase inverters；Three described value 1-3 line address decoders have input, One output end, the second output end and the 3rd output end, three described input nand gates have first input end, the second input, 3rd input and output end；Three described value 1-3 lines address decoders include CNFET pipes, the 2nd CNFET pipes, the 3rd CNFET pipes, the 4th CNFET pipes, the 5th CNFET pipes, the 6th CNFET pipes, the 7th CNFET pipes, the 8th CNFET pipes, the 9th CNFET Pipe, the tenth CNFET pipes and the 11st CNFET pipes；Described the 3rd CNFET pipes, described the 4th CNFET pipes, the described the 7th CNFET pipes, described 8th CNFET pipes and the tenth described CNFET pipes are p-type CNFET pipes, described CNFET pipes, The 2nd described CNFET is managed, described the 5th CNFET pipes, described the 6th CNFET pipes, the 9th described CNFET are managed and described The 11st CNFET pipes be N-type CNFET pipe；The grid of a described CNFET pipes, the source of the 4th described CNFET pipes Pole, the source electrode, the source electrode of the 8th described CNFET pipes and the tenth described CNFET pipes of the 7th described CNFET pipes source electrode it is equal The first power supply is accessed, the drain electrode of a described CNFET pipes accesses second source, and described second source is the first described electricity The half in source；The grid of the 8th described CNFET pipes, the grid of the 9th described CNFET pipes, the tenth described CNFET pipes The grid of grid and the 11st described CNFET pipes is connected and its connection end is the defeated of three described value 1-3 line address decoders Enter end；The grid of the 2nd described CNFET pipes, the grid of the 3rd described CNFET pipes, the drain electrode of the 8th described CNFET pipes It is the first of three described value 1-3 line address decoders to export with the drain electrode connection of the 9th described CNFET pipes and its connection end End；The source electrode of the 2nd described CNFET pipes, the source electrode of the 5th described CNFET pipes, source electrode, the institute of the 6th described CNFET pipes The source electrode of the 9th CNFET pipes stated and the source grounding of the 11st described CNFET pipes；The grid of the 6th described CNFET pipes Pole, the grid of the 7th described CNFET pipes, the drain electrode of the tenth described CNFET pipes and the drain electrode of the 11st described CNFET pipes Connection, grid, the grid of the 5th described CNFET pipes, the drain electrode of the 6th described CNFET pipes of described the 4th CNFET pipes With the 3rd output that the drain electrode connection of the 7th described CNFET pipes and its connection end are three described value 1-3 line address decoders End；The source electrode of a described CNFET pipes, the drain electrode of the 2nd described CNFET pipes, the drain electrode of the 3rd described CNFET pipes and The drain electrode of the 5th described CNFET pipes is connected and its connection end is the second output end of three described value 1-3 line address decoders； The drain electrode connection of the source electrode and the 4th described CNFET pipes of the 3rd described CNFET pipes；Three value 1-3 lines addresses described in two Decoder is respectively the one or three value 1-3 lines address decoder and the two or three value 1-3 line address decoders, three inputs described in nine NAND gate be respectively the one or three input nand gate, the two or three input nand gate, the three or three input nand gate, the four or three input with it is non- Door, the five or three input nand gate, the six or three input nand gate, the seven or three input nand gate, the eight or three input nand gate and the 9th Three input nand gates, the phase inverter described in nine is respectively the first phase inverter, the second phase inverter, the 3rd phase inverter, the 4th anti-phase Device, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter and the 9th phase inverter；The one or three described value 1-3 The input of line address decoder is the first input end of three described value 2-9 line address decoders, the two or three described value 1-3 The input of line address decoder is the second input of three described value 2-9 line address decoders, the one or three described value 1-3 First output end of line address decoder respectively with the second input, the described the 2nd 3 of the one or three described input nand gate The second input connection of the second input of input nand gate and the three or three described input nand gate；The one or three described value Second output end of 1-3 line address decoders the second input respectively with the four or three described input nand gate, described The second input connection of the second input of five or three input nand gates and the six or three described input nand gate；Described first It is 3rd output end of three value 1-3 line address decoders the second input respectively with the seven or three described input nand gate, described The eight or three input nand gate the second input and the 9th 3 described input nand gate the second input connection；Described First output end of the two or three value 1-3 line address decoders the 3rd input respectively with the one or three described input nand gate, The 3rd input connection of the 3rd input and the seven or three described input nand gate of the four or three described input nand gate；Institute Second output end of the two or the three value 1-3 line address decoders stated respectively with the 3rd input of the two or three described input nand gate 3rd input at end, the 3rd input of the five or three described input nand gate and the eight or three described input nand gate connects Connect；3rd output end of the two or three described value 1-3 line address decoders is respectively with the of the three or three described input nand gate 3rd input of three inputs, the 3rd input of the six or three described input nand gate and the 9th 3 described input nand gate End connection；The first input end of the one or three described input nand gate, the first input end of the two or three described input nand gate, It is the first input end of the three or three described input nand gate, the first input end of the four or three described input nand gate, described First input end, the described the 7th 3 of the first input end of the five or three input nand gate, the six or three described input nand gate The first input end of input nand gate, the first input end of the eight or three described input nand gate and described 9th 3 input with The first input end of not gate is connected and its connection end is the Enable Pin of three described value 2-9 line address decoders；Described first The input connection of the output end of three input nand gates and the first described phase inverter, described the two or three input nand gate it is defeated The input for going out end and the second described phase inverter is connected, the output end and the described the 3rd of described the three or three input nand gate The input connection of phase inverter, the described output end of the four or three input nand gate and the input of the 4th described phase inverter connects Connect, the described output end of the five or three input nand gate and the input of the 5th described phase inverter is connected, the described the 6th 3 The input connection of the output end of input nand gate and described hex inverter, the output of described the seven or three input nand gate The input of end and the 7th described phase inverter is connected, the output end of described the eight or three input nand gate and the described the 8th anti- The input connection of phase device, the described output end of the 9th 3 input nand gate and the input of the 9th described phase inverter connects Connect；The output end of the first described phase inverter is the first output end of three described value 2-9 line address decoders, described second The output end of phase inverter is the second output end of three described value 2-9 line address decoders, the output of described the 3rd phase inverter It is the 3rd output end of three described value 2-9 line address decoders to hold, and the output end of the 4th described phase inverter is described three 4th output end of value 2-9 line address decoders, the output end of the 5th described phase inverter is that three described value 2-9 lines addresses are translated 5th output end of code device, the output end of described hex inverter is the 6th defeated of three described value 2-9 line address decoders Go out end, the output end of the 7th described phase inverter is the 7th output end of three described value 2-9 line address decoders, described the The output end of eight phase inverters is the 8th output end of three described value 2-9 line address decoders, described the 9th phase inverter it is defeated It is the 9th output end of three described value 2-9 line address decoders to go out end.
2. the 4-81 line address decoders that a kind of utilization CNFET according to claim 1 is realized, it is characterised in that described The threshold voltage of the first CNFET pipes is 0.428v, the threshold voltage and the described the 5th of described the 2nd described CNFET pipes The threshold voltage of CNFET pipes is 0.557v, the threshold voltage of described the 3rd CNFET pipes and the 4th described CNFET pipes Threshold voltage is -0.557v, the threshold voltage and the threshold voltage of the 9th described CNFET pipes of described the 6th CNFET pipes It is 0.289v, the described threshold voltage of the 7th CNFET pipes and the threshold voltage of the 8th described CNFET pipes be- 0.557v, the threshold voltage of the tenth described CNFET pipes is -0.289v, and the threshold voltage of the 11st described CNFET pipes is 0.557v。
3. the 4-81 line address decoders that a kind of utilization CNFET according to claim 1 is realized, it is characterised in that described The caliber of the first CNFET pipes is 1.018nm, caliber, caliber, the institute of the 3rd described CNFET pipes of described the 2nd CNFET pipes It is the caliber of the 4th CNFET pipes stated, the caliber of the 5th described CNFET pipes, the caliber of the 7th described CNFET pipes, described The caliber of the caliber of the 8th CNFET pipes and the 11st described CNFET pipes is 0.783nm, the pipe of described the 6th CNFET pipes The caliber of footpath and the 9th described CNFET pipes is 1.487nm, and the caliber of the tenth described CNFET pipes is 1.488nm.
4. the three value 4-81 line address decoders that a kind of utilization CNFET according to claim 1 is realized, it is characterised in that institute The first power supply stated is 0.9v, and described second source is 0.45v.
5. the three value 4-81 line address decoders that a kind of utilization CNFET according to claim 1 is realized, it is characterised in that institute Three input nand gates stated are managed including the 12nd CNFET pipes, the 13rd CNFET pipes, the 14th CNFET, the 15th CNFET is managed, 16th CNFET pipes, the 17th CNFET pipes and the 18th CNFET pipes；Described the 12nd CNFET pipes, the described the 16th CNFET is managed and the 17th described CNFET pipes are p-type CNFET pipes, described the 13rd CNFET pipes, the described the 14th CNFET pipes, described the 15th CNFET pipes and the 18th described CNFET pipes are N-type CNFET pipes；Described the 12nd The source electrode of CNFET pipes, the source electrode of the 16th described CNFET pipes, the source electrode and the described the tenth of the 17th described CNFET pipes The grid of eight CNFET pipes accesses the first described power supply, and drain described in access the second of the 18th described CNFET pipes is electric Source；The grid of the 12nd described CNFET pipes and the grid of the 13rd described CNFET pipes are connected and its connection end is described The first input end of three input nand gates, the drain electrode of described the 12nd CNFET pipes, the drain electrode of the 13rd described CNFET pipes, The source of the drain electrode, the drain electrode of the 17th described CNFET pipes and the 18th described CNFET pipes of the 16th described CNFET pipes Pole connects and its connection end is the output end of three described input nand gates, the source electrode of described the 13rd CNFET pipes and described The 14th CNFET pipes drain electrode connection, the leakage of the source electrode and the 15th described CNFET pipes of described the 14th CNFET pipes Pole connects, the grid connection of the grid and the 16th described CNFET pipes of described the 14th CNFET pipes and its connection end is institute Second input of three input nand gates stated, the source ground of described the 15th CNFET pipes, the 15th described CNFET The grid connection of the grid of pipe and the 17th described CNFET pipes and its connection end are the 3rd defeated of three described input nand gates Enter end.
6. the three value 4-81 line address decoders that a kind of utilization CNFET according to claim 5 is realized, it is characterised in that institute The caliber of the 12nd CNFET pipes stated, the caliber of the 13rd described CNFET pipes, the caliber of the 14th described CNFET pipes, The pipe of the caliber, the caliber of the 16th described CNFET pipes and the 17th described CNFET pipes of the 15th described CNFET pipes Footpath is 0.783nm, and the caliber of the 18th described CNFET pipes is 1.018nm.
7. the three value 4-81 line address decoders that a kind of utilization CNFET according to claim 1 is realized, it is characterised in that institute The phase inverter stated includes the 19th CNFET pipes, the 20th CNFET pipes and the 21st CNFET pipes, the 19th described CNFET Manage as p-type CNFET is managed, described the 20th CNFET pipes and the 21st described CNFET pipes are N-type CNFET pipes；It is described The source electrode of the 19th CNFET pipes and the grid of the 21st described CNFET pipes access the first described power supply, it is described The drain electrode of the 21st CNFET pipes access described in second source, the grid and described second of described the 19th CNFET pipes The grid connection of ten CNFET pipes and its connection end are the input of described phase inverter, the leakage of described the 19th CNFET pipes The source electrode of pole, the drain electrode of the 20th described CNFET pipes and the 21st described CNFET pipes is connected and its connection end is described Phase inverter output end, the source ground of described the 20th CNFET pipes.
8. the three value 4-81 line address decoders that a kind of utilization CNFET according to claim 7 is realized, it is characterised in that institute The caliber of the 19th CNFET pipes stated and the caliber of the 20th described CNFET pipes are 0.783nm, the described the 21st The caliber of CNFET pipes is 1.018nm.
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