CN105976856B - A kind of latch-type flowing structure high speed address decoder applied to Static RAM - Google Patents
A kind of latch-type flowing structure high speed address decoder applied to Static RAM Download PDFInfo
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- CN105976856B CN105976856B CN201610504828.XA CN201610504828A CN105976856B CN 105976856 B CN105976856 B CN 105976856B CN 201610504828 A CN201610504828 A CN 201610504828A CN 105976856 B CN105976856 B CN 105976856B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Abstract
The invention discloses a kind of latch-type flowing structure high speed address decoders applied to Static RAM, decoding time caused by pre-decode module can be eliminated is lost, its second level decoding module can effectively improve the decoding speed of second level decoding module using the novel decoding circuit structure by clock control proposed in the present invention simultaneously, and then improve the performance of entire address decoder.Especially suitable for having in the circuit of particular/special requirement to decoding speed, such as high-performance SRAM.
Description
Technical field
The present invention relates to integrated circuit (IC) design field more particularly to a kind of latches applied to Static RAM
Type flowing structure high speed address decoder.
Background technology
With the development of science and technology, the demand to high-speed low-power-consumption integrated circuit is growing day by day.In processor and the system integration
The working frequency of SRAM becomes the principal element for restricting performance in chip (SoC).The performance of SRAM memory cell depends primarily on
Manufacturing process, this has had exceeded the control range of circuit designers.Therefore, the method for improving SRAM performances is concentrated mainly on pair
The improvement of SRAM peripheral circuits.Address decoder is one of most important peripheral circuits of SRAM, high speed, the address decoder stablized
The Performance And Reliability of SRAM can greatly be improved.
Two level decoding architecture be in SRAM design through frequently with structure.Its basic thought is：In the control of enable signal
Under, address signal inputs in pre-decode module (i.e. first order decoding circuit) into row decoding；Later, the result first order decoded
Second level decoding module is input into row decoding, final output wordline or bit line signal by permutation and combination.Using this structure
Compared to single-stage decoder, the number of transistors used is greatly reduced, while also reducing its transmission delay.
Existing decoding circuit structure can be divided into static decoders and dynamic decoder, and concrete structure is as follows：
1) it is as shown in fig. 1 2-4 static decoders, it is made of phase inverter and logic gate.It has a disadvantage in that, when
When input port is more than 5, the parasitic capacitance of logic gate becomes very large, and has seriously affected decoding speed.
2) as shown in Figure 2 be 2-4 dynamic N OR decoders, it by preliminary filling pipe with pull down evaluation network form, by when clock
Preliminary filling or evaluation operation processed：When clock falling edge temporarily, output node to be charged to high potential；When rising edge clock arrives
When, preliminary filling pipe cut-off, evaluation network is started to work, and final decoding result is exported.It has a disadvantage in that, using the dynamic of this structure
State decoder is easy to generate burr in output to influence the accuracy of decoding.
3) it is 3-8 domino buffer structure dynamic nor gate decoding circuit structures as shown in Figure 3, it is by dynamically or non-
Door is bonded with domino buffer.When enable signal EN is low level, decoder does not work, and at this moment output node Q is
Low level.When enable signal EN is high level, decoder is started to work：If at this moment control clock is low level, node Y is filled
For electricity to high level, output node Q is low level；If control clock is high level, circuit starts to decode, and exports final decoding knot
Fruit.It has a disadvantage in that, dynamic power consumption is larger while which increase the complexities of design to control sequential more demanding.
Invention content
The object of the present invention is to provide a kind of latch-type flowing structure high speed addresses applied to Static RAM to translate
The decoding speed of code device, the decoder is very quick and address signal no longer influences to translate in advance when two level decoding module works
The output of code module, the decoder can greatly improve the opening speed of SRAM wordline to improve the operating rate of SRAM simultaneously
And can to avoid being interfered due to address signal caused by maloperation.
The purpose of the present invention is what is be achieved through the following technical solutions：
A kind of latch-type flowing structure high speed address decoder applied to Static RAM, including：
The pre-decode module by clock control being connected with each other and the two level decoding module by clock control；
Wherein, several decoding circuits by clock control are contained in the two level decoding module by clock control；
The decoding circuit by clock control includes：4 input ports：PA, PB, PC, FLOAT；1 output port Q；
1 two input nor gate NOR0；1 two input nand gate NAND0；6 phase inverters：INV0, INV1, INV2, INV3, INV4,
INV5；2 PMOS tube：P0, P1；1 NMOS tube N0；
Input terminal PA and PB is connected to the input terminal of two input nor gate NOR0, the output end output of two input nor gate NOR0
Y；Y is connected to the input terminal of phase inverter INV0, and the output end of phase inverter INV0 exports Y '；Y ' is connected to the input terminal of phase inverter INV1,
The output end of phase inverter INV1 exports Y_delay, while Y ' is connected to the source electrode of NMOS tube N0；Y_delay is connected to PMOS tube P1's
Grid；Input terminal PC is connected to the input terminal of phase inverter INV4, and the output end of phase inverter INV4 exports PCB；Input terminal FLOAT is connected to
Phase inverter INV3 input terminals, phase inverter INV3 output ends export FLOATB；PCB, FLOATB are input to two input nand gate NAND0
Input terminal, two input nand gate NAND0 output ends export Z；Z is connected to phase inverter INV5 input terminals, phase inverter INV5 outputs
End output ZB；ZB is connected to the grid of NMOS tube N0 and PMOS tube P0；The source electrode of PMOS tube P0 is connected to power vd D；PMOS tube P0's
Drain electrode is connected to X nodes with the drain electrode of NMOS tube N0 and the drain electrode of PMOS tube P1, is connected to the input of phase inverter INV2 later
The output end at end, phase inverter INV2 exports Q；The source electrode of PMOS tube P1 is connected to power vd D.
The pre-decode module by clock control includes：Input terminal FLOAT and A<6:0>；Output end PC<1:0>,
PB<7:0>And PA<7:0>；1 address input module ADR0 by clock control；2 3-8 by clock control decode mould
Block DEC0 and DEC1；Wherein：
Input terminal FLOAT is connected to the address input module ADR0 by clock control, by the 3-8 decoding modules of clock control
The input terminal FLOAT of DEC1 and DEC0；
Input terminal A<6:0>In A<6>Port is connected to the input port of the address input module ADR0 by clock control
A；
Input terminal A<6:0>In A<5:3>Port is connected respectively to be inputted by the 3-8 decoding modules DEC0 of clock control
Port A<2:0>；Input terminal A<6:0>In A<2:0>Port is connected respectively to the 3-8 decoding modules DEC1 by clock control
Input port A<2:0>；
Output end PC<1:0>In PC<1>Port is connected to the output end of the address input module ADR0 by clock control
Mouth AT；Output end PC<1:0>In PC<0>Port is connected to the output port of the address input module ADR0 by clock control
AB；Output end PB<7:0>It is connected respectively the output port QB of the 3-8 decoding modules DEC0 by clock control<7:0>；Output
Hold PA<7:0>It is connected respectively the output port QB of the 3-8 decoding modules DEC1 by clock control<7:0>.
The address input module by clock control includes：Input terminal A and FLOAT；Output terminals A B and AT；Phase inverter
INV0 and INV1；Controlled reverser CINV0；NMOS tube N0 and N1；PMOS tube P0 and P1；Wherein：
Input terminal A is connected to the grid of PMOS tube P1 and NMOS tube N0；Input terminal FLOAT is connected to the input terminal of phase inverter INV0
FLOATB is exported, while input terminal FLOAT is connected to the Enable Pin of the grid and controlled reverser CINV0 of NMOS tube N1；FLOATB
It is connected to the grid of PMOS tube P0；The source electrode of PMOS tube P0 is connected to power vd D, and the drain electrode of PMOS tube P0 is connected to the source of PMOS tube P1
Pole；The source electrode of NMOS tube N1 is connected to ground VSS, and the drain electrode of NMOS tube N1 is connected to the source electrode of NMOS tube N0；The drain electrode of PMOS tube P1 with
The drain electrode of NMOS tube N0, which is connected together, is connected to the output end of controlled reverser CINV0, output end as output terminals A B, output terminals A B
AB is connected to the input terminal of phase inverter IINV1；Output terminals A T is also coupled to the input terminal of controlled reverser CINV0.
The 3-8 decoding modules by clock control include：Input terminal FLOAT and A<2:0>；Output port QB<7:0
>；3 address input modules by clock control：ADR00, ADR1 and ADR2；8 three input nand gates：NAND0,NAND1,
NAND2, NAND3, NAND4, NAND5, NAND6 and NAND7；Wherein：
Input terminal A<2:0>In A<2>Port is connected to the input terminal A of the address input module ADR2 by clock control；It is defeated
Enter to hold A<2:0>In A<1>Port is connected to the input terminal A of the address input module ADR1 by clock control；Input terminal A<2:0>
In A<0>Port is connected to the input terminal A of the address input module ADR00 by clock control；Input terminal FLOAT is connected respectively to
By the input terminal FLOAT of address input module ADR2, ADR1 and ADR00 of clock control；
Address input module ADR2 by clock control exports AT<2>, AB<2>；By the address input module of clock control
ADR1 exports AT<1>, AB<1>；Address input module ADR00 by clock control exports AT<0>, AB<0>；
AT therein<2>, AT<1>, AT<0>QB is exported after being input to three input nand gate NAND7<7>；
AT therein<2>, AT<1>, AB<0>QB is exported after being input to three input nand gate NAND6<6>；
AT therein<2>, AB<1>, AT<0>QB is exported after being input to three input nand gate NAND5<5>；
AT therein<2>, AB<1>, AB<0>QB is exported after being input to three input nand gate NAND4<4>；
AB therein<2>, AT<1>, AT<0>QB is exported after being input to three input nand gate NAND3<3>；
AB therein<2>, AT<1>, AB<0>QB is exported after being input to three input nand gate NAND2<2>；
AB therein<2>, AB<1>, AT<0>QB is exported after being input to three input nand gate NAND1<1>；
AB therein<2>, AB<1>, AB<0>QB is exported after being input to three input nand gate NAND0<0>；
The QB of output<0>~QB<7>The as title of corresponding output port finally constitutes the 3-8 decodings by clock control
The output port QB of module<7:0>.
The two level decoding module by clock control includes：
Input port FLOAT, PA<7:0>,PB<7:0>And PC<1:0>；128 decoding circuits by clock control,
Each decoding circuit by clock control has an output port, then constitutes 128 of the two level decoding module by clock control
A output port WL<127:0>；
There are four types of the input ports of type for each decoding circuit by clock control：FLOAT, PA, PB and PC；By described
Input port FLOAT, PA<7:0>,PB<7:0>And PC<1:0>128 groups are formed by way of permutation and combination includes
The input port of these four types of FLOAT, PA, PB and PC is simultaneously separately input into each decoding circuit by clock control.
When clock signal clk is high level, Static RAM SRAM is operated in hold mode, address signal input
To by clock control pre-decode module, the pre-decode module by clock control by pre-decode result be transported to by when clock
The two level decoding module of system is not worked by the two level decoding module of clock control at this time；When clock signal clk saltus step is low level
When, SRAM is operated in read-write state, address signal and is disconnected and is latched in before CLK saltus steps by the pre-decode module of clock control
The address signal of input, while being started to work by the two level decoding module of clock control and exporting decoding result.
As seen from the above technical solution provided by the invention, decoding time caused by capable of eliminating pre-decode module damages
Consumption, while its second level decoding module can be carried effectively using the decoding circuit structure by clock control proposed in the present invention
The decoding speed of high second level decoding module, and then improve the performance of entire address decoder.Especially suitable for decoding speed
Have in the circuit of particular/special requirement, such as high-performance SRAM.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is traditional 2-4 static decoders electrical block diagram that background of invention provides；
Fig. 2 is the structural schematic diagram for traditional 2-4 dynamic Ns OR decoder circuits that background of invention provides；
Fig. 3 is traditional 3-8 domino buffer structure dynamic nor gate decoding circuit that background of invention provides
Structural schematic diagram；
Fig. 4 is the structural schematic diagram of the decoding circuit provided in an embodiment of the present invention by clock control；
Fig. 5 is the structural schematic diagram of the pre-decode module provided in an embodiment of the present invention by clock control；
Fig. 6 is the structural schematic diagram of the address input module provided in an embodiment of the present invention by clock control；
Fig. 7 is the structural schematic diagram of the 3-8 decoding modules provided in an embodiment of the present invention by clock control；
Fig. 8 is the structural schematic diagram of the two level decoding module provided in an embodiment of the present invention by clock control；
Fig. 9 is that the latch-type flowing structure high speed address provided in an embodiment of the present invention applied to Static RAM is translated
Code device structure and its course of work schematic diagram；
Figure 10 is controlled for the discharging model and traditional cmos of the decoding circuit provided in an embodiment of the present invention by clock control
The discharging model schematic diagram of decoding circuit；
Figure 11 is the decoding circuit provided in an embodiment of the present invention by clock control and the controlled CMOS decoding circuits of tradition
Decoding speed contrast schematic diagram；
Figure 12 is the latch-type flowing structure high speed address provided in an embodiment of the present invention applied to Static RAM
The decoding speed contrast schematic diagram of decoder and conventional decoder.
Specific implementation mode
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
The embodiment of invention, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, belongs to protection scope of the present invention.
The embodiment of the present invention provides a kind of latch-type flowing structure high speed address decoding applied to Static RAM
Device, including：
The pre-decode module by clock control being connected with each other and the two level decoding module by clock control；
Wherein, several decoding circuits by clock control are contained in the two level decoding module by clock control；
The decoding circuit by clock control is as shown in figure 4, include mainly：4 input ports：PA, PB, PC,
FLOAT；1 output port Q；1 two input nor gate NOR0；1 two input nand gate NAND0；6 phase inverters：INV0,
INV1, INV2, INV3, INV4, INV5；2 PMOS tube：P0, P1；1 NMOS tube N0；
Input terminal PA and PB is connected to the input terminal of two input nor gate NOR0, the output end output of two input nor gate NOR0
Y；Y is connected to the input terminal of phase inverter INV0, and the output end of phase inverter INV0 exports Y '；Y ' is connected to the input terminal of phase inverter INV1,
The output end of phase inverter INV1 exports Y_delay, while Y ' is connected to the source electrode of NMOS tube N0；Y_delay is connected to PMOS tube P1's
Grid；Input terminal PC is connected to the input terminal of phase inverter INV4, and the output end of phase inverter INV4 exports PCB；Input terminal FLOAT is connected to
Phase inverter INV3 input terminals, phase inverter INV3 output ends export FLOATB；PCB, FLOATB are input to two input nand gate NAND0
Input terminal, two input nand gate NAND0 output ends export Z；Z is connected to phase inverter INV5 input terminals, phase inverter INV5 outputs
End output ZB；ZB is connected to the grid of NMOS tube N0 and PMOS tube P0；The source electrode of PMOS tube P0 is connected to power vd D；PMOS tube P0's
Drain electrode is connected to X nodes with the drain electrode of NMOS tube N0 and the drain electrode of PMOS tube P1, is connected to the input of phase inverter INV2 later
The output end at end, phase inverter INV2 exports Q；The source electrode of PMOS tube P1 is connected to power vd D.
The operation principle of the decoding circuit by clock control that the present invention implements to provide is：As input port PA, PB, PC,
When the signal of FLOAT is all low level, output end Q is high level.When clock signal clk is high level, signal is just defeated
Enter PA, PB, pc port (clock signal clk inputs the ports FLOAT), as long as at this moment CLK signal is reduced to low level, by clock control
Decoding circuit i.e. start to work.For selected decoding circuit, the signal for inputting its port PA, PB, PC is low level, this
When P1 pipes be turned off, node Y ' is pulled to low level, when CLK saltus steps be low level when decoding circuit nodes X start to discharge.
In the embodiment of the present invention, the pre-decode module by clock control is as shown in figure 5, it includes mainly：Input terminal
FLOAT and A<6:0>；Output end PC<1:0>,PB<7:0>And PA<7:0>；1 address by clock control inputs mould
Block ADR0；2 3-8 the decoding modules DEC0 and DEC1 by clock control；Wherein：
Input terminal FLOAT is connected to the address input module ADR0 by clock control, by the 3-8 decoding modules of clock control
The input terminal FLOAT of DEC1 and DEC0；
Input terminal A<6:0>In A<6>Port is connected to the input port of the address input module ADR0 by clock control
A；
Input terminal A<6:0>In A<5:3>Port is connected respectively to be inputted by the 3-8 decoding modules DEC0 of clock control
Port A<2:0>；Input terminal A<6:0>In A<2:0>Port is connected respectively to the 3-8 decoding modules DEC1 by clock control
Input port A<2:0>；
Output end PC<1:0>In PC<1>Port is connected to the output end of the address input module ADR0 by clock control
Mouth AT；Output end PC<1:0>In PC<0>Port is connected to the output port of the address input module ADR0 by clock control
AB；Output end PB<7:0>It is connected respectively the output port Q of the 3-8 decoding modules DEC0 by clock control<7:0>；Output
Hold PA<7:0>It is connected respectively the output port Q of the 3-8 decoding modules DEC1 by clock control<7:0>.
It will be understood by those skilled in the art that input terminal A<6:0>Including 7 ports：A<0>,A<1>,...,A<5>,A<6
>.Similarly, port A<5:3>Including：A<3>,A<4>,A<5>；Port A<2:0>Including：A<0>,A<1>,A<2>.In addition, output
Hold PB<7:0>,PA<7:0>,Q<7:0>Include 8 ports, specific port name and input terminal A<6:0>It is similar, it is no longer superfluous
It states.To sum up, the above-mentioned literary style in each port involved by the embodiment of the present invention is general descriptor in the art, this field skill
Art personnel can be clear that its meaning.
In the embodiment of the present invention, the address input module by clock control is as shown in fig. 6, it includes mainly：Input
Hold A and FLOAT；Output terminals A B and AT；Phase inverter INV0 and INV1；Controlled reverser CINV0；NMOS tube N0 and N1；PMOS tube
P0 and P1；Wherein：
Input terminal A is connected to the grid of PMOS tube P1 and NMOS tube N0；Input terminal FLOAT is connected to the input terminal of phase inverter INV0
FLOATB is exported, while input terminal FLOAT is connected to the Enable Pin of the grid and controlled reverser CINV0 of NMOS tube N1；FLOATB
It is connected to the grid of PMOS tube P0；The source electrode of PMOS tube P0 is connected to power vd D, and the drain electrode of PMOS tube P0 is connected to the source of PMOS tube P1
Pole；The source electrode of NMOS tube N1 is connected to ground VSS, and the drain electrode of NMOS tube N1 is connected to the source electrode of NMOS tube N0；The drain electrode of PMOS tube P1 with
The drain electrode of NMOS tube N0, which is connected together, is connected to the output end of controlled reverser CINV0, output end as output terminals A B, output terminals A B
AB is connected to the input terminal of phase inverter IINV1；Output terminals A T is also coupled to the input terminal of controlled reverser CINV0.
In the embodiment of the present invention, the 3-8 decoding modules by clock control are as shown in fig. 7, include mainly：Input terminal
FLOAT and A<2:0>；Output port QB<7:0>；3 address input modules by clock control：ADR00, ADR1 with
ADR2；8 three input nand gates：NAND0, NAND1, NAND2, NAND3, NAND4, NAND5, NAND6 and NAND7；Wherein：
Input terminal A<2:0>In A<2>Port is connected to the input terminal A of the address input module ADR2 by clock control；It is defeated
Enter to hold A<2:0>In A<1>Port is connected to the input terminal A of the address input module ADR1 by clock control；Input terminal A<2:0>
In A<0>Port is connected to the input terminal A of the address input module ADR00 by clock control；Input terminal FLOAT is connected respectively to
By the input terminal FLOAT of address input module ADR2, ADR1 and ADR00 of clock control；
Address input module ADR2 by clock control exports AT<2>, AB<2>；By the address input module of clock control
ADR1 exports AT<1>, AB<1>；Address input module ADR00 by clock control exports AT<0>, AB<0>；
AT therein<2>, AT<1>, AT<0>QB is exported after being input to three input nand gate NAND7<7>；
AT therein<2>, AT<1>, AB<0>QB is exported after being input to three input nand gate NAND6<6>；
AT therein<2>, AB<1>, AT<0>QB is exported after being input to three input nand gate NAND5<5>；
AT therein<2>, AB<1>, AB<0>QB is exported after being input to three input nand gate NAND4<4>；
AB therein<2>, AT<1>, AT<0>QB is exported after being input to three input nand gate NAND3<3>；
AB therein<2>, AT<1>, AB<0>QB is exported after being input to three input nand gate NAND2<2>；
AB therein<2>, AB<1>, AT<0>QB is exported after being input to three input nand gate NAND1<1>；
AB therein<2>, AB<1>, AB<0>QB is exported after being input to three input nand gate NAND0<0>；
The QB of output<0>~QB<7>The as title of corresponding output port finally constitutes the 3-8 decodings by clock control
The output port QB of module<7:0>.
In actual operation, can determine as needed it is described in by the two level decoding module of clock control by when clock
The particular number of the decoding circuit of system sets quantity by the decoding circuit of clock control in the embodiment of the present invention as 128, accordingly
The two level decoding module structure by clock control as shown in figure 8, it includes mainly：Input port FLOAT, PA<7:0>,PB<
7:0>And PC<1:0>；128 decoding circuit HSXDEC by clock control<127:0>, each to be decoded by clock control
Circuit has an output port, then constitutes 128 output port WL of the two level decoding module by clock control<127:0>；
There are four types of the input ports of type for each decoding circuit by clock control：FLOAT, PA, PB and PC；By described
Input port FLOAT, PA<7:0>,PB<7:0>And PC<1:0>128 groups are formed by way of permutation and combination includes
The input port of these four types of FLOAT, PA, PB and PC is simultaneously separately input into each decoding circuit by clock control.
It is a kind of latch-type flowing structure high speed applied to Static RAM provided in an embodiment of the present invention above
The main composed structure of address decoder, elaborates below for its course of work and principle.
In a kind of latch-type flowing structure high speed address applied to Static RAM provided in an embodiment of the present invention
In decoder, as shown in figure 9, address signal input is translated in advance (i.e. when FLOAT is high level) when SRAM is operated in hold mode
Code module, exports pre-decode result, that is, PC later<1:0>,PB<7:0>,PA<7:0>, and at this time since FLOAT is high level two
The output of grade decoding module is locked into low level (two level decoding module works when FLOAT is low level)；When SRAM works
The address signal inputted before FLOAT saltus steps are low level (i.e. when FLOAT is low level) when read-write state is locked
It deposits, at this moment address input end and the decoding portion disconnection of Pre-decoder module makes the variation of address signal no longer influence pre-decode knot
Fruit is to improve the anti-interference ability of decoder, and two level decoding module starts to decode and export decoding result at this time.
The decoding circuit of above-mentioned two level decoding module uses the decoding circuit structure provided by the invention by clock control, should
Circuit structure has faster decoding speed.Thus, using this technology can eliminate time that pre-decode stage is consumed from
And improve the operating rate of SRAM, while can also reduce be interfered due to address signal caused by maloperation.It is described by
The discharging model of the decoding circuit of clock control and the discharging model comparison of the controlled decoding circuit of traditional cmos are as shown in Figure 10.It is false
If the equivalent resistance of each NMOS tube is RN, then by the discharge time constant τ < 2R of the decoding circuit of clock controlN·CX,
The discharge time constant τ ≈ 4R of the controlled decoding circuit of traditional cmosN·CX, wherein CXFor the load capacitance of wordline.Figure 11 is two
The decoding speed comparison of kind decoding circuit, wherein Q_new is the output end voltage by the decoding circuit of clock control, and Q_tran is
The output end voltage of the controlled decoding circuit of traditional cmos, the voltage of H1 is the half of supply voltage, when word line voltage is more than H1,
Think to generate decoding result.
The principle of the latch-type flowing structure high speed address decoder applied to Static RAM is as follows：At that time
When clock signal CLK is high level, SRAM is operated in hold mode, and address signal is input to the pre-decode module by clock control,
Pre-decode result is transported to the two level decoding module by clock control by the pre-decode module by clock control, at this time by when
The two level decoding module of clock does not work；When clock signal clk saltus step is low level, SRAM is operated in read-write state, ground
Location signal (latched with being disconnected by the pre-decode module of clock control and be latched in the address signal inputted before CLK saltus steps
Pre-decode result), while being started to work by the two level decoding module of clock control and exporting decoding result.It is translated for 2 grades with tradition
The decoding speed comparison of code device is as shown in figure 12, and wherein Q_new is the output electricity of latch-type flowing structure high speed address decoder
Pressure, Q_tran are the output voltage of traditional 2 grades of decoders.It can be seen that latch-type flowing structure high speed address decoding from comparison
Device eliminates the influence of the time of pre-decode module consumption and its two level decoding module has faster decoding speed.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art is in the technical scope of present disclosure, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Subject to enclosing.
Claims (5)
1. a kind of latch-type flowing structure high speed address decoder applied to Static RAM, which is characterized in that including：
The pre-decode module by clock control being connected with each other and the two level decoding module by clock control；
Wherein, several decoding circuits by clock control are contained in the two level decoding module by clock control；
The decoding circuit by clock control includes：4 input ports：PA, PB, PC, FLOAT；1 output port Q；1
Two input nor gate NOR0；1 two input nand gate NAND0；6 phase inverters：INV0, INV1, INV2, INV3, INV4,
INV5；2 PMOS tube：P0, P1；1 NMOS tube N0；
Input terminal PA and PB is connected to the input terminal of two input nor gate NOR0, and the output end of two input nor gate NOR0 exports Y；Y
It is connected to the input terminal of phase inverter INV0, the output end of phase inverter INV0 exports Y '；Y ' is connected to the input terminal of phase inverter INV1, reverse phase
The output end of device INV1 exports Y_delay, while Y ' is connected to the source electrode of NMOS tube N0；Y_delay is connected to the grid of PMOS tube P1；
Input terminal PC is connected to the input terminal of phase inverter INV4, and the output end of phase inverter INV4 exports PCB；Input terminal FLOAT is connected to reverse phase
Device INV3 input terminals, phase inverter INV3 output ends export FLOATB；PCB, FLOATB are input to the defeated of two input nand gate NAND0
Enter end, two input nand gate NAND0 output ends export Z；Z is connected to phase inverter INV5 input terminals, and phase inverter INV5 output ends are defeated
Go out ZB；ZB is connected to the grid of NMOS tube N0 and PMOS tube P0；The source electrode of PMOS tube P0 is connected to power vd D；The drain electrode of PMOS tube P0
The drain electrode of drain electrode and PMOS tube P1 with NMOS tube N0 is connected to X nodes, is connected to the input terminal of phase inverter INV2 later, instead
The output end of phase device INV2 exports Q；The source electrode of PMOS tube P1 is connected to power vd D；
Wherein, when clock signal clk is high level, Static RAM SRAM is operated in hold mode, and address signal is defeated
Enter to the pre-decode module by clock control, pre-decode result is transported to by clock by the pre-decode module by clock control
The two level decoding module of control is not worked by the two level decoding module of clock control at this time；When clock signal clk saltus step is low electricity
Usually, SRAM is operated in read-write state, address signal with by the pre-decode module of clock control disconnect and be latched in CLK saltus steps it
The address signal of preceding input, while being started to work by the two level decoding module of clock control and exporting decoding result.
2. a kind of latch-type flowing structure high speed address decoding applied to Static RAM according to claim 1
Device, which is characterized in that the pre-decode module by clock control includes：Input terminal FLOAT and A<6:0>；Output end PC<
1:0>,PB<7:0>And PA<7:0>；1 address input module ADR0 by clock control；2 3-8 by clock control are translated
Code module DEC0 and DEC1；Wherein：
Input terminal FLOAT is connected to the address input module ADR0 by clock control, the 3-8 decoding modules DEC1 by clock control
With the input terminal FLOAT of DEC0；
Input terminal A<6:0>In A<6>Port is connected to the input port A of the address input module ADR0 by clock control；
Input terminal A<6:0>In A<5:3>Port is connected respectively to the input port of the 3-8 decoding modules DEC0 by clock control
A<2:0>；Input terminal A<6:0>In A<2:0>Port is connected respectively to be inputted by the 3-8 decoding modules DEC1 of clock control
Port A<2:0>；
Output end PC<1:0>In PC<1>Port is connected to the output port AT of the address input module ADR0 by clock control；
Output end PC<1:0>In PC<0>Port is connected to the output port AB of the address input module ADR0 by clock control；Output
Hold PB<7:0>It is connected respectively the output port QB of the 3-8 decoding modules DEC0 by clock control<7:0>；Output end PA<7:
0>It is connected respectively the output port QB of the 3-8 decoding modules DEC1 by clock control<7:0>.
3. a kind of latch-type flowing structure high speed address decoding applied to Static RAM according to claim 2
Device, which is characterized in that the address input module by clock control includes：Input terminal A and FLOAT；Output terminals A B and AT；Instead
Phase device INV0 and INV1；Controlled reverser CINV0；NMOS tube N0 and N1；PMOS tube P0 and P1；Wherein：
Input terminal A is connected to the grid of PMOS tube P1 and NMOS tube N0；Input terminal FLOAT is connected to the input terminal output of phase inverter INV0
FLOATB, while input terminal FLOAT is connected to the Enable Pin of the grid and controlled reverser CINV0 of NMOS tube N1；FLOATB is connected to
The grid of PMOS tube P0；The source electrode of PMOS tube P0 is connected to power vd D, and the drain electrode of PMOS tube P0 is connected to the source electrode of PMOS tube P1；
The source electrode of NMOS tube N1 is connected to ground VSS, and the drain electrode of NMOS tube N1 is connected to the source electrode of NMOS tube N0；The drain electrode of PMOS tube P1 and NMOS
The drain electrode of pipe N0, which is connected together, is connected to the output end of controlled reverser CINV0 as output terminals A B, output terminals A B, and output terminals A B connects
To the input terminal of phase inverter IINV1；Output terminals A T is also coupled to the input terminal of controlled reverser CINV0.
4. a kind of latch-type flowing structure high speed address applied to Static RAM according to claim 2 or 3
Decoder, which is characterized in that the 3-8 decoding modules by clock control include：Input terminal FLOAT and A<2:0>；Output
Port QB<7:0>；3 address input modules by clock control：ADR00, ADR1 and ADR2；8 three input nand gates：
NAND0, NAND1, NAND2, NAND3, NAND4, NAND5, NAND6 and NAND7；Wherein：
Input terminal A<2:0>In A<2>Port is connected to the input terminal A of the address input module ADR2 by clock control；Input terminal A
<2:0>In A<1>Port is connected to the input terminal A of the address input module ADR1 by clock control；Input terminal A<2:0>In A<
0>Port is connected to the input terminal A of the address input module ADR00 by clock control；Input terminal FLOAT is connected respectively to by clock
The input terminal FLOAT of address input module ADR2, ADR1 and ADR00 of control；
Address input module ADR2 by clock control exports AT<2>, AB<2>；By the address input module ADR1 of clock control
Export AT<1>, AB<1>；Address input module ADR00 by clock control exports AT<0>, AB<0>；
AT therein<2>, AT<1>, AT<0>QB is exported after being input to three input nand gate NAND7<7>；
AT therein<2>, AT<1>, AB<0>QB is exported after being input to three input nand gate NAND6<6>；
AT therein<2>, AB<1>, AT<0>QB is exported after being input to three input nand gate NAND5<5>；
AT therein<2>, AB<1>, AB<0>QB is exported after being input to three input nand gate NAND4<4>；
AB therein<2>, AT<1>, AT<0>QB is exported after being input to three input nand gate NAND3<3>；
AB therein<2>, AT<1>, AB<0>QB is exported after being input to three input nand gate NAND2<2>；
AB therein<2>, AB<1>, AT<0>QB is exported after being input to three input nand gate NAND1<1>；
AB therein<2>, AB<1>, AB<0>QB is exported after being input to three input nand gate NAND0<0>；
The QB of output<0>~QB<7>The as title of corresponding output port finally constitutes the 3-8 decoding modules by clock control
Output port QB<7:0>.
5. a kind of latch-type flowing structure high speed address applied to Static RAM according to claim 1 or 2
Decoder, which is characterized in that the two level decoding module by clock control includes：
Input port FLOAT, PA<7:0>,PB<7:0>And PC<1:0>；128 decoding circuits by clock control, it is each
Decoding circuit by clock control has an output port, then 128 of two level decoding module constituted by clock control are defeated
Exit port WL<127:0>；
There are four types of the input ports of type for each decoding circuit by clock control：FLOAT, PA, PB and PC；By the input
Port FLOAT, PA<7:0>,PB<7:0>And PC<1:0>Formed by way of permutation and combination 128 groups comprising FLOAT, PA,
The input port of these four types of PB and PC is simultaneously separately input into each decoding circuit by clock control.
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