KR940002027Y1 - Pusy t-type latch - Google Patents

Pusy t-type latch Download PDF

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Publication number
KR940002027Y1
KR940002027Y1 KR2019910022837U KR910022837U KR940002027Y1 KR 940002027 Y1 KR940002027 Y1 KR 940002027Y1 KR 2019910022837 U KR2019910022837 U KR 2019910022837U KR 910022837 U KR910022837 U KR 910022837U KR 940002027 Y1 KR940002027 Y1 KR 940002027Y1
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South Korea
Prior art keywords
current
pmos transistor
nmos
pmos
fuzzy
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KR2019910022837U
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Korean (ko)
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KR930016691U (en
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김정범
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금성일렉트론 주식회사
문정환
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Priority to KR2019910022837U priority Critical patent/KR940002027Y1/en
Publication of KR930016691U publication Critical patent/KR930016691U/en
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Publication of KR940002027Y1 publication Critical patent/KR940002027Y1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback

Abstract

내용 없음.No content.

Description

퍼지 T형 래치회로Fuzzy T-Latch Circuit

제1도는 본 고안 퍼지 T형 래치회로도.1 is a fuzzy T-type latch circuit diagram of the present invention.

제2도의 a 내지 d는 제1도에 따른 출력파형도.A to d in FIG. 2 are output waveforms according to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 2 : 엔모스전류미러 3 : 피모스전류미러1, 2: NMOS current mirror 3: PMOS current mirror

4 : 전류소스 MN1-MN5: 엔모스트랜지스터4: Current source MN 1 -MN 5 : Enmo transistor

MP1-MP5: 피모스트랜지스터 CTL : 제어단자MP 1 -MP 5 : PMOS transistor CTL: Control terminal

본 고안은 퍼지 T형 래치회로에 관한 것으로, 특히 퍼지논리를 이용한 퍼지정보처리에 적합하도록 한 퍼지 T형 래치회로에 관한 것이다.The present invention relates to a fuzzy T type latch circuit, and more particularly, to a fuzzy T type latch circuit suitable for fuzzy information processing using fuzzy logic.

일반적으로 퍼지정보처리를 수행하기 위해서는 전류레벨의 퍼지논리치를 래치시키는 래치회로가 필요하게 된다.In general, in order to perform the fuzzy information processing, a latch circuit for latching the fuzzy logic value of the current level is required.

본 고안은 이러한 점을 감안하여 전류레벨의 퍼지논리치를 토글시키는 전류모드형의 퍼지 T형 래치회로를 안출한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention devised a current mode fuzzy T-type latch circuit for toggling the fuzzy logic of the current level in consideration of this point, and will be described in detail with reference to the accompanying drawings.

제1도는 본 고안의 퍼지 T형 래치회로도로서, 이에 도시한 바와같이, 입력단자(IN)를 엔모스트랜지스터(MN1, MN2)로 구성한 엔모스 전류미러(1) 및 엔모스트랜지스터(MN3, MN4)로 구성한 엔모스전류미러(2)를 통해 피모스트랜지스터(MP1, MP2)로 구성한 피모스전류미러(3)의 입력단자에 접속하고, 그 피모스전류미러(3)의 출력단자를 최종 출력단자(IOUT)에 접속하고, 피모스트랜지스터(MP3, MP4)와 엔모스트랜지스터(MN5)로 구성한 전류소스(4)의 출력단자를 제어단자(CTL)가 게이트와 접속된 피모스트랜지스터(MP5)의 소스에 접속하고, 그 피보스트랜지스터(MP5)의 드레인을 상기 엔모스전류미러(1), (2)의 접속점에 접속하여 구성한다.FIG. 1 is a fuzzy T-type latch circuit diagram of the present invention. As shown therein, the NMOS current mirror 1 and the NMOS transistor MN including the input terminal IN as the NMOS transistors MN 1 and MN 2 . 3 , MN 4 ) is connected to the input terminal of the PMOS current mirror 3 composed of the PMOS transistors MP 1 and MP 2 through the NMOS current mirror 2 composed of the PMOS current mirror 3. Is connected to the final output terminal (I OUT ), and the output terminal of the current source (4) constituted by the MOS transistors (MP 3 , MP 4 ) and the ENMOS transistor (MN 5 ) is the control terminal (CT L ). Is connected to the source of the PMOS transistor MP 5 connected to the gate, and the drain of the PMOS transistor MP 5 is connected to the connection points of the NMOS current mirrors 1 and 2.

이와같이 구성한 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured in this way as follows.

제1도에 도시한 바와같이 제어단자(CTL)에 고전위가 입력되면, 이에따라 피모스트랜지스터(MP5)가 턴-오프되므로 전류소스(4)는 동작을 하지 않는다.As shown in FIG. 1, when the high potential is input to the control terminal CTL, the current source 4 does not operate since the PMOS transistor MP 5 is turned off accordingly.

이때 입력단자(IN)에 전류 a가 입력되면 그 전류 a는 엔모스전류미러(1), (2) 및 피모스전류미러(3)를 통해 최종출력단자(IOUT)에서 그대로 출력되어진다.At this time, when a current a is input to the input terminal IN, the current a is output as it is at the final output terminal I OUT through the NMOS current mirrors 1, 2 and PMOS current mirror 3.

반면, 제어단자(CTL)에 저전위가 입력되면, 이에따라 피모스트랜지스터(MP5)가 턴-온되므로 전류소스(4)의 피모스트랜지스터(MP4)가 턴-온된다.On the other hand, when the low potential is input to the control terminal CTL, the PMOS transistor MP 5 is turned on accordingly, so the PMOS transistor MP 4 of the current source 4 is turned on.

따라서 전류소스(4)로부터 전류 "1"이 엔모스전류미러(2)의 입력단자에 입력되므로 엔모스전류미러(2)의 출력단자에는 1-a의 전류가 출력된다.Therefore, since the current "1" is input from the current source 4 to the input terminal of the NMOS current mirror 2, a current of 1-a is output to the output terminal of the NMOS current mirror 2.

이때 이 1-a의 전류는 피모스전류미러(3)를 통해 최종출력단자(IOUT)로 출력되어진다. 이때 피지논리에서=1-a 이므로 최종출력단자(IOUT)에서의 전류가 출력되어진다.At this time, the current of 1-a is output to the final output terminal (I OUT ) through the PMOS current mirror (3). At this time, = 1-a, so at the final output terminal (I OUT ) Current is outputted.

따라서, 상기의 설명을 제2도의 a와 같이 나타낼 수 있다.Therefore, the above description can be expressed as a in FIG.

즉, 제2도의 b와 같은 제어신호가 제어단자(CTL)에 입력되고, 제2도의 b와같이, t1, t2, t3구간에서 a, b' 상승된 b, c' 상승된 c의 전류가 입력단자(IN)를 각기 입력된다고 가정하면, 제2도의 d와 같이 T1구간에서 최종출력단자(IOUT)에는 제어신호가 고전위이면 전류 a가 그대로 출력되고, 저전위로 반전되며 전류 1-a가 출력된다.That is, a control signal such as b of FIG. 2 is input to the control terminal CTL, and as shown in b of FIG. 2 , a, b 'raised b, c' raised c in the interval t 1 , t 2 , t 3 Assuming that the currents of the input terminals IN are respectively inputted, as shown in FIG. 2, when the control signal is the high potential, the current a is output as it is and is inverted to the low potential in the final output terminal I OUT in the period T 1 . Current 1-a is output.

또한 T2 구간에서는 제어신호가 고전위이면 전류 a 보다 b' 만큼 상승된 전류 b가 그대로 출력되고, 반면에 저전위로 반전되면 전류 1-b가 최종출력단자(IOUT)로 출력된다.In addition, in the T2 section, when the control signal is high potential, the current b, which is increased by b ', is output as it is. On the other hand, when inverted to the low potential, current 1-b is output to the final output terminal I OUT .

또한, T3구간에서 제어신호가 고전위이면 전류 a 보다 c'만큼 상승된 c 전류가 그대로 출력되고, 반면에 저전위로 반전되면 전류 1-c가 최종출력단자(IOUT)를 통해 출력된다.In addition, when the control signal is high potential in the T 3 period , the current c increased by c 'is output as it is, whereas when inverted to the low potential, current 1-c is output through the final output terminal I OUT .

이상에서 설명한 바와같이 본 고안은 전류레벨에 피지논리치를 제어신호에 따라 a 또는로 토글시킴으로서 퍼지정보를 처리함에 있어 유용한 효과가 있다.As described above, the present invention has a or By toggling it has a useful effect in processing fuzzy information.

Claims (2)

입력단자(IN)를 엔모스전류미러(1), (2) 및 피모스전류미러(3)를 통해 최종출력단자(IOUT)에 접속하고, 전류소스(4)의 출력측을 피모스트랜지스터(MP5)의 소스에 접속하고, 상기 피모스트랜지스터(MP5)의 게이트에 제어단자(CTL)를 접속한 후 그 피모스트랜지스터(MP5)의 드레인을 상기 엔모스전류미러(1), (2)의 접속점에 접속하여 구성된 것을 특징으로 하는 퍼지 T형 래치회로.The input terminal IN is connected to the final output terminal I OUT through the NMOS current mirrors 1, 2 and PMOS current mirror 3, and the output side of the current source 4 is connected to the PMOS transistor ( connected to the source of MP 5), the PMOS transistor (MP 5) and then connected to a control terminal (CTL) to the gate of the PMOS transistor (MOS current mirror (1), the drain of the MP 5) the yen, and ( A fuzzy T-type latch circuit characterized in that it is connected to the connection point of 2). 제1항에 있어서, 전류소스(4)는 피모스트랜지스터(MP3), (MP4)의 게이트 접속점을 상기 피모스트랜지스터(MP3) 및 엔모스트랜지스터(MN5)의 공통 드레인에 접속하고, 그 접속점을 상기 엔모스트랜지스터(MN5)의 게이트에 접속하여 구성된 것을 특징으로 하는 퍼지 T형 래치회로.The method of claim 1, wherein the current source 4 is connected to the common drain of the PMOS transistor (MP 3), (MP 4) the gate connection point of the PMOS transistor of the (MP 3) and NMOS transistor (MN 5) and And a connection point thereof connected to a gate of the NMOS transistor (MN 5 ).
KR2019910022837U 1991-12-19 1991-12-19 Pusy t-type latch KR940002027Y1 (en)

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KR2019910022837U KR940002027Y1 (en) 1991-12-19 1991-12-19 Pusy t-type latch

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Application Number Priority Date Filing Date Title
KR2019910022837U KR940002027Y1 (en) 1991-12-19 1991-12-19 Pusy t-type latch

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KR930016691U KR930016691U (en) 1993-07-29
KR940002027Y1 true KR940002027Y1 (en) 1994-04-01

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