JPS63251847A - Main storage device - Google Patents

Abstract

PURPOSE:To improve the overall processing capacity of a system by performing the simultaneous reading and writing jobs over two words by an amount equal to the 1-word length when data are transferred over the word boundary between a main memory and a main memory access device and arranging the data on a bus to end the reading and writing jobs while the 1-word data is transferred. CONSTITUTION:The 1-word length data is read out of an address w0 shown by an intra-word selection address bus 30 in an address w1 shown by a word selection address bus 29 by an access request given from a main memory access device 15. Under such conditions, both the data on a submemory covering the w0-th place through the n-th place of a submemory address w1 and the data on the submemory covering the 0-th place through the (w0-1)-th place of a submemory address (w1+1) are read out at one time. Then an intra-word array changing circuit, 19 rearranges those data into the 1-word length data as mw0,..., mn, m0,..., mw0-1. Thus the transfer of data is through in the bus cycle of a single time. Then the bus application rate is halved in terms of a single word for the transfer of data between a main memory 14 and the device 15. As a result, the overall system performance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a main memory, and in particular, the addressing in the main memory is finer than the word unit, and the arrangement of word-length data in the main memory is in the word unit. Concerning main memory that allows boundaries to be crossed.

2. Description of the Related Art Conventionally, in a main memory device that allows the arrangement of l-word length data in the main memory to cross word boundaries, the main memory access device and the connected.

The main memory device l that transfers the word data in the main memory designated by the address bus 3 onto the data bus da is l
Words are addressed by word addresses o-n, but memory access from the main memory access device can only be read and written in word units, and word addresses W,
Address W in word. When accessing l-word length data starting from , submemory address bus t,9
．． All sub-memories r, A, ? accesses address W, of submemory data bus //, /J,
Data m via /3. Reads and writes 1m1-mn. At this time, the intra-word address W. If is other than O, the main memory access device makes a decision and similarly accesses the word at the primary word address vr, +/. The above co-word data is synthesized within the main memory access device and converted into necessary l-word data.

The problem that the invention seeks to solve However, the above-mentioned conventional main storage device.

Even when reading/writing only 7-word length data at an arbitrary address, there is a drawback that if the data is arranged on the main memory across words, it always requires 7 main memory access cycles.

The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks inherent in conventional main memory devices, and improve the processing capacity of the entire system by reducing the bus exclusive time during data transfer between the main memory device and the main memory access device. The object of the present invention is to provide a new main storage device that enables

Means for Solving the Problems In order to achieve the above object, a main storage device according to the present invention includes:
Addressing in the main memory is as detailed as a word, which is the unit of data exchange between the main memory and the main memory access device. In a main memory device that allows reading and writing at the same time in each word address unit, a word selection address generation circuit that generates 7° address data for accessing the submemory, and input/output data of the submemory. and an intra-word placement conversion circuit that converts No. 11 within a word, and when data is transferred across a word boundary between the main memory device and the main memory access device, the word selection address generation circuit simultaneously converts the word placement across λ words. The reading/writing for /word length is performed, and the intra-word arrangement conversion circuit aligns the data on the bus, so that the transfer is completed in one word data transfer time.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 7 is a block diagram showing an embodiment of the present invention.

8g1 In Figure 1, one embodiment of the present invention is a main memory device/l that allows l word length data to be arranged on the main memory across word boundaries, and a main memory access device/l.
(!Connected by near address bus 16 and data bus 17.The main memory device has n+/submemories X
, -/, :, 1, a word selection address generation circuit /g, and an intra-word layout conversion circuit 19. Access to submemories m, 2/, and W is provided by submemory address buses nl and co, respectively. and submemory data busco 4.27
．． independently accessed by H and each accessed data value. 1m.

...1mn. Word selection address generation circuit/g
is the word selection address W in the address bus /6, and the word selection address bus 9 and the word selection address W in the word
The sub-memory address is input to the intra-word selection address bus 30 indicating W1 and Wo, and the sub-memory address is set on the sub-memory address bus 23.0 according to the operation table of FIG.
Kohiro, generates on Ko5.

The intra-word placement conversion circuit/de selects the intra-word selection address W.
. As an input to the in-word selection address bus 30 indicating
Data m on the data bus 17 and submemory data buses CO, CO, CO according to the operation table shown in FIG. .

Convert the correspondence with ml # mn.

The main memory device /II is connected to the address bus /6 as in the conventional system.
is connected to the main memory access device [/& by the data bus /7, but in response to an access request from the main memory access device IS, the word selection address bus 30 in the vrIe field, indicated by the word selection address bus 2q, is connected to the main memory access device [/&]. W. #li
When reading l-word length data from the sub-memory address W. The data of the submemory from the n@th submemory and the data of the submemory from the 0th to Wg−/th of the submemory address W1 + / are sequentially outputted at the same time, and the intra-word arrangement conversion circuit 19 converts the data to −, “・1mn
* mar "'1 The data is rearranged into /word length data of mwO-1, and the data transfer is completed in one bus cycle.

The same applies to writing, but the intra-word placement conversion circuit 1
9 is an operation opposite to reading.

In this embodiment, when the data transfer between the main memory device and the main memory access device is performed for one word, the bus usage rate is halved, and it is possible to prevent the main memory access device from deteriorating its processing capacity due to the bus free waiting time. can.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by eliminating unnecessary memory accesses within the main storage device and effectively using bus cycles, it is possible to improve bus performance and, by extension, the performance of the entire system. .

According to the present invention, there is no difference in performance compared to conventional methods that use software to reduce memory usage efficiency and intentionally place data on word boundaries to improve performance. The effect of this can be obtained.

[Brief explanation of the drawing]

@Figure 1 is a block configuration diagram showing an embodiment of the main memory device according to the present invention, Figure 1 is the operation of the word selection address generation circuit shown in Figure 1, and Figure 3 is the same as shown in Figure 7. FIG. q of the operation table of the intra-word rearrangement conversion circuit is a block diagram showing the structure of a conventional main memory device. /, /'I... Main memory It, ko, /! ...main memory access device, 3. /A...address bus, 4(,
/? ...f-11 bus, j, A, ? , a,
2/, 22... sub memory, g. De, 10.23.2: I, , 25...Sub memory address bus. //, /ko, 13. -7,2g...Sub memory data bus.

Claims (1)

[Claims] Addressing within the main memory is finer than the word unit, which is the unit of data exchange between the main memory and the main memory access device, and allows the arrangement of 1-word length data in main memory to straddle word boundaries. In the storage device, a submemory that can be read and written simultaneously in each word address unit;
The main storage device includes a word selection address generation circuit that generates address data for accessing the submemory, and an intraword arrangement conversion circuit that converts the order of input/output data of the submemory within a word. When transferring data across word boundaries with the main memory access device, the word selection address generation circuit simultaneously reads/writes one word length over two words, and the intra-word arrangement conversion circuit converts the data on the bus. A main memory device characterized in that by aligning the data, the transfer can be completed in one word of data transfer time.