JPS63250176A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain sufficient formation of a metallic wiring even in an opening part on a source/drain region, by forming an opening part to provide continuity in a source or a drain and making a dimension of this opening part larger than that of an opening part which is formed to provide continuity in a gate. CONSTITUTION:In order to draw wirings from a source or drain region 102 and a gate 101, opening parts are formed on layer insulation films 104 which are formed on them respectively. Thereupon, a dimension of an opening part 107 on the source/drain region is made larger than that of an opening part 108 on the gate. when metallic wirings 105 are formed in succession, an aspect ratio in the opening part 107 on the source/drain region is also obtained identically with that in the opening part 108 on the gate so that the formations of the metallic wirings are obtained approximately in the same degrees in both parts. Sufficient formations of the metallic wirings 105 can be thus obtained, and so disconnections of the metallic wirings 105 can be significantly decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of an opening formed in an insulating crotch of a semiconductor device.

[Summary of the invention]

The present invention provides MO3yJ! ,) In a semiconductor device consisting of a run sister, the dimensions of the open part formed on the insulating film to establish conduction to the source and drain are larger than the dimensions of the open part formed to establish conduction to the gate. As a result, the throwing power in the opening portion of the metal wired to the source and drain becomes the same as the throwing power in the tti1 hole portion of the metal wired to the gate,
This is intended to reduce disconnection of metal wires connected to the source and drain.

[Conventional technology]

As shown in FIGS. 2(a) and 2(b), the structure of the opening formed in the insulating crotch of a conventional semiconductor device is such that the dimensions of the opening are large, both above the source and drain, and above the gate. It was the same.

[Problems that the invention attempts to solve]

However, in the above-mentioned conventional technology, when planarization is performed using an etch-back method, a bias sputtering method, a silica coating method, etc., the thickness of the interlayer insulating film 104 formed on the source and drain regions 102 is Since the thickness of the interlayer insulating film 104 formed on the gate 201 is considerably thicker than that of the interlayer insulating film 104 formed on the gate 201, the ratio of the thickness of the interlayer insulating film to the width of the opening (hereinafter abbreviated as aspect ratio) is Compared to the above case, the source/drain f11' [area 102
When the metal wiring 205 is formed, the coverage of the metal wiring 205 at the opening portion 207 above the source/drain region deteriorates, which may lead to disconnection.

Therefore, the present invention aims to solve such problems, and the main feature of the present invention is that even in the opening part 207 of the source/drain region, the opening part 208 of the gate part and the opening part 208 of the gate part are The purpose is to obtain similar coverage of the metal wiring 205.

[Failure to solve the problem]

In the semiconductor device of the present invention, in an IC formed by MO8 type transistors, the dimensions of the opening formed on the insulating film to establish conduction to the source or drain are such that the dimensions are such that the dimensions of the opening are such that the dimensions are such that the dimensions of the opening formed to establish conduction to the gate are It is characterized by being larger than the size of the cleaved portion to be formed.

[Example] FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view of an example of the present invention, and below, according to the steps,
I'll explain. LOCO3103 on semiconductor substrate 10G,
After forming the gate 101 and source/drain regions, an interlayer insulating film 104 is formed. At this time, interlayer insulating film 1
04 consists of an S r Ox film and a silica coating film produced by the vapor phase growth method (hereinafter abbreviated as CV 1), but the V: thickness of one 5iO layer produced by CVI) is uniformly 0 on the semiconductor substrate surface.
．． 47j 171, whereas the silica coating film has a thickness of 0.27zm on the source/drain region 102.
On the other hand, it is 0.1 μm above the gate 101, which means that it is flattened. After all, living room insulation'
The film U serving as the crotch is 0.6 μm 1 on the source/drain region 102 and 0.5 μm 1 on the source/drain region 101 .

Next, source/drain region 102 and gate 101
In order to draw out the wiring further, openings are formed in the interlayer insulating film 104 formed on each layer. At this time, the dimension of the opening part 107 on the source/drain region is 1.2 μm, and the dimension of the opening part 108 on the gate is 1.0 μm.
It is set to μm.

That is, the aspect ratio of the opening portion 107 above the source/drain region is O.Gμm/1. '2μm=0.5
, 0°5μm/1.0μ in the opening part 108 on the gate
m=0.5, and both are equal. Next, a metal arrangement 11105 is formed, and since the [tn hole portion 107 on the source/drain region also has the same aspect ratio as the open portion 108 on the gate, the metal wiring 105 is The running power is approximately the same for both, and sufficient running power can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the dimensions of the opening portion 107 on the source/drain region are adjusted to the dimensions of the opening portion 107 on the gate.
By making the dimension larger than 08, the metal wiring 10 can also be formed in the open portion 107 on the source-drain region.
No. 5 has sufficient coverage, and the occurrence of disconnection of the metal wiring 105 in this portion is extremely reduced (as a result, a semiconductor device with high yield and high reliability can be obtained).

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view (a) and a cross-sectional view (b) showing a semiconductor device of the present invention. FIGS. 2(a) and 2(b) are a plan view (a) and a cross-sectional view (b) showing a conventional semiconductor device. 10i201...Gate 102.202...Source/drain region 103.2
03...LOCO3 104,204...Interlayer insulating film 105.205...Metal wiring 106.206...Semiconductor J model 107.207...Source-drain region"2 opening portion 108. 208... Above the opening on the gate Applicant Seiko Epson Co., Ltd. 1st item (＾2 2nd item (α2 fO7゜yu06 ￥2nd item)

Claims (1)

[Claims] In a semiconductor device constituted by a MOS transistor, the dimensions of the opening formed on the insulating film to establish conduction to the source or drain are larger than the dimensions of the opening formed to establish conduction to the gate. A semiconductor device characterized by its large size.