JPH02116123A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02116123A JPH02116123A JP26975288A JP26975288A JPH02116123A JP H02116123 A JPH02116123 A JP H02116123A JP 26975288 A JP26975288 A JP 26975288A JP 26975288 A JP26975288 A JP 26975288A JP H02116123 A JPH02116123 A JP H02116123A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- thin film
- forming
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 239000010936 titanium Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 1
- 238000005979 thermal decomposition reaction Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000001556 precipitation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、半導体基板と配線金
属とのコンタクトの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to a contact structure between a semiconductor substrate and a wiring metal.
従来、半導体装置における半導体基板（Ｓｉ）と配線金
属（ＡＱ）とのコンタクト構造は、熱処理時において基
板中のＳｉがＡＱ中に拡散することによりＡＱがＡｉ基
板中に異常拡散するアロイスパイクと呼ばれる不良を防
ぐため、ＡＱ中に１％程度Ｓｉを予め混合させたスパッ
タターゲットを用いでにＤＣマグネトロンスパッタ法に
よりＳｉ基板表面に配線金属をスパッタする方法や、Ｓ
ｉ基板表面にＣＶＤ法により多結晶Ｓｉ薄膜を成長させ
、さらにその上に純粋のＡＱをスパッタする方法等があ
る。さらには、バリアメタルとしてチタン等の膜をＡＱ
と基板シリコンとの間にはさむ方法もある。Conventionally, the contact structure between a semiconductor substrate (Si) and wiring metal (AQ) in a semiconductor device is called an alloy spike, in which Si in the substrate diffuses into AQ during heat treatment, and AQ abnormally diffuses into the Ai substrate. In order to prevent defects, there is a method in which wiring metal is sputtered onto the surface of the Si substrate by DC magnetron sputtering using a sputtering target in which about 1% Si is pre-mixed in AQ.
There is a method of growing a polycrystalline Si thin film on the surface of an i-substrate by CVD and then sputtering pure AQ thereon. Furthermore, AQ films such as titanium are used as barrier metals.
There is also a method of sandwiching it between the substrate and the silicon substrate.
上述したように従来の予めＳｉを過剰にいれる構造では
、アロイスパイクの防止には効果があるものの、近年半
導体集積回路装置の高集積化に伴うコンタクト孔の微細
化のために、Ｓｉノジュールと呼ばれるＳＬの析出によ
ってコンタクト孔がふさがれてしまう不良モードが発生
している。また、Ｔｉのバリアメタルは、ＡＱとの反応
でＴｉＡ（１３ができると、７０イスパイクが生じる（
例えば、ＡｐｐｌｉｅｄＰｈｙｓｉｃｓ Ｌｅｔｔｅｒ
ｓ ｖｏｌ、２３． ＮＯ，２，１５Ｊｕｌｙ １９７
３゜ρ、９９）。As mentioned above, the conventional structure in which Si is added excessively in advance is effective in preventing alloy spikes, but due to the miniaturization of contact holes in recent years as semiconductor integrated circuit devices become more highly integrated, A failure mode occurs in which the contact hole is blocked by SL precipitation. In addition, when Ti barrier metal reacts with AQ, TiA (13 is formed, 70 ispike is generated (
For example, Applied Physics Letter
s vol, 23. NO, 2, 15July 197
3゜ρ, 99).
本発明の目的は前記課題を解決した半導体装置を提供す
ることにある。An object of the present invention is to provide a semiconductor device that solves the above problems.
上記目的を達成するため、本発明に係る半導体装置にお
いては、一導電型半導体基板の一主面に絶縁膜のコンタ
クト開口部が形成され、該開口部を含む前記基板一主面
の絶縁膜上に形成された配線用金属膜と前記基板との間
に半導体薄膜及びチタン薄膜の積層膜を介装したもので
ある。In order to achieve the above object, in a semiconductor device according to the present invention, a contact opening of an insulating film is formed on one main surface of a semiconductor substrate of one conductivity type, and a contact opening of an insulating film on one main surface of the substrate including the opening is formed. A laminated film of a semiconductor thin film and a titanium thin film is interposed between the wiring metal film formed on the substrate and the substrate.
本発明の半導体装置は、Ｓｉ基板表面にＣＶＤ法により
多結晶Ｓｉ薄膜を成長させ、さらにその上に純粋のＡＱ
をスパッタする前にＴｉ等の高融点金属薄膜をスパッタ
することにより、多結晶Ｓｉ、 Ｔｉ、 Ａ（１のサン
ドイッチ構造を形成したものである。In the semiconductor device of the present invention, a polycrystalline Si thin film is grown on the surface of a Si substrate by the CVD method, and pure AQ
A sandwich structure of polycrystalline Si, Ti, and A(1) was formed by sputtering a thin film of a high-melting point metal such as Ti before sputtering.
本発明の構造により、ＴｉはＳｉのＡＱへの拡散を抑制
する効果（例えば、Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ
Ｌｅｔｔｅｒｓｖｏｌ、２８． ＮＯ，５，Ｉ Ｍａｒ
ｃｈ １９７６） 、 ＳｉはＴｉの拡散を抑制する効
果（例えば、Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ Ｌｅｔ
ｔｅｒｓ。Due to the structure of the present invention, Ti has the effect of suppressing the diffusion of Si into AQ (for example, Applied Physics
Lettersvol, 28. NO, 5, I Mar
ch 1976), Si has the effect of suppressing the diffusion of Ti (for example, Applied Physics Let
ters.
５０（３）、 １９ Ｊａｎｕａｒｙ １９８７． ｐ
、１３０）を利用して、基板Ｓｉが外方拡散するのを防
ぎ、Ｔｉ又はＡＱによるアロイスパイクを防ぎ、Ｓｉ析
出によるコンタクトの不良を防ぐことができる。50(3), 19 January 1987. p
, 130) can be used to prevent outward diffusion of the substrate Si, prevent alloy spikes due to Ti or AQ, and prevent contact failure due to Si precipitation.
次に本発明を図面を用いて説明する。 Next, the present invention will be explained using the drawings.
（実施例１）
第１図（ａ）〜（ｄ）は本発明の実施例１であるｎチャ
ネルＭｏＳトランジスタの製造工程の断面図を示す。(Example 1) FIGS. 1(a) to 1(d) show cross-sectional views of the manufacturing process of an n-channel MoS transistor, which is Example 1 of the present invention.
第１図（ａ）に示すように、ｐ型シリコン基板１の表面
を選択的にＬＯＣＯ５酸化膜２ （Ｌｏｃａｌ ０ｘｉ
ｄａｔｉｏｎｏｆ ５ｉｌｉｃｏｎ）を形成し、マスク
となったシリコン窒化膜を除去しく図示せず）、ゲート
酸化膜を約３００人形成し、ゲートポリシリコンを６０
００人、低圧ＣＶＤ（化学気相成長）によりシランガス
を熱分解して成長させ、９００℃において、リンを拡散
した（図示せず）のち、フォトリングラフィにより、パ
ターニングして、フォトレジストをマスクにＣＦ４＋
Ｏ□ガスを用いて反応性イオンエツチングしゲート電極
３を形成する。As shown in FIG. 1(a), the surface of the p-type silicon substrate 1 is selectively coated with a LOCO5 oxide film 2 (Local Oxide film 2).
The silicon nitride film used as a mask was removed (not shown), a gate oxide film was formed by about 300 layers, and gate polysilicon was deposited by about 60 layers.
00 people, grown by thermally decomposing silane gas by low-pressure CVD (chemical vapor deposition), diffusing phosphorus at 900°C (not shown), patterning by photolithography, and using photoresist as a mask. CF4+
A gate electrode 3 is formed by reactive ion etching using O□ gas.
さらに、フォトリソグラフィにより、レジスト及びゲー
トポリシリコンをマスクに７０Ｋ ｅ Ｖのエネルギー
でＡｓをｌ Ｘ １０” （ｃｍ−１）イオン注入し、
ソース、ｎ型ドレイン拡散層４を形成する。次に、４０
０℃において常圧ＣＶＤ法により、４モル％濃度のＣＶ
Ｄ酸化膜（リンガラス層）５を約１ミクロン形成する。Furthermore, As was ion-implanted by photolithography at an energy of 70 K e V using the resist and gate polysilicon as masks to a depth of 1×10” (cm−1).
Source and n-type drain diffusion layers 4 are formed. Next, 40
CVD with a concentration of 4 mol% was carried out at 0°C by atmospheric pressure CVD method.
A D oxide film (phosphorus glass layer) 5 is formed to a thickness of about 1 micron.
フォトリソグラフィにより、コンタクト孔６をフォトレ
ジストをマスクにＣＦ、とＨ２の混合ガスを用いて反応
性イオンエツチングにより開口する。By photolithography, contact holes 6 are opened by reactive ion etching using a mixed gas of CF and H2 using a photoresist as a mask.
第１図（ｂ）に示すように基板表面に低圧ＣＶＤ法によ
り、厚さ２００人の多結晶シリコン膜７を６００℃で形
成する。ここで、多結晶シリコン膜７の代りに。As shown in FIG. 1(b), a polycrystalline silicon film 7 having a thickness of 200 nm is formed at 600° C. on the surface of the substrate by low pressure CVD. Here, instead of the polycrystalline silicon film 7.
ＤＣマグネトロンスパッタにより、シリコンターゲット
をアルゴンガスでスパッタし、厚さ２００人のアモルフ
ァスシリコン膜を室温で形成してもよい。An amorphous silicon film with a thickness of 200 nm may be formed at room temperature by sputtering a silicon target with argon gas by DC magnetron sputtering.
さらに、前記シリコン膜７上にＴｉ薄膜８をＤＣマグネ
トロンスパッタにより、厚さ２００人形成する。Furthermore, a Ti thin film 8 with a thickness of 200 mm is formed on the silicon film 7 by DC magnetron sputtering.
さらに同一スパッタ装置内において、Ｔｉ薄膜８上に連
続的にアルミニウム膜９を１ミクロン、ＤＣマグネトロ
ンスパッタで形成する（第１図（ｃ））−次に、フォト
リングラフィ技術によりアルミニウム膜９（配線）をパ
ターニングし、ＣＣＱ４ガスを用いて反応性イオンエツ
チングにより、電極配線１ｏを形成する（第１図）、な
お、パターニング後、シリコン基板と配線金属とのコン
タクトをとるため、４５０℃。Furthermore, in the same sputtering apparatus, an aluminum film 9 of 1 micron thickness is continuously formed on the Ti thin film 8 by DC magnetron sputtering (FIG. 1(c)).Next, the aluminum film 9 (wiring ) is patterned, and electrode wiring 1o is formed by reactive ion etching using CCQ4 gas (Fig. 1). After patterning, the temperature is 450°C in order to make contact between the silicon substrate and the wiring metal.
３０分間のリンタリングを行っている。Lintering is done for 30 minutes.
（実施例２）
第２図（ａ）〜（ｄ）は本発明の実施例２であるｐチャ
ネルＭＯＳトランジスタの製造工程断面図を示す。(Embodiment 2) FIGS. 2(a) to 2(d) show cross-sectional views of the manufacturing process of a p-channel MOS transistor which is Embodiment 2 of the present invention.
第２図（ａ）に示すように、ｎ型シリコン基板１１の表
面を選択的にＬＯＣＯ５酸化膜１２（Ｌｏｃａｌ ０ｘ
ｉｄａｔｉｏｎ ｏｆＳｉｌｉｃｏｎ）を形成し、マス
クとなったシリコン窒化膜を除去しく図示せず）、ゲー
ト酸化膜を約３００人形成し、ゲートポリシリコンを６
０００人、６００℃ノ低圧ＣＶＤ （化学気相成長）に
より成長させ、９００℃においてリンを拡散したのち、
フォトリソグラフィによりパターニングして、フォトレ
ジストをマスクにドライエツチングし、ゲート電極１３
を形成する。As shown in FIG. 2(a), the surface of the n-type silicon substrate 11 is selectively coated with a LOCO5 oxide film 12 (Local 0x
The silicon nitride film that served as a mask was removed (not shown), a gate oxide film was formed by about 300 layers, and the gate polysilicon was
000 people, grown by low pressure CVD (chemical vapor deposition) at 600℃, and after diffusing phosphorus at 900℃,
The gate electrode 13 is patterned by photolithography and dry etched using the photoresist as a mask.
form.
さらに、フォトリングラフィにより、レジスト及びゲー
トポリシリコンをマスクにＩＯＫ ｅ Ｖのエネルギー
でＢＦ２をｌＸｌ０”（Ｃ１１−’）イオン注入し、ソ
ース、ｐ型ドレイン拡散層１４を形成する。Furthermore, by photolithography, BF2 is ion-implanted using resist and gate polysilicon as a mask with an energy of IOK e V to form source and p-type drain diffusion layers 14.
次に、４００℃において常圧ＣＶＤ法により、４モル％
濃度のＣＶＤ酸化膜（リンガラス層）１５を約１ミクロ
ン形成する。フォトリソグラフィにより、コンタクト孔
１６をフォトレジストをマスクにドライエツチングし開
口する。基板表面にＤＣマグネトロンスパッタリングに
より、Ｔｉ（チタン）薄膜１７を厚さ２００人の室温で
形成する。同一スパッタ装置内においてＳｉターゲット
をアルゴンガスでスパッタしアモルファスＳｉ薄膜１８
を厚さ２００人室温で形成し。Next, 4 mol%
A CVD oxide film (phosphorus glass layer) 15 with a density of about 1 micron is formed. By photolithography, contact holes 16 are opened by dry etching using a photoresist as a mask. A Ti (titanium) thin film 17 with a thickness of 200 mm is formed on the surface of the substrate by DC magnetron sputtering at room temperature. In the same sputtering device, a Si target is sputtered with argon gas to form an amorphous Si thin film 18.
Formed to a thickness of 200 people at room temperature.
続けてアルミニウム膜１９を１ミクロン、ＤＣマグネト
ロンスパッタで形成する（第２図（ｃ） ）、フォトリ
ングラフィにより、アルミニウム膜（配線）１９をパタ
ーニングし、続いてレジストをマスクにドライエッチを
行い、電極配線２０を形成する（第２図（ｄ） ）。Subsequently, an aluminum film 19 of 1 micron thickness is formed by DC magnetron sputtering (FIG. 2(c)), the aluminum film (wiring) 19 is patterned by photolithography, and then dry etching is performed using a resist as a mask. Electrode wiring 20 is formed (FIG. 2(d)).
なお、バターニング後、シリコン基板と配線金属とのコ
ンタクトをとるため、４５０℃、３０分間のリングリン
グを行っている。After buttering, ringing was performed at 450° C. for 30 minutes in order to establish contact between the silicon substrate and the wiring metal.
以上説明したように１本発明は近年の半導体装置の高集
積化に伴うコンタクト孔の微細化のために、ＳＬノジュ
ールとよばれるＳＬの析出によってコンタクト孔がふさ
がれてしまう不良モードに対し、半導体基板一主面上の
絶縁膜に開口部を形成したあと、多結晶又は非晶質半導
体薄膜及びチタン薄膜アルミニウム膜の積層膜を前記開
口部を含む絶縁膜上に形成することにより、ＴｉはＳＬ
の八〇への拡散を抑制し、 ＳｉはＴｉの拡散を抑制す
る効果を利用して、基板Ｓｉが外方拡散するのを防ぎ、
Ｔｉｓ ＡＱによるアロイスパイクを防ぎ、Ｓｉ析出に
よるコンタクトの不良を防ぐことができ、半導体集積回
路の製造における歩留り改善に著しい効果がある。As explained above, one aspect of the present invention is to prevent a failure mode in which contact holes are blocked by precipitation of SL called SL nodules due to the miniaturization of contact holes accompanying the recent increase in the degree of integration of semiconductor devices. After forming an opening in the insulating film on one main surface of the substrate, a laminated film of a polycrystalline or amorphous semiconductor thin film and a titanium thin film and an aluminum film is formed on the insulating film including the opening.
By using the effect of suppressing the diffusion of Ti, Si prevents the substrate Si from diffusing outward.
It is possible to prevent alloy spikes caused by Tis AQ and contact defects caused by Si precipitation, and has a significant effect on improving yields in the production of semiconductor integrated circuits.
第１図（ａ）〜（（１）は本発明の実施例１であるｎチ
ャネルＭＯＳトランジスタの製造工程断面図、第２図（
ａ）〜（ｄ）は本発明の実施例２であるｐチャネルＭＯ
Ｓトランジスタの製造工程断面図である。
１・・・ｐ型シリコン基板 ２，１２・・・ＬＯＣＯ５
酸化膜３．１３・・・ゲート電極 ４・・・ｎ型ド
レイン拡散層５・・・ＣＶＯ（ａ化）膜 ６，１６
・・・コンタクト孔７・・・多結晶シリコン膜 ８・・
・Ｔｉ薄膜９．１９・・・アルミニウム１ｉ１１１・・
・ｎ型シリコン基板１４・・・ｐ型ドレイン拡散層1(a) to (1) are cross-sectional views of the manufacturing process of an n-channel MOS transistor according to the first embodiment of the present invention, and FIG.
a) to (d) are p-channel MOs which are Example 2 of the present invention.
FIG. 3 is a cross-sectional view of the manufacturing process of the S transistor. 1...p-type silicon substrate 2, 12...LOCO5
Oxide film 3.13...Gate electrode 4...N-type drain diffusion layer 5...CVO (a) film 6,16
...Contact hole 7...Polycrystalline silicon film 8...
・Ti thin film 9.19...Aluminum 1i111...
・N-type silicon substrate 14...p-type drain diffusion layer
Claims (1)
ト開口部が形成され、該開口部を含む前記基板一主面の
絶縁膜上に形成された配線用金属膜と前記基板との間に
半導体薄膜及びチタン薄膜の積層膜を介装したことを特
徴とする半導体装置。(1) A contact opening in an insulating film is formed on one main surface of a semiconductor substrate of one conductivity type, and a wiring metal film formed on an insulating film on one main surface of the substrate including the opening is connected to the substrate. A semiconductor device characterized in that a laminated film of a semiconductor thin film and a titanium thin film is interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26975288A JPH02116123A (en) | 1988-10-25 | 1988-10-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26975288A JPH02116123A (en) | 1988-10-25 | 1988-10-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02116123A true JPH02116123A (en) | 1990-04-27 |
Family
ID=17476662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26975288A Pending JPH02116123A (en) | 1988-10-25 | 1988-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02116123A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0476429A (en) * | 1990-07-18 | 1992-03-11 | Mitsubishi Electric Corp | Semiconductor pressure sensor |
| JPH07161813A (en) * | 1993-12-08 | 1995-06-23 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-10-25 JP JP26975288A patent/JPH02116123A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0476429A (en) * | 1990-07-18 | 1992-03-11 | Mitsubishi Electric Corp | Semiconductor pressure sensor |
| JPH07161813A (en) * | 1993-12-08 | 1995-06-23 | Nec Corp | Manufacture of semiconductor device |
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