JPS63246830A - Passivation for super lsi - Google Patents

Passivation for super lsi

Info

Publication number
JPS63246830A
JPS63246830A JP7962887A JP7962887A JPS63246830A JP S63246830 A JPS63246830 A JP S63246830A JP 7962887 A JP7962887 A JP 7962887A JP 7962887 A JP7962887 A JP 7962887A JP S63246830 A JPS63246830 A JP S63246830A
Authority
JP
Japan
Prior art keywords
grain boundary
film
crystalline
passivation
potential barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7962887A
Other languages
Japanese (ja)
Inventor
Keiji Kobayashi
啓二 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7962887A priority Critical patent/JPS63246830A/en
Publication of JPS63246830A publication Critical patent/JPS63246830A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To improve the blocking effect of impurity ions and humidity resistance and to enhance reliability, by using two or more layers for passivation films, diffusing ions in another layer of an amorphous film into the grain boundary of one layer of a crystalline film of said two layers, and enhancing the potential barrier of the grain boundary. CONSTITUTION:An amorphous thin film 1 and a crystalline thin film 3 are provided at adjacent positions. As the crystalline thin film 3, an insulating film, which has a grain boundary comprising polysilicon, SiO2, SiN and other oxide and fluoride and the like, is used. As the amorphous film 1, As doped phospho-silicate glass is used. As a crystalline film 2, silicon nitride film 2 is used. Both thin films are bonded and then undergo heat treatment at 500 deg.C for 15 minutes. Thus As is diffused into the grain boundary 2. As a result, the potential barrier of the grain boundary 2 after the As diffusion can be improved to about 0.75 eV in comparison with the low potential barrier of 0.2 eV in the grain boundary of ordinary silicon nitride. Since the movement of impurity ions in the crystal grain boundary 2 is suppressed in this way, the characteristics of a semiconductor element at high temperature and high humidity can be enhanced by about two-three times, thereby the passivation for a highly reliable super LSI can be obtained.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分gf) この発明はブロッキング効果が大き(て耐湿性)高いg
 +i a 性の、[1,Sl用パッシベーションに関
するものである。
[Detailed description of the invention] [Object of the invention] (Industrial use gf) This invention has a high blocking effect (and moisture resistance).
This relates to passivation for [1,Sl] with +ia characteristics.

(従来の技術) 従来技術では、LSIやその池の半導体チップのIsと
してP2O(りん酸シリカ系ガラス)が用いられて米た
。これは抵抗が高くて耐アルカリ性などには比較的好椿
性を示すが、耐湿性、長期ffi頌性、不純物抑制効果
、パックベーションのクラックなどに問題があった。
(Prior Art) In the prior art, P2O (phosphoric acid silica glass) has been used as the Is of LSI and other semiconductor chips. This has high resistance and is relatively good in terms of alkali resistance, etc., but it has problems with moisture resistance, long-term ffi resistance, impurity suppression effect, cracks in packvation, etc.

(発明が解決しようとする問題点) 本発明はこのような欠点を解決するためic研究がなさ
れたものであり、その目的とするところはパッシベーシ
ョン@L−211以上のものにしてかつそのうちの一層
の結晶質嘆の粒界に池の一層の非晶質膜中のイオンを拡
散させて粒界のポテンシャルバリアーを高め不純物イオ
ンのブロッキング効果、耐湿性の向上などとはかりチッ
プの信碩性r高めようとするものである。
(Problems to be Solved by the Invention) The present invention is the result of IC research conducted in order to solve these drawbacks, and its purpose is to improve passivation @L-211 or higher, and to improve The ions in the amorphous film are diffused into the crystalline grain boundaries, increasing the potential barrier of the grain boundaries, blocking impurity ions, improving moisture resistance, and increasing the reliability of the weighing chip. This is what we are trying to do.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 本発明は−f偵または複aSSの結晶質「−を−・−ま
たは複数層の非晶質1−とが隣接して成る[j模でかつ
結晶質の粒界に非晶質層からのイオン全拡散熱処理、そ
の池の方去で導入して粒界のポテンシャル障壁を高める
ことによりて模のブロッキング効果を高めたこと金時徴
とするものである。
(Means for Solving the Problems) The present invention provides a structure in which crystalline or multiple aSS crystalline ``-'' or multiple layers of amorphous 1- are adjacent to each other. It is a sign that the blocking effect of the grain is enhanced by increasing the potential barrier of the grain boundary by introducing heat treatment for total diffusion of ions from the amorphous layer into the grain boundary and removing the pond. .

(作用) 前記のように粒界のポテンシャル障りr高めておくこと
によって結晶粒界での不純物イオンの移1助が抑制され
るため、半導体素子の高温高湿の特性を2〜3倍程度高
めることが可能となりた。
(Function) As mentioned above, by increasing the grain boundary potential, the transfer of impurity ions at the grain boundaries is suppressed, thereby increasing the high temperature and high humidity characteristics of semiconductor elements by about 2 to 3 times. It became possible.

(実施例1) @1図に示したような非晶質薄@(ガラス)1と結晶質
i1僕3とを隣接させる。結晶1R薄模3にはポリシリ
コン、8i0.、 SiN、その他の酸化物弗化物等の
粒界をもつ絶縁;庚を用いる。ガラス1はAs、Sb、
B、P、Fなど拡散性のイオン?含むガラX4薄1vX
を用いる。ガラスからの′6.界へD拡牧2は電界、熱
処理、イオン注入Wk組片せてもよい。
(Example 1) An amorphous thin (glass) 1 and a crystalline i1 as shown in FIG. 1 are placed adjacent to each other. The crystal 1R thin pattern 3 is made of polysilicon, 8i0. Insulation with grain boundaries such as SiN, other oxides, fluorides, etc. is used. Glass 1 is As, Sb,
Diffusible ions such as B, P, and F? Contains Gala X4 Thin 1vX
Use. '6 from glass. The D expansion 2 to the field may be performed using an electric field, heat treatment, or ion implantation Wk assembly.

非晶質)漢1にAsドープりん酸シリカ系ガラスを用い
、結晶質臭2として窒化/リコン模r用いた0両者゛O
i#模を接合した後に550℃15分熱処理を行りて粒
界にAs茫拡政2させた。この結果通常の窒化シリコン
の粒界のポテンシャルバリアーidO,2eVと低いの
に対し1本発明vcgけるAs弘牧麦の粒界のポテンシ
ャルバリアーは0.75eVI度まで向上させることが
出来た。
Amorphous) As-doped phosphoric acid silica glass was used for the glass 1, and nitrided/reconstituted glass was used for the crystalline odor 2.
After bonding the i# pattern, heat treatment was performed at 550° C. for 15 minutes to cause As expansion at the grain boundaries. As a result, while the grain boundary potential barrier idO of ordinary silicon nitride is as low as 2 eV, the grain boundary potential barrier of As Hiromaki barley according to the present invention could be improved to 0.75 eVI degree.

なおこのパッシベーション[kiUいてS t (10
0)/S t Os (500A )/バクシベーシ、
:/ 膜(+、5μm)/A!電極のMOSキャパシタ
ーと用いてC−V時(iji1MH1常温で評価したと
ころ第2図曲IJAに示すようになり、侍に異常はなか
った。
Note that this passivation [kiUteS t (10
0)/S t Os (500A)/Bakshibasi,
:/ Membrane (+, 5μm)/A! Using a MOS capacitor as an electrode, evaluation was made at room temperature during CV (iji1MH1), as shown in Figure 2, song IJA, and no abnormality was found in the Samurai.

(=J!施eAJ2) ガラスとしてSiO,(97%)−〇em、(3%)4
喚1を用い、結晶賀漠3としてpoly−8i((用い
+ この粒界にBF、にイオン主人法(I X 10” c
m”5 Q K e V )で拡散させた。この結晶質
模(1μm)にガラス’i(0,5μ+11)kスパッ
ター法でつけパツシベーシヨン膜とした。この粒界のボ
テンンヤルバリアーは0.42eVでありた。またこの
パツシベーシヨン膜を用いて5t(100)/5inl
(りoo  。
(=J!useAJ2) SiO as glass, (97%)-〇em, (3%)4
Poly-8i ((using + BF at this grain boundary, ion main law (I x 10" c
m"5 Q K e V ). This crystalline model (1 μm) was coated with a glass 'i (0,5 μ + 11) k sputtering method to form a passivation film. The bottom layer of this grain boundary was 0. 42 eV. Also, using this passivation film, 5t(100)/5inl
(Rioo.

A)/パlバ、イベーション嘆/AJ心極の積1−構造
のMO8キ皐パシターのC−V特性と1MHz常温で評
価したところ第2図曲線BIC示すように正常なカーブ
を示していた。又このバッフベージ(ン模の比抵抗も西
宮のP SG@よりも高いl×1016Ωcm以上の値
が得られた。
A)/Palva, evolution/AJ core product product 1-When the CV characteristics of the MO8-kiopasitor with the structure were evaluated at 1MHz at room temperature, it showed a normal curve as shown in Figure 2, curve BIC. . Moreover, the resistivity of this buff base model was higher than that of Nishinomiya's PSG@, which was 1×10 16 Ωcm or more.

(実、m例3 ) ガラスとしてBPSG4@1 (りん酸シリカホロシ系
)を用い、7晧晶質模3とし″CB拡牧拡散n、嘆を用
いた。Bはイオン注入法で(I X 10”cm” t
60KeV)導入した。この両者つτsi漢と隣接させ
ガラス伝移点以下の@度でυ口熱し、アニールした。
(Actual Example 3) BPSG4@1 (phosphoric acid silica holographic system) was used as the glass, and "CB expansion diffusion" was used as the 7-crystalline model 3. "cm" t
60KeV) was introduced. These two were placed adjacent to each other and annealed by heating at a temperature below the glass transition point.

この粒界のポテンシャルバリアーは0.35eVであり
た。またこのパッシベーション@七用いて51(100
)/S簾01(500A)/パッシベーション/Al′
α甑7)積層構造のMOSキャパシタ一つC−V特性を
IM)(z常温で測定したところ第2図曲線Cで示すよ
うに正常なカーブを示していた。
The potential barrier of this grain boundary was 0.35 eV. Also, using this passivation @7, 51 (100
)/S blind 01 (500A)/passivation/Al'
7) When the CV characteristic of a MOS capacitor with a laminated structure was measured at room temperature, it showed a normal curve as shown by curve C in Figure 2.

以上5!施例で示したようtC本パックベーションは電
気的特性もすぐれ、かつ耐水性も通常の1’ 8Gの2
fIi度ありすぐれたLSI用パックベーションである
ということができる。
That’s all 5! As shown in the examples, the tC packvation has excellent electrical characteristics and water resistance as high as 1'8G2.
It can be said that this is an excellent packvation for LSI.

〔宅間の効果〕[Takuma effect]

本発明によれば高信頼性の超り、SI用パッジベージタ
ンが得られる。
According to the present invention, it is possible to obtain a padge beige tongue for SI that is more than highly reliable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明パッシベーションの一部拡大断面図、第
2図は本発明によるMU8キジパシターのC−■特性?
示す説明図である。 1・・・非晶質嘆、2・・・粒界拡散層、3・・・焙晶
質薄嘆。
FIG. 1 is a partially enlarged sectional view of the passivation according to the present invention, and FIG. 2 is a C-■ characteristic of the MU8 pheasant passivator according to the present invention.
FIG. 1...Amorphous layer, 2...Grain boundary diffusion layer, 3...Crystalline layer.

Claims (1)

【特許請求の範囲】[Claims] 結晶質被膜と非結晶質被膜とが隣接し、かつ結晶質被膜
の粒界に非結晶質被膜からのイオンの拡散により粒界の
ポテンシャル障壁を高めたことを特徴とする超LSI用
パッシベーション。
A passivation for a VLSI, characterized in that a crystalline film and an amorphous film are adjacent to each other, and a potential barrier at the grain boundary is increased by diffusion of ions from the amorphous film to the grain boundaries of the crystalline film.
JP7962887A 1987-04-02 1987-04-02 Passivation for super lsi Pending JPS63246830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7962887A JPS63246830A (en) 1987-04-02 1987-04-02 Passivation for super lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7962887A JPS63246830A (en) 1987-04-02 1987-04-02 Passivation for super lsi

Publications (1)

Publication Number Publication Date
JPS63246830A true JPS63246830A (en) 1988-10-13

Family

ID=13695341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7962887A Pending JPS63246830A (en) 1987-04-02 1987-04-02 Passivation for super lsi

Country Status (1)

Country Link
JP (1) JPS63246830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100716904B1 (en) 2005-12-28 2007-05-10 동부일렉트로닉스 주식회사 Passivation layer for semiconductor device and manufacturging method thereof
JP2018164102A (en) * 2011-09-26 2018-10-18 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100716904B1 (en) 2005-12-28 2007-05-10 동부일렉트로닉스 주식회사 Passivation layer for semiconductor device and manufacturging method thereof
JP2018164102A (en) * 2011-09-26 2018-10-18 株式会社半導体エネルギー研究所 Semiconductor device

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