JPS6112033A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the increase of interfacial charge density Qss as well as to effectively prevent the generation of adverse effect of the deterioration of insulating characteristics of an element isolation region by a method wherein a high density PSG film having the concentration of P of a specific value or above is provided. CONSTITUTION:A silicate glass of one or more layers containing 5wt% or more of P is provided between a protective film 3 and a plasma SiN film 10 in the semiconductor device having a silicate glass 6 of one or more layers containing 5wt% or less of impurities such as As, Sb or P and the like and an SiN film 10 formed in deposition by performing a plasma CVD method provided on the protective film 3 of SiO2 and the like formed on the semiconductor substrate 1 of Si and the like. By providing said high density PSG film 9, the H contained in the plasma SiN film is moved when an annealing and the like is performed, and H is prevented from reaching the semiconductor substrate by the high density PSG film, thereby enabling to substantially reduce the charge density Qss located on the interface between the semiconductor substrate 1 and the protective film 3 3 of SiO2 and the like.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device in which a plurality of elements such as MOS FETs are formed on a semiconductor substrate, and in particular, the present invention relates to a semiconductor device in which a plurality of elements such as MOS FETs are formed on a semiconductor substrate. The present invention relates to a semiconductor device having a silicon film.

[Background technology and its problems]

For example, an N-channel MO8 type FgT (field effect transistor) or an I
In semiconductor devices such as C (integrated circuits) and LSI (large scale integrated circuits), a reflow film made of As5G (arsenic silicate glass) or Sb'SG (antimony-based silicate glass) is formed on the semiconductor substrate. A structure is known in which a plasma SiN (silicon nitride) film is formed directly or via an 8i (h layer) on a flow film.

That is, FIG. 8 shows a part of an IC or LSI having an N-channel MO8 type FET element 30.degree. 30 as an example of such a semiconductor device. In FIG. 8, for example, a P-type diffusion region 32 is formed facing the surface of an N-type silicon semiconductor substrate 31, and facing the surface of this P-type region 32 becomes the source and drain regions of the FET element 30, 30. An N-type region is formed by a diffusion method or the like.

Here, the surface of the P-type region 32 is oxidized by selective oxidation or the like.
After forming an insulating protective film 33 of i (h) and forming a gate electrode 34 and wiring electrodes 35 made of Po1y-8i (polycrystalline silicon) on this protective film 33, As5G (arsenic silicate glass) or A reflow film 36 of 5b8G (antimony silicate glass) is formed.For example, this As5G glue flow film 36 can be reflowed at a relatively low temperature,
It has features such as less adverse effects due to corrosion and migration of Al when forming 5 etc., and high reliability of wiring. Next, As5G! After forming an Alt electrode 31 and the like on the J flow film 36 as necessary, a 5iN (silicon nitride) film 38 for surface stabilization (passivation) is deposited by plasma CVD. This plasma SiN film 38 has excellent moisture resistance, chemical stability, and physical stability, and has the advantage that it can be deposited at a relatively low temperature.

By the way, in the structure in which the plasma SiN film 38 is laminated on the As5G reflow film 36, the so-called forming annealing treatment is performed at a temperature of 350 to 450, for example.
When carried out for about 30 to 120 minutes in the temperature range of ℃, the S of the substrate
The charge density Qss existing at the interface between the 5in2 insulating protective film 33 and the PET element 30.
As the interfacial charge density QSs of the element isolation region 39 between the elements 30 increases, it becomes impossible to effectively isolate the elements.

That is, while the normal Qss value is about 1~5X10cm, the Qss value in the above configuration is about 1~5X10cm.
The distance reaches as much as 10 cm 2 , and the element isolation region 39 becomes nearly conductive.

This means that the plasma SiN film 38 absorbs 5 to 5 [H] (hydrogen).
It contains a relatively large amount of 20% by weight, and CV
As (J?a or SbC) is used as the source gas when forming D.
Due to the fact that a CZ (chlorine)-based gas such as /g is used, the plasma SiN film 3
[H] of 8 moves and is not captured by the flow film 36 on the way (reaches the Si (substrate)-8iOz (protective film) interface and is accumulated as a charge, causing a so-called field reversal phenomenon and Pseudo N is present at the 5i-8iOz interface in the separation region.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and
Suppressing the increase in the 5i-8iCh interfacial electric field density Qss in the element isolation region in a semiconductor device in which a reflow film made of silicate glass such as s5G and a plasma SiN film are laminated, without adversely affecting the isolation between elements. The purpose is to provide semiconductor devices.

[Summary of the invention]

That is, the feature of the semiconductor device according to the present invention is that Si
At least one layer of silicate glass film containing impurities such as As (arsenic), SB (antimony), or impurities of less than 5% by weight on a protective film such as 810□ formed on a semiconductor substrate such as (silicon); In a semiconductor device having a 5iN (silicon nitride) film deposited by a plasma CVD method, at least a silicate or glass film containing 5% by weight or more of impurities is provided between the protective film and the plasma 8iN film. It is necessary to further establish this. By providing this high concentration PSG (phosphorus silicate glass with a P concentration of 5% by weight or more) film, the semiconductor substrate and the 5i0
It becomes possible to significantly reduce the charge density Qss existing at the interface with the protective film 2 and the like (approximately one order of magnitude or more compared to the conventional method). This is included in the plasma SiN film [
This is because the high concentration PSG film prevents H] (hydrogen) from moving during annealing treatment and reaching the semiconductor substrate.

〔Example〕

Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention, in which an N-type source region 2S and a drain region 2D are formed by, for example, a diffusion method, facing the surface of a P-type region of a Si semiconductor substrate 1. Multiple sets of each are formed. Above the active region sandwiched between the source region 2S and drain region 2D, a gate electrode 4 made of Po1y-8i (polycrystalline silicon) is connected via a thin gate insulating film 3G made of Sioz or the like. is formed. Here, as for the gate insulating film 3G, by performing, for example, selective oxidation on the surface of the Si substrate, the field insulating film 3G is thicker (for example, about 3000 to 8000 Å) in other parts.
It may be formed together with F. A wiring electrode 5 made of, for example, Poly-8i may be formed on the field insulating film 3F, if necessary.

These gate insulating film 3G and field insulating film 3F
On the insulating protective film 3, As5G (arsenic silicate glass) is deposited, for example, by CVD to
It is deposited to about 0A, and then heated at 900°C for 1
After being subjected to reflow treatment (or glass flow treatment) by heating for about 0 minutes, As5G! A J flow membrane 6 is formed.

This reflow process uses the above-mentioned flow phenomenon of glass during heating to loosen the slope of steps such as etching edges.
This is to prevent wire breakage, etc.

For example, after the As5G deposition is performed before this reflow treatment, contact window openings for the source and drain regions 28.7D are processed, and the source and drain electrodes 78.7D are formed. , an N-channel MO8 type FET (field effect transistor) element is formed.

The above configuration is the same as the conventional one, and is not limited to the manufacturing method described above, and the film thickness and the like may be set in the same manner as the conventional one.

Next, the ASSG film 6 is also used as, for example, an insulating film between the eyebrows,
After forming a wiring electrode 8a made of AA (aluminum) or the like on this AsSG film 6 as necessary, pso(
PSGSeO2 is formed by depositing a phosphorus silicate glass (phosphorus silicate glass) by, for example, a CVD method. At this time, the PSGSeO2 concentration was set to 3000 to 8000 A, and the impurity concentration was set to 5% by weight or more. ThisΦP
The concentration is preferably in the range of 7 to 12% by weight, more preferably in the range of 9 to 12% by weight, as described below.

Next, after forming a wiring electrode 8b made of A1 or the like as necessary on the PSG film 9, a 5i
A N (silicon nitride) film 10 is deposited to a thickness of approximately 8,000 to 12,000 Å (0.8 to 1.2 μ771), for example.

In a semiconductor device having the above structure, that is, from the top layer to the plasma SiN=PSG-AsSG-81o2-8i substrate, PSGSeO
As a result of measuring the 5iCh-8i interfacial charge density Qss when changing the 2 (phosphorus) concentration, a graph as shown in FIG. 2 was obtained. In this Figure 2, the vertical axis is the unit area (1c
The interfacial charge Qss per m) is expressed on a logarithmic scale, and the horizontal axis expresses the P concentration on a weight scale. As is clear from the graph in FIG. 2, this is a silicate gas that does not contain P (P concentration is 0% by weight).

The PSG film has a Qss of 2×1 (Fcm” or more), but when a PSG film with a P concentration of 5% by weight or more is used, the Qss decreases by about one order of magnitude or more, and is reduced to 1/1.
0 or less), and good results have been obtained. In practical terms, the value of Qss is approximately 10Cm or less.
The P concentration is preferably 7% by weight or more, and in consideration of corrosion of AA when used as an interlayer insulating film for A/wiring electrodes, the P concentration is preferably 12% by weight or less. More preferably, the P concentration is in the range of 9 or more and 12% by weight or less.

Here, instead of the As5GIJ flow membrane 6, 5bS
G (antimony silicate glass) reflow treatment, PSG4J film, etc. may be used, and As8
A multilayer structure of a G film, a 5bSG film, and a PSG film may be used. These silicate glass film impurities (As, Sb
, P, etc.) is generally less than 5% by weight.

In short, these low concentration silicate glass films, such as A
s5 () Apart from the IJ flow film, the plasma SiN film and s
A PSG film having a P concentration of 5% by weight or more is provided between an insulating protective film such as JOG.

For example, a structure using a 5bSG (antimony silicate glass) glue flow film instead of the As5G reflow film 6 in the configuration shown in FIG. 1, that is, a plasma SiN
-PSG-8b 8G-8i'02-8i substrate, in the semiconductor device according to the second embodiment of the present invention using the laminated structure of 5i-8 when the PSGSeO2 concentration is changed.
A graph representing the iOa interfacial charge density Qss is shown in FIG. Next, FIG. 4 is a schematic cross-sectional view showing the main part of the third embodiment of the present invention. is 5% by weight
The above) PSG film 13 is directly formed. This PSG
Film 1 on film 3 SG film 14 and plasma SiN film 1
5 in this order, the plasma 5iN-ASSG-P2O-8iCh-8i substrate,
It has a laminated structure.

In this third embodiment, not only the As5G film 14 but also the PSG film 13 are subjected to a glue flow process of about 900°C to 950°C. Although the As5G film 14 has too high fluidity during reflow, since the PSG film 13 has low fluidity, no drop in breakdown voltage occurs at the stepped portion. Also, Po 1
A PSG film 13 is formed on the y-8i wiring electrode 16, and
By forming the AJ wiring electrode 17 on the s5G film 14, that is, by creating a structure in which the PSG film 13 and the AA electrode 17 are not in contact with each other, adverse effects such as A/corrosion caused by impurities can be prevented, and the P concentration can be reduced. Can be made high. The other structure of this third embodiment is the same as that of the first embodiment described above, so it is not shown and the explanation will be omitted.

In the third embodiment, the 5j-8iCh interfacial charge density Qss when the P concentration of the PSG film 13 is changed is as shown in FIG. In Fig. 5, when the P concentration is 7% by weight, Qss is about 1 to 2 x 10 Cm, but as mentioned above, it is possible to prevent adverse effects such as A/corrosion, so the P concentration is further increased. Qss can be significantly reduced.

Next, FIG. 6 shows a fourth embodiment of the present invention, and FIG.
As5G film 14 and plasma SiN film 1 in the example of
A structure in which a 5iOz film 18 is disposed between the 5iOz film 18 and the 5iOz film 18 is shown. Similarly to the third embodiment, this fourth embodiment can also be constructed so that the Al wiring electrode 17 and the PEG film 13 do not come into direct contact with each other, and the P concentration of the PSG film 13 is increased to increase the Qss. This can be significantly reduced.

The 5iCh film 18 of this fourth embodiment has a low concentration of P.
An SG film may also be used, and by setting the P concentration of this low concentration PSG film to less than 5% by weight, adverse effects such as corrosion of the A/electrode 17 can be prevented.

Furthermore, the high concentration PSG film 13 of this fourth embodiment and the As
5G film 14 to form a SiO2 film 19 into which P and As are introduced, as in the fifth embodiment shown in FIG.
may be formed. This fifth implementation P in 7 cases
It goes without saying that Qss can be reduced by setting the As-introduced Si0 film 19P concentration to 5% by weight or more. Furthermore, according to this fifth embodiment,
Manufacturing is easier than in the fourth embodiment, and the first embodiment is easier to manufacture than the fourth embodiment.
Compared to the second embodiment, this embodiment has the advantage that there are fewer adverse effects such as corrosion of the Al electrode.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be applied to, for example, a high concentration PSG film or a low concentration silicate film.
Glass film (As8G film, 5b8G film, PSG film, etc.)
Each layer may be configured in multiple layers.

In addition to MO8 type FET elements, we also offer
It is also applicable to semiconductor devices using transistors.

〔Effect of the invention〕

According to the semiconductor device of the present invention, by providing a high concentration PSG film with a P concentration of 5% by weight or more, the interfacial charge density Qs
The increase in s can be suppressed, and adverse effects such as deterioration of the insulation properties of the element isolation region can be completely prevented.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the main part of the first embodiment of the present invention, and FIG. 2 is a graph showing the relationship between the P concentration and interfacial charge density Qss of the PSG film of the first embodiment. Figure 3 shows the P concentration and interfacial charge density Qss of the PSG film of the second embodiment of the present invention.
FIG. 4 is a schematic sectional view showing the main part of the third embodiment of the present invention, and FIG. 5 is a graph showing the relationship between
A graph showing the relationship between the P concentration of the SG film and the interfacial charge density Qss, FIG. 6 is a schematic cross-sectional view showing the main part of the fourth embodiment of the present invention, and FIG. 7 is a fifth embodiment of the present invention. FIG. 8 is a schematic sectional view showing a conventional example.

Claims (1)

[Claims] A semiconductor device comprising, on a protective film formed on a semiconductor substrate, at least one silicate glass film containing less than 5% by weight of impurities, and a silicon nitride film formed by plasma CVD, the protective film and the silicon nitride film. A semiconductor device characterized in that at least one silicate glass film containing 5% by weight or more of P (phosphorus) is provided between the semiconductor device and the semiconductor device.