JPS6324663A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the time required for overall processes by a method wherein the formation of ROM patterns and the formation of interconnection patterns are performed by the same photoetching process. CONSTITUTION:A field oxide film 2, a source-drain region 8, a channel region 4, a gate insulating film 5 and a gate electrode 6 are formed on a P type substrate 1. Next, a protective insulating layer 7 is formed and then a contact holes 8 are made in the positions corresponding to overall region of layer 7 to form a conductive layer 10 thereon. Thus, overall region 3 is commonly connected to the layer 10 Later, when any data to be written are presented by a user, ROM patterns are designed conforming to the data to decide if any MOSFET elements on an array are necessary or not. The overall region 3 being connected to the layer 10, this shortcircuited state may be maintained for any unnecessary elements while the layer 10 may be removed to isolate the source-drain from each other for any necessary elements. Through these procedures, the time required from receiving order to delivery can be cut down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device suitable for manufacturing a mask ROM.

(Prior Art) Mask ROMs are widely used as devices that permanently store information. This mask ROM generally has a large number of M
It is composed of an O3FET element array. Mask RO
Since the data to be written to M differs from C to C depending on the requirements of each user, normally, in the middle of manufacturing a general-purpose MO8FET m-child array, an order is received from the user and the data to be written is presented by the user. After that, a ROM pattern is designed based on this data, and based on this ROM pattern, unnecessary elements are short-circuited between sources and drains, and necessary elements are provided with predetermined wiring.

Figure 2 shows an example of the manufacturing process of such a conventional general mask ROM. First, as shown in the figure (a), a semiconductor substrate 1 made of P-type silicon is prepared, and a field oxide film 2 for element isolation is formed.Next, as shown in the figure (b), a semiconductor substrate 1 made of P-type silicon is prepared. N-type impurities are implanted at predetermined locations to form source/drain regions 3. Furthermore, polyimide is implanted onto the channel head 4 formed between the source/drain regions 3 via a gate insulating film 5 made of silicon oxide. A gate electrode 6 made of silicon is formed. In this state, an array of general-purpose MOS FET elements is formed on the substrate 1. The next step is to write from the knee 11. It will continue only after data is presented.

Once the data is presented, a unique ROM pattern is designed for each MO8 on the array based on this data.
It is determined whether the FETX child is necessary or not. For unnecessary elements, the operation of transistors Tmll8L1 to Tmll8L1 must be disabled between the source and drain. This is R
This is done by forming an OM pattern mask by photolithography and performing ion implantation using this mask. This situation is shown in FIG. 2(C). Ions are implanted into the channel region 41 from above the gate electrode of the element to be shorted to shorten the source 31 and drain 32 (the implanted region is indicated by "-'° in the figure). In this way, the substrate 1
When the desired ROM pattern is formed on the top, the pattern shown in FIG.
), a protective insulating layer 7 is formed and contact holes 8 are opened at predetermined locations. Furthermore, as shown in the same figure (e), using this contact hole 8, Al1
A wiring layer 9 made of -8i or the like is formed by photolithography based on a predetermined wiring pattern.

As described above, a mask ROM desired by the user can be obtained.

(Problems to be Solved by the Invention) However, the above-described conventional method has the following problems.

(1) After receiving the order from the user, as shown in Figure 2 (C)
In order to carry out the processes shown in ~(e), R
IMI will be charged.

(2) In the process shown in FIG. 2(C), RO is placed on the substrate 1.
A photolithographic process is required to form the M pattern, which increases the total number of processes.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can shorten the entire process and shorten the period from order receipt to delivery.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device that includes a C1 source region, a drain region, a channel region provided between these regions, and an insulating film provided over the channel region. A step of forming a plurality of FET elements having a gate electrode provided on a semiconductor substrate, a step of forming a protective insulating layer on the semiconductor substrate to cover a source region, a drain region, and a channel region, and a step of forming a protective insulating layer on a source region of the protective insulating layer. a step of opening a contact hole at a position corresponding to the region and a drain region; a step of forming an overlapping layer on the protective insulating layer and electrically commonly connecting the plurality of source regions and drain regions via a contact ball; Among the multiple FET elements,
For unnecessary elements, the conductive layer is maintained so that the source region and drain region remain short-circuited by the conductive layer, and for necessary elements, the source region and drain region are respectively connected in a predetermined connection state. The patterning process and the design shorten the entire process and shorten the manufacturing period.

(Function) According to the method of the present invention, the ROM pattern formation process can be performed by photolithography at the same time as the wiring pattern formation process, so the photolithography process is reduced by one step compared to the conventional method. It turns out. In addition, before receiving an order from a user, we will form a protective insulating layer, open a contact hole,
From order to delivery, we can proceed with the process up to electrical connection via contact holes.
period will also be shortened.

(Example) The present invention will be described below based on an example shown in FIG. First, as shown in FIG. 1(a), a field oxide WA2 for element isolation is placed on a semiconductor substrate 1 made of P-type silicon.
, a source/drain region 3, a channel region 4, a gate insulating film 5, and a gate TiK 6 are formed. The steps up to this point are exactly the same as the steps up to FIG. 2(b) in the conventional method.

In the conventional method, the next step could not proceed without receiving an order from Nier Flea. In the method according to the present invention, several steps are further performed before receiving an order. First, a protective insulating layer 7 is formed as shown in FIG. A conductive layer 10 made of AN-8i is formed thereon. This state is shown in FIG. 1(b). Since contact holes 8 are formed in all source/drain regions 3,
All source/drain regions 3 are commonly connected to a conductive layer 10. Please check this figure 1 (b) before ordering.
) Continue the process until the state is reached. The ROM pattern has not yet been formed.

Now, when the user presents the data to be written, a ROM pattern is designed based on this, and the necessity or necessity of each MO3FE'T element on the array is determined. For unnecessary elements, the sources and drains must be shorted to disable the operation of the transistors. This short circuit is made by the conductor layer 10. As described above, all the source/drain regions 3 are in a short-circuited state by the conductor layer 10, so it is sufficient to maintain this short-circuited state for unnecessary elements. - On the other hand, for necessary elements, conductor FJ10 may be removed to isolate the source and drain. This removal operation of the conductor layer 10 is performed by photolithography based on the ROM pattern desired by the user. A feature of the present invention is that etching based on the wiring pattern is simultaneously performed during photoetching. Therefore, the mask pattern used during photoetching is a combination of the ROM pattern and the wiring pattern.

FIG. 1(C) shows the state after this etching. For unnecessary elements, the shorting layer 11 short-circuits the source 31 and drain 32, and for the necessary elements, predetermined wiring is provided by the wiring layer 12.

By comparing the state of FIG. 1(C) with the state of FIG. 2(e), it will be understood that the circuits are equivalent.

As described above, the method according to this embodiment has the following advantages compared to the conventional method.

(1) Before receiving an order from the user, the process has already progressed to Figure 1 (b), so after receiving the order, the same figure (C
), which shortens the time from order receipt to delivery.

(2) In the process shown in FIG. 1C, the formation of the ROM pattern and the formation of the wiring pattern are performed in the same photolithography process, so the number of photolithography processes can be reduced by one process.

This has the advantage of reducing labor and materials used in the photo-etching process.

(Effects of the Invention) As described above, according to the present invention, in the method for manufacturing a semiconductor device, the formation of a ROM pattern and the formation of a wiring pattern are performed by the same photolithography process, thereby shortening the entire process and! ! J construction period can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a process explanatory diagram of one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram illustrating a conventional semiconductor device. It is a process explanatory diagram which shows an example of the iJ manufacturing method. 1... Semiconductor substrate, 2... Field oxide film, 3...
... Source/drain region, 31... Source region, 3
2... Drain region, 4... Channel region, 41.
...Channel region into which impurities are implanted, 5...Gate insulating film, 6...Gate electrode, 7...Protective insulating layer, 8
...Contact hole, 9...Wiring layer, 10...
Conductive layer, 11... Short circuit layer, 12... Wiring layer. Applicant's agent Fi Fujio (C) Tsumugi I Figure

Claims (1)

[Claims] 1. An FET element having a source region, a drain region, a channel region provided between these, and a gate electrode provided on the channel region with an insulating film interposed therebetween is mounted on a semiconductor substrate. forming a plurality of protective insulating layers on the semiconductor substrate to cover the source region, drain region, and channel region; and contacting the protective insulating layer at positions corresponding to the source region and the drain region. forming a conductive layer on the protective insulating layer and electrically connecting a plurality of the source regions and drain regions in common through the contact hole; For unnecessary elements, the source region and drain region are maintained in a short-circuited state by the conductive layer, and for necessary elements, the source region and drain region are respectively connected in a predetermined connection state. , a step of patterning the conductive layer. 2. The patterning of the conductive layer is performed using the R provided by the user.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the manufacturing method is performed based on an OM pattern. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the conductive layer is patterned by photolithography. 4. Manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that the semiconductor substrate is made of silicon, the gate electrode is made of polysilicon, and the conductive layer is made of a compound of aluminum and silicon. Method.