JPS63244743A - Solder die bonding substrate of semiconductor device - Google Patents
Solder die bonding substrate of semiconductor deviceInfo
- Publication number
- JPS63244743A JPS63244743A JP7799987A JP7799987A JPS63244743A JP S63244743 A JPS63244743 A JP S63244743A JP 7799987 A JP7799987 A JP 7799987A JP 7799987 A JP7799987 A JP 7799987A JP S63244743 A JPS63244743 A JP S63244743A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thickness
- substrate
- die bonding
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 18
- 229910000990 Ni alloy Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 8
- 238000009736 wetting Methods 0.000 abstract description 5
- 238000009713 electroplating Methods 0.000 abstract description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 239000000956 alloy Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 13
- 239000010949 copper Substances 0.000 description 8
- 238000005476 soldering Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005253 cladding Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000009864 tensile test Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体チップの基板へのハンダダイボンデ
ィング時に、薄いＡｇ層によっても、すぐれたハンダぬ
れ性を示し、高い接合強度が得られる半導体装置のハン
ダダイボンディング用基板に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor that exhibits excellent solder wettability and provides high bonding strength even with a thin Ag layer during solder die bonding of a semiconductor chip to a substrate. The present invention relates to a solder die bonding substrate for an apparatus.
従来、一般に半導体装置として、例えば第１図に概略断
面図で示されるサーディツプ型のセラミックパッケージ
が知られている。2. Description of the Related Art Conventionally, as a semiconductor device, for example, a cerdip type ceramic package shown in a schematic cross-sectional view in FIG. 1 has been known.
このセラミックパッケージは、ノーンダダイボンディン
グ用基板１として、例えば厚さ：０．３０のＦｅ −４
２％Ｎｉ合金製基材の片面あるいは両面に、厚さ二０．
５μｍのＣｕ層をはさんで厚さ１２０μｍのＡｇ層を、
通常の湿式メッキ法やロールクラッド法などにより形成
したものを用い、これをセラミック下型２のキャビティ
底面にガラスペーストを用いて接着した後、この基板１
の上面に、例えばＰｂ−５％Ｓｎ合金ノ・ンダを用いて
８１などの半導体チップ３を接着し、ついで前記セラミ
ック下型２の上面に同じくガラスペーストを用いて接着
しであるＦｅ −４２％Ｎｉ合金製リード４と、半導体
チップ３とに渡ってＡｕ極細線５をボールボンディング
し。This ceramic package is made of Fe-4 having a thickness of 0.30, for example, as a substrate 1 for non-under die bonding.
A 20% thick Ni alloy substrate is coated on one or both sides of the 2% Ni alloy base material.
A 120 μm thick Ag layer sandwiched between a 5 μm Cu layer,
This substrate 1 is formed using a normal wet plating method or roll cladding method, and is bonded to the bottom of the cavity of the ceramic lower mold 2 using glass paste.
A semiconductor chip 3 such as 81 is bonded to the top surface using, for example, a Pb-5%Sn alloy powder, and then a Fe-42% semiconductor chip 3 such as 81 is bonded to the top surface of the ceramic lower mold 2 using a glass paste as well. An ultrafine Au wire 5 is ball-bonded across the Ni alloy lead 4 and the semiconductor chip 3.
ｊｌ終的に同じくセラミック上型６をガラスは−ストを
用いてセラミック下型２にノミツク接合することによっ
て製造されている。Finally, the ceramic upper mold 6 is similarly manufactured by chiseling the glass to the ceramic lower mold 2 using a metal mold.
上記のように従来半導体装置においては、ハンダダイボ
ンディング用基板として、 Ｆｅ −４２％Ｎｉ合金製
基材の片面または両面に１通常のメッキ法あるいはクラ
ッド法により、ハンダぬれ性および接合強度を向上させ
るために、 ＣＵ層を介してＡｇ層を積層形成したもの
が使用されているが、この場合前記Ａｇ層の厚さが２０
μｍ以下だと、例えば大気中、温度二５００℃に１０分
間保持の条件での基板のセラミック下型への接着時に、
大気中の酸素がＡｇ層を通して拡散し、 Ｃｕ層が著し
く酸化し。As mentioned above, in conventional semiconductor devices, as a substrate for solder die bonding, one or both sides of a Fe-42%Ni alloy base material is coated with a conventional plating method or cladding method to improve solder wettability and bonding strength. For this reason, a layer in which an Ag layer is laminated through a CU layer is used, but in this case, the thickness of the Ag layer is 20 mm.
If it is less than μm, for example, when bonding the substrate to the ceramic lower mold under conditions of holding the temperature at 2500°C for 10 minutes in the air,
Oxygen in the atmosphere diffuses through the Ag layer, significantly oxidizing the Cu layer.
この結果半導体チップのハンダ付は時に、 Ｃｕ層への
拡散酸素によってハンダぬれ性が低下し、高い接合強度
を確保することができなくなることから。As a result, when soldering semiconductor chips, the solder wettability sometimes decreases due to oxygen diffusing into the Cu layer, making it impossible to ensure high bonding strength.
Ａｇ層の厚さを２０μｍ以上に厚くして、その下層のＣ
ｕ層への酸素拡散を防止しているのが現状である。The thickness of the Ag layer is increased to 20 μm or more, and the C layer below it is
The current situation is to prevent oxygen diffusion into the u layer.
一方、近年の半導体装置に対する省力化および低コスト
化の要求は厳しく、かかる点から基板における高価なＡ
ｇ層の薄肉化が急務となっている。On the other hand, in recent years there has been a severe demand for labor saving and cost reduction for semiconductor devices, and from this point of view, expensive A
There is an urgent need to reduce the thickness of the G layer.
そこで、本発明者等は、上述のような観点から。 Therefore, the inventors of the present invention, from the above-mentioned viewpoint.
半導体装置の組立てに用いられるハンダダイボンディン
グ用基板における特に何層の薄肉化に着目し研究を行な
った結果、従来ハンダダイボンディング用基板における
Ｃｕ層をＮｉ層に代えると、その上に形成されるＡｇ層
を薄くしても１例えば前記基板のセラミック下型への接
着時における酸化が著しく抑制されるようになシ、この
結果半導体チップのハンダ付は時に、すぐれたハンダぬ
れ性を示し、高い接合強度で半導体チップを基板に接着
することができるようになるという知見を得たのである
。As a result of research focusing on thinning the number of layers in solder die bonding substrates used for assembling semiconductor devices, we found that when the Cu layer in conventional solder die bonding substrates is replaced with a Ni layer, Even if the Ag layer is made thinner, oxidation can be significantly suppressed, for example during bonding of the substrate to the ceramic lower mold, and as a result, soldering of semiconductor chips sometimes exhibits excellent solder wettability and high They discovered that it is possible to bond a semiconductor chip to a substrate by increasing the bonding strength.
したがって、この発明は、上記知見にもとづいてなされ
たものであって、Ｆｅ−４２％Ｎｉ合金製基材の片面あ
るいは両面に、通常のメッキ法あるいはクラッド法を用
いて、厚さ１０．１〜２μｍのＮｉ層を介して、厚さ２
５〜１５μｍのＡｇ層を積層形成してなる半導体装置の
・・ンダダイボンデイング用基板に特徴を有するもので
ある。Therefore, the present invention has been made based on the above knowledge, and uses a conventional plating method or cladding method on one or both sides of a Fe-42%Ni alloy base material to a thickness of 10.1 to 10.1 mm. Through a 2 μm Ni layer, a thickness of 2
This is a substrate for die bonding of a semiconductor device formed by laminating Ag layers of 5 to 15 μm.
なお、この発明の基板において、Ｎｉ層は、その厚さが
０．１μｍ未満では半導体チップを基板に十分な接合強
度で接合することができないので、その厚さをＯ，１μ
ｍ以上にする必要があるが、一方その厚さが２μｍを越
えても、より一層の向上効果は得られず、経済性を考慮
すると、その上限値は２μｍで十分であ＃）、またＡｇ
層についても、その厚さが５μｍ未満では、半導体チッ
プの接合強度が低く、十分な接合強度を確保するために
は５μｍ以上の厚さにする必要があるが、１５μｍを越
えた厚さにすると、コスト面での有利性が損なわれるよ
うになるばかシでなく、よシ一層の向上効果も現われな
いことから、その上限値を１５μｍと定めたのである。In the substrate of the present invention, if the thickness of the Ni layer is less than 0.1 μm, the semiconductor chip cannot be bonded to the substrate with sufficient bonding strength, so the thickness is set to 0.1 μm.
On the other hand, even if the thickness exceeds 2 μm, no further improvement effect can be obtained, and considering economic efficiency, the upper limit of 2 μm is sufficient.
Regarding the layer, if the thickness is less than 5 μm, the bonding strength of the semiconductor chip will be low, and in order to ensure sufficient bonding strength, it is necessary to have a thickness of 5 μm or more, but if the thickness exceeds 15 μm, the bonding strength of the semiconductor chip will be low. The upper limit was set at 15 .mu.m because it would not be foolish to impair the cost advantage and no further improvement would occur.
つぎに、この発明の基板を実施例によシ具体的に説明す
る。Next, the substrate of the present invention will be specifically explained using examples.
厚さ：０．３１１１のＦｅ−４２％Ｎｉ合金製基材を用
意し、この基材の両面に通常の電気メツキ法にて。A base material made of Fe-42%Ni alloy with a thickness of 0.3111 was prepared, and both sides of this base material were plated using a normal electroplating method.
それぞれ第１表に示される厚さのＮｉ層またはＣｕ層を
形成し、さらにその上にＡｇ層を形成し、ついで縦：５
ｕＸ横ニア龍の寸法に打抜くことによって本発明基板１
〜７および比較基板１〜９をそれぞれ製造した。A Ni layer or a Cu layer is formed with the thickness shown in Table 1, and an Ag layer is further formed thereon, and then vertical: 5
The substrate 1 of the present invention is punched to the dimensions of uX horizontal near dragon.
-7 and comparative substrates 1-9 were manufactured, respectively.
つぎに、これらの各種の基板に、基板のセラミック下型
への接着条件に相当する条件、すなわち大気中、温度二
５００℃に１０分間保持後、冷却の条件で加熱処理を施
した後、これをヒートブロック上に置き、半導体チップ
のノ・ンダ付けに相当する条件、すなわち窒素雰囲気中
、温度：３５０℃に加熱した状態で、５ｍｇのＰｂ−５
％Ｓｎ合金ノ１ンダを乗せ、このノ・ンダのぬれ拡がり
性を観察すると共に、その後直径：３１Ｌｌの純銅製ピ
ンを垂直に立てた状態で基板にノ・ンダ付けし、室温ま
で冷却して接合強度を測定した。なお、接合強度は、第
２図に正面図で示されるように、引張試験機を用い、基
板Ａを支持板Ｂでおさえた状態でピンＣを基板から引き
離し、この時の荷重をもって表わした。これらの結果を
第１表に示した。Next, these various substrates were heat-treated under conditions equivalent to the bonding conditions of the substrate to the ceramic lower mold, that is, held at a temperature of 2,500°C for 10 minutes in the atmosphere, and then cooled. was placed on a heat block and heated to a temperature of 350°C in a nitrogen atmosphere under conditions equivalent to bonding semiconductor chips.
%Sn alloy solder and observed the wetting and spreading properties of the solder. Then, a pure copper pin with a diameter of 31 Ll was placed vertically on the substrate and soldered, and the solder was cooled to room temperature. The bond strength was measured. As shown in the front view of FIG. 2, the bonding strength was measured by using a tensile testing machine and pulling the pin C away from the substrate while holding the substrate A with the support plate B, and expressed the load at this time. These results are shown in Table 1.
第 １ 表
第１表に示される結果から１本発明基板１〜７は、Ａｇ
層の厚さが１５μｍ以下と薄い釦もかかわらず、下地層
のＮｉ層によってハンダ付は前の大気加熱での酸化が防
止されるので、ハンダ付は時には良好なぬれ拡がシ性を
示し、かつきわめて高い接合強度を示すのに対して、比
較基板１〜７に見られるように、下地層が従来基板にお
けると同様にＣｕ層の場合にはｓ Ａｇ層の厚さが１５
μｍ以下と薄いと、 Ｃｕ層の酸化が原因でハンダのぬ
れ拡がり性が十分でなく、接合強度も著しく低く、この
傾向はＮｉ層またはＡｇ層の厚さがこの発明の範囲から
薄い方に外れた比較基板８．９にも見られることが明ら
かである。Table 1 From the results shown in Table 1, substrates 1 to 7 of the present invention were Ag
Despite the thin button with a layer thickness of 15 μm or less, the Ni layer as the base layer prevents soldering from oxidizing during previous atmospheric heating, so soldering sometimes exhibits good wetting and spreading properties. On the other hand, as seen in Comparative Boards 1 to 7, when the underlying layer is a Cu layer as in the conventional board, the thickness of the Ag layer is 15 cm.
If the thickness is less than μm, the wetting and spreading properties of the solder will be insufficient due to oxidation of the Cu layer, and the bonding strength will also be extremely low. It is clear that this can also be seen in Comparative Board 8.9.
上述のように、この発明のハンダダイボンディング用基
板は、これの表面に形成されるＡｇＥｊｉの厚さが薄い
にもかかわらず、これへの半導体チップのハンダ付けに
際しては、良好なハンダぬれ拡がシ性を示し、かつ高い
接合強度が得られるものであって、半導体装置のコスト
低減に寄与するところ大なるものである。As mentioned above, the solder die bonding substrate of the present invention exhibits good solder wetting and spreading when a semiconductor chip is soldered thereon, despite the thin AgEji formed on its surface. It exhibits high bonding strength and high bonding strength, and greatly contributes to cost reduction of semiconductor devices.
第１図はセラミックパッケージを示す概略断面図、第２
図は接合強度の測定状態を示す正面図である。
１・・・基板、 ２・・・セラミック下型。
３・・・半導体チップ、 ４・・・リード、５・・・
Ａｕ極細線、 ６・・・セラミック上型、Ａ・・
・基板、 Ｂ・・・支持板、Ｃ・・・ピン。Figure 1 is a schematic sectional view showing a ceramic package, Figure 2 is a schematic cross-sectional view showing a ceramic package.
The figure is a front view showing the state of measurement of bonding strength. 1...Substrate, 2...Ceramic lower mold. 3...Semiconductor chip, 4...Lead, 5...
Au ultra-fine wire, 6...Ceramic upper mold, A...
・Board, B...Support plate, C...Pin.
Claims (1)
さ：０．１〜２μｍのＮｉ層を介して、厚さ：５〜１５
μｍのＡｇ層を積層形成してなる半導体装置のハンダダ
イボンディング用基板。A Ni layer with a thickness of 0.1 to 2 μm is interposed on one or both sides of the Fe-42%Ni alloy substrate to a thickness of 5 to 15 μm.
A substrate for solder die bonding of semiconductor devices, which is formed by stacking μm-thick Ag layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7799987A JPS63244743A (en) | 1987-03-31 | 1987-03-31 | Solder die bonding substrate of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7799987A JPS63244743A (en) | 1987-03-31 | 1987-03-31 | Solder die bonding substrate of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63244743A true JPS63244743A (en) | 1988-10-12 |
Family
ID=13649498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7799987A Pending JPS63244743A (en) | 1987-03-31 | 1987-03-31 | Solder die bonding substrate of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63244743A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396670A (en) * | 1977-02-04 | 1978-08-24 | Hitachi Ltd | Pellet bonding method |
| JPS57149741A (en) * | 1981-03-11 | 1982-09-16 | Hitachi Ltd | Bonding method for semiconductor pellet |
| JPS57211762A (en) * | 1981-06-24 | 1982-12-25 | Hitachi Cable Ltd | Lead frame for semiconductor |
-
1987
- 1987-03-31 JP JP7799987A patent/JPS63244743A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396670A (en) * | 1977-02-04 | 1978-08-24 | Hitachi Ltd | Pellet bonding method |
| JPS57149741A (en) * | 1981-03-11 | 1982-09-16 | Hitachi Ltd | Bonding method for semiconductor pellet |
| JPS57211762A (en) * | 1981-06-24 | 1982-12-25 | Hitachi Cable Ltd | Lead frame for semiconductor |
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