JPS63244735A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an insulating film generating in response to the removal of a natural oxide film using an HF chemical solution, to prevent the deterioration in element characteristics due to the ion implantation into an active element region as well as to prevent the adverse effect inflicting on the element characteristics and the like of a diffusion layer by a method wherein the first insulating film, the first conductive layer and the second insulating film are formed successively on a semiconductor substrate, then after a contact hole has been formed, the second conductive layer constituting the upper wiring layer is formed, and then ions are implanted. CONSTITUTION:After a gate oxide film 23 has been grown on the silicon substrate 21 of an element region R1, the first polycrystalline film 24 is deposited on an interelement isolation film 22. Then, impurities are doped using a POC 13 liquid source. Subsequently, a thermal oxide film 25 is grown on the polycrystalline silicon film 24. Then, a contact hole 26 is perforated, and the natural oxide film grown on the silicon substrate 21 is removed using an HF chemical solution. Subsequently, the second polycrystalline silicon film 27 is deposited on the upper surface of the thermal oxide film 25 and the inner surface of the contact hole 26. Then As ions are implanted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for obtaining direct contact between an upper wiring layer and a semiconductor substrate.

(Prior Art) A MO8I field effect transistor (hereinafter referred to as MOSFET) has a structure for directly contacting an upper wiring layer and a semiconductor substrate (specifically, a drain electrode formed on the surface area of the semiconductor substrate). have A conventional manufacturing method of such a direct contact structure will be explained using FIGS. 3(a) to 3(C).

Note that in the following explanation, MOSFET will be taken as an example.

In FIG. 3(a), first, an element isolation film 12 is formed on a silicon substrate 11, and an element region R1 is set.

Thereafter, a gate insulating film 13 is formed on the silicon substrate 11 in this element region R1.

In FIG. 3(b), first, a recontact hole 14 is formed by selective etching. Next, the natural oxide film grown on the silicon substrate 11 is removed using HF-based chemicals.

After this, polycrystalline silicon 15 is deposited.

In FIG. 3C, mixing ion implantation is first performed to destroy the native oxide film on the silicon substrate 11 and obtain good contact characteristics. 16 is an ion implantation layer formed by this ion implantation.

Note that instead of performing the mixing ion implantation, as shown in FIG. 4, a deep diffusion layer 17 may be formed in the silicon substrate 11 by a high temperature liquid source diffusion method such as POC13. There is.

However, the conventional method described above has the following problems.

(1) In either of the above two methods, the surface of the gate insulating film 13 is destroyed as shown in FIG. 3(b) by the HF-based chemical treatment performed to remove the native oxide film.

(2) In the method shown in FIGS. 3(a) to (C), when performing mixing ion implantation, active element region R2 (MO
SFET gate region) (see Figure 3 (C)), the maximum value of ion distribution (hereinafter referred to as average range)
(see FIG. 3C) is located near the silicon substrate 31, and mixing is also performed in this region R2, resulting in deterioration of device characteristics.

(3) In the liquid source diffusion method shown in FIGS. 3(a), 4(b) and 4, the depth D of the diffusion layer 19 is large, which often has an adverse effect on device isolation characteristics or device characteristics.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device manufacturing method in which the upper wiring layer and the semiconductor substrate are brought into direct contact, the insulating film is removed due to the removal of the natural oxide film using HF-based chemicals. There are problems such as destruction, deterioration of device characteristics due to ion implantation into the active device region, and adverse effects on the device characteristics of the diffusion layer.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above problems.

[Structure of the Invention (Means for Solving the Problems)] To achieve the above object, the present invention first includes a first insulating film, a first conductive layer, and a second insulating film on a semiconductor substrate.
& form films sequentially. Next, after forming a contact hole, a second conductor layer forming an upper wiring layer is formed. After this, ion implantation is performed.

(Function) According to the above configuration, the first conductor layer retains mil! during the removal treatment of the natural oxide film using HF-based chemicals! Therefore, destruction of the first insulating film can be prevented.

Furthermore, during mixing ion implantation, the second insulating film prevents ions from being implanted into the active element region, thereby preventing deterioration of element characteristics. Furthermore, since this method does not use a diffusion layer, it is possible to prevent deterioration of device isolation characteristics and device characteristics due to the deep depth of the diffusion layer.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that in the following explanation, a MOSFET will be used as an element.

FIGS. 1(a) and 1(b) are cross-sectional views showing steps of a manufacturing method according to an embodiment.

In FIG. 1(a), first, on a P-type silicon substrate, a P-type wafer, etc. (hereinafter referred to as a p-type silicon substrate as a representative) 21, element isolation M! 22 and the element m region R
Set 1. Next, approximately 100 to 150 gate oxide films 23 are grown on the silicon substrate 21 in the element region R1. After this, either omit the pre-deposition treatment or
After performing a pre-deposition treatment using chemicals other than F-based chemicals, the first polycrystalline silicon 11!24 is deposited on the inter-element isolation film 22 in a thickness of approximately 500 to 1000 μm. In this case, this polycrystalline silicon M! The film thickness of the contact hole 24 is made as thin as possible in order to reduce processing conversion differences and steps caused by the opening of the contact hole 26, which will be described later. Next, an impurity, for example, about -10α is doped using a poc13 liquid source. Note that this doping amount is set to an extent that at least the work function is stabilized. Next, thermally oxidize l! on the polycrystalline silicon shield 24! 25 to grow to around 300 to 500 people. The thickness of the thermal oxide film 25 in this case is set to a thickness that can prevent ion implantation into the active element region R2, as will be described later.

In FIG. 1(b), first, by photoengraving process and reactive ion etching,
A contact hole 26 is opened to expose the silicon substrate 21. Next, the natural oxide film grown on the silicon substrate 31 is removed using HF-based chemicals. Thereafter, a second polycrystalline silicon film 37 is deposited on the upper surface of the thermal oxide film 35 and on the inner surface of the contact hole 36 by approximately 1,000 to 2,000 layers. After this, A with a small diffusion coefficient in silicon
Dosing s ions with acceleration energy x Kev! y
Inject approximately α. In this case, the above acceleration energy xK
ev is set so that the average range X is near the silicon substrate 31. Further, the dose amount y is set to a value such that the damage energy is sufficient to destroy the native oxide film, for example, a value such that the damage energy exceeds 3×10″ eV/person/ion.

As detailed above, in this embodiment, the gate oxidation l113
A polycrystalline silicon film 34 is formed on the gate oxide 11133, and with this polycrystalline silicon film 34 on the gate oxide 11133, the natural oxide film is removed using an HF-based chemical. According to such a configuration, the polycrystalline silicon film 3
4 serves as a protective film and can prevent the gate oxide film 33 from being destroyed by the HF-based chemicals.

Further, in this embodiment, a thermally oxidized film 35 is formed between polycrystalline silicon 1134 and polycrystalline silicon 1137. According to such a configuration, during mixing ion implantation, the thermal oxide film 35 serves as a stopper material for implanted ions, and can prevent impurities from being implanted into the MO8FET gate region R2. Thereby, deterioration of element characteristics can be prevented. When this is viewed in terms of threshold voltage vth, it becomes as shown in FIG. In FIG. 2, characteristic A is of this embodiment, and characteristic B is of the conventional one. According to this characteristic diagram, in this example, compared to the conventional method,
It can be seen that the threshold voltage vth can be prevented from decreasing.

Furthermore, since there is no need to form a diffusion layer in this embodiment, the diffusion layer does not have an adverse effect on element isolation characteristics and element characteristics.

Furthermore, by optimizing the mixing ion implantation conditions, low resistance and stable contact characteristics can be obtained.

Note that in the previous embodiment, thermal oxidation film 11 was used as the second insulating film.
25 has been described, but it goes without saying that, for example, a chemical vapor grown oxide film or a silicon nitride film may be used.

Further, in the previous embodiment, the case where the polycrystalline silicon film 27 is used as the second conductor layer has been described, but it goes without saying that, for example, a high melting point metal film may be used.

Furthermore, the present invention is of course applicable to direct contact between the upper wiring layer and the semiconductor substrate in devices other than MO8FET.

[Objective of the Invention] As described above, according to the present invention, destruction of the insulating film due to the removal of the natural oxide film by HF-based chemicals, deterioration of device characteristics due to ion implantation into the active device region, and damage to the device of the diffusion layer. A method for manufacturing a semiconductor device that can prevent adverse effects on characteristics etc. can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a manufacturing method according to an embodiment of the present invention;
FIG. 2 is a characteristic diagram showing the effects of one embodiment, FIG. 3 is a sectional view showing an example of a conventional manufacturing method, and FIG. 3 is a sectional view showing another example of the conventional manufacturing method. 21...Silicon substrate, 22...Element portion TLF film,
23... Gate oxide film, 24... First polycrystalline silicon film, 25... Thermal oxide film, 26... Contact hole, 27... Second polycrystalline silicon film. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (5)

[Claims] (1) A method for manufacturing a semiconductor device having a direct contact structure between a semiconductor substrate and an upper wiring layer, including a first step of forming an element isolation region on the semiconductor substrate, and an element region set in the first step. a second step of forming a first insulating film on the insulating film; a third step of forming a first conductive layer on the insulating film; and a third step of forming a first conductive layer on the first conductive layer; a fourth step of forming a second insulating film having a large stopping power;
a fifth step of selectively removing the conductive layer to expose the semiconductor substrate; and a second conductive layer on the portion of the semiconductor substrate exposed by the fifth step and the second insulating film. The sixth layer forms the body layer.
and performing ion implantation such that the average range is near the semiconductor substrate to damage or destroy the native oxide film and cause the first conductor layer and the semiconductor substrate to react with each other. A method for manufacturing a semiconductor device, comprising: a seventh step of making electrical contact. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a thermal oxide film. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a chemical vapor grown oxide film. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive layer is a high melting point metal film.