JPS6324338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal reception interrupt failure control method, and in particular to a signal reception interrupt failure control method for a device that owns a large number of data lines and processes signal reception equally for each line by interrupt processing. The present invention relates to detection of a fault in an interrupt request signal and a processing method when a fault occurs in a data line signal receiving circuit.

Conventionally, signal receiving systems have had a configuration as shown in the example of FIG. In the figure, when the received signal is stored in the reception buffer section A' of the signal reception section A, this reception buffer section A' generates the signal reception information signal 3, presets the flip-flop circuit FF, and outputs the interrupt request signal. Generates 6. The device control section D that receives the interrupt request signal 6 operates the device control interface section E of the signal reception section A using the bus line and the control signal 8, and operates the reception buffer section using the data and read control signal 1.
All received signals were read from A' and the flip-flop circuit FF was cleared by an interrupt reset signal 5.

However, if the interrupt request signal 6 continues to be generated due to a failure in the reception buffer section A or the flip-flop circuit FF, the device control section D will constantly repeat the interrupt processing for the line, and there is a possibility that other processing will become impossible. It was hot.

The present invention has been made in order to eliminate the above-mentioned disadvantages of the conventional technology, and therefore, an object of the present invention is to interrupt after reading one signal worth of received data in order to prevent the above-mentioned failure from occurring. Even if the next signal has already been received at the time of reset, the interrupt request signal is always lost until the next divided clock rises, so the operation of the interrupt request signal is checked and the corresponding interrupt It is an object of the present invention to provide a novel control method characterized by detecting a failure in a request signal and forcibly disconnecting the signal by a gate circuit when the failure occurs.

The above-mentioned object of the present invention is to sequentially process received signals in a signal receiving circuit of each data line of a device that owns a large number of data lines and processes signal reception equally for each line by interrupt processing. a receiving buffer unit which continues to output a signal reception information signal while the received signal is stored, and a device which generates a delayed interrupt signal from the signal reception information signal from the reception buffer unit and a clock signal and which will be described later. a delayed interrupt signal generating section that resets the delayed interrupt signal in response to an interrupt reset signal from the control interface section and generates the delayed interrupt signal again after a certain period of time when the signal reception information signal is generated; and the delayed interrupt signal. a gate circuit that relays or cuts off the interrupt request signal to the device control section, and has an interface with the device control section to read the received signal from the reception buffer section and generate an interrupt reset signal; and a device control interface section that inputs the relay output of the gate circuit and relays it to the device control, and even when multiple signals of fixed byte length are input continuously, all received signals are The device control unit activated by the interrupt request signal intermittently reads the received signal for the number of received signals, reads the interrupt reset, and reads the level change of the interrupt request signal after the interrupt reset, and interrupts the interrupt. If the request signal does not return to the no-interrupt level after being reset, it is determined that there is a failure in the data receiving line, and the device control section instructs the device control interface section to output a prohibition signal to the gate circuit; This is achieved by a signal reception interrupt failure control method characterized by stopping the relay of the interrupt request signal and disconnecting the main data reception line from the device control section.

Next, the present invention will be described in a second section with respect to a preferred embodiment thereof.
This will be explained in detail with reference to FIGS. FIG. 2 is a configuration diagram showing an embodiment of the present invention. In the figure, reference numeral B indicates a delayed interrupt signal generation section;
C indicates a date circuit, respectively. Other reference numerals have similar functions as shown in FIG.

Here, the specific block configuration of each element shown in FIG. 2 will be explained.

As shown in FIG. 3, the reception buffer section A' includes a buffer consisting of, for example, a FIFO that can buffer a signal consisting of a fixed n bytes by N signals;
It consists of a shift register for N bits and a start pattern detection circuit in parallel with the buffer. The signal reception information signal 3 is output while the shift register has "1" (the signal remains).

The delayed interrupt signal generating section B has the configuration shown in FIG. Signal reception information signal 3 is “1”
During this period, the F/F is set by a clock with a length close to one signal generated from the frequency dividing circuit, and the delayed interrupt signal 4 is output.

The device interface section E consists of the block configuration shown in FIG. This circuit performs order analysis based on the control signal from the device control section, operates the read control to read the received data through the bus interface circuit, outputs the read reset signal (pulse), and outputs the gate control signal "0". ”Outputs a fixed level.

The device control unit D consists of a CPU, ROM, RAM, a peripheral control circuit, a scan monitoring circuit for the interrupt signal 6, etc., and scans the signal 6 to set it to "0".
If there is a receiving line that has an interrupt at the level, scanning is stopped there, the port number is read, the received data of the corresponding receiving line is read, and after reading, the interrupt signal is reset.

When a plurality of signals are continuously received in the reception buffer section A' and the first signal is stored, the signal reception information signal 3 of the reception buffer section A' becomes "1" level, and the "1" level information is stored. After being subjected to a certain delay by the clock signal 2 in the delayed interrupt signal generating section B, the delayed interrupt signal 4 is output as a "1" level. The gate circuit C outputs the interrupt request signal 6 at the "0" level to the device control unit D as a result of the delayed interrupt signal 4 at the "1" level and the gate control signal 7 at the normal "1" level. The device control section D that has received the interrupt request signal 6 uses the bus line and the control signal 8 to control the device control interface section E.
The first received signal is read through the data and read control signal 1, and the delayed interrupt signal generator B is reset by the interrupt reset signal 5 to return the delayed interrupt signal 4 to the "0" level. Furthermore, the device control section D reads the level of the interrupt request signal 6, which has returned to the "1" level through the gate circuit C, via the device control interface section E, and confirms that the interrupt request has disappeared.

Here, if the interrupt request signal 6 remains at the "0" level even though the interrupt reset operation has been performed, the second signal has already been received if the operation of the delayed interrupt signal generator B is normal. Even if the signal reception information signal 3 remains at the "1" level, the "1" level information is not output during the delay time until the rise of the next divided clock. This can be determined to be a failure in the interrupt request signal due to a failure in the interrupt request signal, or a failure in the interrupt reset signal generation part. Therefore, the device control section D receives the gate control signal 7 via the device control interface section E.
By setting the interrupt request signal 6 to the "0" level and returning the interrupt request signal 6 to the "1" level by the gate circuit C, it is possible to disconnect the line and prevent it from affecting other processes.

Furthermore, even if the interrupt request signal 6 is generated when there is no signal due to a failure in the reception buffer section A', the corresponding reception signal is read and determined as a failure, and the gate circuit C is activated.
By controlling this, it is possible to disconnect the faulty line.

As shown in the time chart in Figure 6, even if the first signal interrupts at point A when two signals are input in succession, if the device control section is busy with reception processing of other lines, etc. , the reading of the first signal becomes point B. At point B, the second signal has already been input, and information 3 remains at the "1" level, but until the divided clock is input (point C), the delayed interrupt signal 4 is reset to "1". After it becomes 0, it does not become 1 again.

Therefore, if the delayed interrupt signal generator B or the interrupt reset related circuit in the order code decoder is broken, the delayed interrupt signal 4 will remain "1" in the worst case, and the signal will always be sent to the device control section. The interrupt request signal 6 continues to be input at "0".

By adopting the control method described above, the present invention prevents the processing of many other lines and other important processing operations from being affected by a failure in the interrupt signal system of the receiving section of one line. There is an effect that can be achieved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a conventional signal receiving system, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a block diagram showing a specific example of a receiving buffer section, and Fig. 4 is a diagram showing delayed interrupt signal generation. FIG. 5 is a block diagram showing a specific example of the device interface section, and FIG. 6 is a time chart showing an example of the operation of the present invention. A...signal receiving section, A'...receiving buffer section,
B...Delayed interrupt signal generation section, C...Gate circuit, E...Device control interface section, D...
Device control unit, 1... data and read control signal, 2... clock signal, 3... signal reception information signal, 4... delayed interrupt signal, 5... interrupt reset signal, 6... interrupt request signal, 7... ...Gate control signal, 8...Bus line and control signal.

Claims (1)

[Claims] 1. In the signal receiving circuit of each data line of a device that owns a large number of data lines and processes signal reception equally on each line by interrupt processing, the received signals are sequentially stored and received. A receiving buffer unit continues to output the signal receiving information signal while the signal is stored, and a delayed interrupt signal is generated from the signal receiving information signal from the receiving buffer unit and the clock signal, and a delayed interrupt signal is generated from the device control interface unit described later. a delayed interrupt signal generating section that resets the delayed interrupt signal using an interrupt reset signal and generates the delayed interrupt signal again after a certain period of time when the signal reception information signal is generated; and a device that uses the delayed interrupt signal as an interrupt request signal. A gate circuit that relays to or interrupts the control section, and has an interface with the device control section, reads the received signal from the reception buffer section, generates an interrupt reset signal, and outputs the relay output of the gate circuit. and a device control interface section that inputs the input signal and relays it to the device control section, so that even when multiple signals of fixed byte length are input continuously, all received signals are activated by an interrupt request signal. The received signal is read intermittently for the number of received signals, the interrupt is reset, and the level change of the interrupt request signal after the interrupt is reset is read until the received signal is taken over by the device control unit that has been reset via the bus and control line. If it does not return to the no-interrupt level, it is determined that there is a failure in the data receiving line, and the device control section instructs the device control interface section to output a prohibition signal to the gate circuit and relay the interrupt request signal. A signal reception interrupt failure control method characterized by stopping the data reception line and disconnecting the main data reception line from the device control unit.