JPS6324333B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes digital signal processing to perform single sideband frequency division multiplexing (hereinafter referred to as SSB-band signal) of a baseband signal.
The present invention relates to a single sideband frequency division multiplexing signal modulation device that multiplexes a signal (abbreviated as FDM signal).

In recent years, digital signal processing has enabled SSB-FDM
Attempts have been made to realize modulation and demodulation of signals. As a well-known method for modulating SSB-FDM signals through digital signal processing, IEEE
TRANSACTION ON COMMUNICATIONS,
VOL.COM−26, No.5, MAY 1978, PP720−
725 “An Improved Method for Digital
SSB−FDM Modulation and Demodulation”
There is.

Here, the principle of the above method will be briefly explained. Let us now assume that the sampling frequency of the baseband signal is _fs (the unit Hz is omitted below), and the sampling frequency of the SSB-FDM signal is N· _fs . However, N is a positive integer. The Z transformation of the sample value series of N baseband signals is expressed as X _k (Z ^N ) (where k=
0, 1, ..., N-1), and the sample value series of the SSB-FDM signal is Y(Z).

Since the baseband signal has a spectrum with a periodic structure that repeats at the frequency f _s , the center frequency is f _s /2
By preparing N band filters with different bandwidths f _s /2, inputting N baseband signals to each band filter, and adding the outputs of the N filters, the SSB-FDM signal can be obtained. Obtainable.

Here, as the above N band filters, a real low pass filter G(Z) with a bandwidth f _s /4 is given, and a complex band filter H k (Z) with a bandwidth f _s /2 is obtained by frequency shifting the real low pass filter _G (Z). can be used.
In other words, the center frequency of H _k (Z) is (4k+1)・
When f _s /4, the filter G(Z) has (4k+
1) If a frequency shift of f _s /4 is applied, H _k (Z) = H _k [exp{j2πf/N·f _s }] = G[exp{j2π(f−4k+1/4·f _s )/ N・f _s }
] =G[Z・exp{−j2π4k+1/4N}] …(1) Here, the complex band filter expressed by equation (1)
Even though H _k (Z) operates at the sampling frequency N・f _s , the input is only given at the frequency f _s , so H _k (Z) is composed of N filters operating at the sampling frequency f _s . It can be realized by breaking it down into

Real low-pass filter G(Z) with bandwidth f _s /4
When it is decomposed into N sets of filters, it becomes as follows.

G (Z) = _N-1 〓 ⁱ⁼⁰ Z ^-i・G _i (Z ^N ) ...(2) Substituting equation (2) into equation (1), H _k (Z) = _N-1 〓 ^{i =0} Z ^-i exp{j2π4k+1/4Ni}・G _i (−jZ ^N )...(3) is obtained. SSB-FDM signal sample value series Y(Z)
is the result of passing X _k (Z ^N ) through a filter H _k (Z) and adding the output for k = 0, 1, ..., N-1, so Y (Z) = R _e [ _N-1 〓 ⁱ⁼⁰ H _k (Z)・X _k (Z ^N )] …(4) holds true. Substituting equation (3) into equation (4), Y(Z)=R _e [ _N-1 〓 ⁱ⁼⁰ G _i (−jZ ^N )・A _i (Z ^N )・Z ^-i ] …(5 ) However, A _i (Z ^N )= _N-1 〓 ⁱ⁼⁰ X _k (Z ^N )・exp{j2π4k+1/4Ni}...(6) is obtained. The complex band filter bank of G _i (−jZ ^N ) in equation (5) is called a polyphase digital filter.

Here, the complex band filter G _i (−jZ ^N ) is obtained by substituting −jZ ^N in place of Z ^N in the transfer function of the real low-pass filter G _i (Z ^N ) determined by equation (2). This defines the transfer function.

As mentioned above, the complex band filter G _i (−jZ ^N )
Since the coefficients of the filters are real numbers or pure imaginary numbers, the amount of multiplication required is equivalent to that of two sets of real band filters.

By the way, SSB by digital signal processing
In modulation and demodulation systems for FDM signals, the scale of the equipment and, in turn, the price of the equipment are determined by the number of multiplications required per unit time, so a hardware configuration with essentially a small number of multiplications per unit time is required. Ru. In particular, the amount of multiplication required for a polyphase digital filter is considerably larger than that of the offset discrete Fourier operation expressed by equation (6), so
It is desired to reduce this. Furthermore, the hardware required for the multiplier depends on the coefficient bit length, so
Efforts must be made to shorten the coefficient bit length.

An object of the present invention is to provide a single sideband frequency division multiplexing signal modulation device that requires fewer multiplications per unit time and lowers coefficient precision than conventional methods, and that has a small hardware scale. It's about doing.

First, let us consider dividing the complex band filter G _i (-jZ ^N ), which is a component of the polyphase circuit, into a real part and an imaginary part and realizing it as two real band filters.

From equations (5) and (6), if expressed using complex conjugate, Y
(Z) is as shown in the following equation.

Y(Z)= _N-1 〓 ⁱ⁼⁰ R _e [G _i (-jZ ^N )・A _i (Z ^N )]・Z ^-i = 1/2 _N-1 〓 ⁱ⁼⁰ [G _i (- jZ ^N )・A _i (Z ^N ) +G _i (+jZ ^N )・A _i ^* (Z ^N )]・Z ^-i …(7) Here, G _i (−jZ ^N ) and G _i (+jZ ^N ) If each is further decomposed into two parts, G _i (-jZ ^N ) = G _i,0 (-Z ^2N ) + jZ ^-N G _i,1 (-Z ^2N ) G _i (+jZ ^N ) = G _i,0 (-Z ^2N )−jZ ^−N G _i,1 (−Z ^2N )…(8) is obtained. Since X _k (Z ^N ) is a real number in equation (6),
I _n [A _i ^* (Z ^N )] = R _e [A _Ni (Z ^N )] (where i≠0)
Then, if we transform equation (7) using this relationship and equation (8), we get 2・Y(Z)= _N-1 〓 ⁱ⁼⁰ {G _i,0 (−Z ^2N )・R _e [A _i (Z ^N )]・Z ^-i −Z ^-N・G _Ni,1 (−Z ^2N )・R _e [A _i (Z ^N )・Z ^iN
}...(9) is obtained. However, R _e [ ] and I _n [ ] are
The real and imaginary parts are shown respectively. Also, in equation (9), when i=0, the second term on the right side is zero.

As is clear from equation (8), the complex band filter G _i
(−jZ ^N ) is the two real band filters G _i,0 (−Z ^2N ) and
This can be realized by G _i,1 (−Z ^2N ).

Next, the real band filters G _i,0 (−Z ^2N ) and G _i,1 (−
A method for reducing the amount of multiplication for Z ^2N ) will be described. The transfer function G(Z) of the actual low-pass filter shown by equation (2) is expressed as follows.

G(Z)={a ₀ Z ⁰ +a ₁ Z ^-1 +a ₂ Z ^-2 +... +a _2nN-1 Z ^-(2mN-1) }/U(Z ^2N )...(10) where m is a positive integer shall be.

In equation (10), it is possible to design a filter G(Z) in which the coefficient of the numerator term satisfies the condition of the following equation.

a ₀ = 0 a _2nN-j = a _j (j = 1, 2, ..., 2m _N -1) (11) From equation (10), when i≠0, the transfer function of each sub-filter in equation (9) is The respective formulas are as follows.

G _i,0 (Z ^2N ) = {a _i Z ⁰ +a _i+2N Z ^-2N +... +a _i+(2n-2)N Z ^-(2m-2)N }/U(Z ^2N ) G _Ni,1 (Z ^2N )={a _2N-i Z ⁰ +a _4N-i Z ^-2N +… +a _2nN-i Z ^-(2m-2)N }/U(Z ^2N )(12) In equation (12), the conditional expression From (11), the following relationship holds true.

a _2N-i = a _i+(2n-2)N 〓 a _2nN-i = a _i …(13) Therefore, in equation (12), G _i,0 (Z ^2N ) and G _Ni,1 (Z ^2N )
The coefficients of the numerator terms are symmetrical to each other, and the transfer functions of the denominators are the same. Furthermore, as is clear from equation (9), since the inputs of the two sub-filters are the same, it is possible to reduce the amount of multiplication by utilizing the symmetry of the coefficients.

The present invention based on the above principle will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining the functions of the present invention. In Figure 1, 10(0), 10
(1), 10(2),..., 10(N-2), 10(N-1)
is an input terminal, 200 is a spectrum inversion circuit, 30
0 is an offset discrete Fourier processing circuit, 40
(0),40(1),40(2),...,40(N-2)40
(N-1) is Polyphase digital filter,
40 (0) 0, 40 (1) 0, 40 (1) 1, 40 (2) 0,
40(2)1,...,40(N-2)0,40(N-
2) 1,40(N-1)0,40(N-1)1
are the outputs of the polyphase digital filter, 50(1), 50(2),..., 50(N-2), 50
(N-1) is a subtracter, 600 is a multiplex circuit, 700
is the output terminal.

In Figure 1, N baseband signals X _k
(Z ^N ) (k=0, 1, ..., N-1) are the input terminals 10 (0), 10 (1), 10 (2), ..., 10, respectively.
(N-2) and 10 (N-1), and becomes an input to the spectrum inversion circuit 200. The spectrum inversion circuit 200 performs a multiplication operation of (-1) ⁿ (where n is a time index) on predetermined N/2 baseband signals to invert the spectrum of the signal. The N outputs of the spectral inversion circuit 200 are sent to an offset discrete Fourier processing circuit 30.
0 is input, and the calculation of equation (6) is performed. Of the N complex outputs of the offset discrete Fourier processing circuit 300, only the real part outputs are sent to the polyphase digital filters 40(0), 40(1), 4, respectively.
0(2),..., 40(N-2), 40(N-1).

Polyphase digital filter 40(0),
40(1), 40(2),..., 40(N-2), 40(N
-1) and subtractors 50(1), 50(2), ..., 50
(N-2), 50(N-2) performs the filter operation of equation (9). Furthermore, the output of the polyphase digital filter 40(0)0 and the subtracter 5
0(1), 50(2),..., 50(N-2), 50(N-
The output of 2) becomes the input of the multiplexing circuit 600,
After receiving delays of Z ⁰ , Z ^-1 , Z ^-2 , ..., Z ^-(N-2) and Z ^-(N-1) respectively, the output terminal 700 receives SSB-FDM.
A signal Y(Z) is obtained.

Next, the Polypheez digital filters 40(0), 40(1), 40(2),..., 40(N-2) shown in FIG.
40(N-1) will be explained in detail. The calculation formula for the polyphase digital filter is expressed by formula (9).

2・Y(Z)= _N-1 〓 ⁱ⁼⁰ {G _i,0 (−Z ^2N )・R _e [A _i (Z ^N )]・Z ^-i −Z ^-N・G _Ni,1 (− Z ^2N )・R _e [Ai(Z ^N )・
Z ^iN }...(9) However, in equation (9), when i=0, the second
The term is set to zero. From equation (9), when i≠0, input
The transfer function of the filter for R _e [A _i (Z ^N )] is
G _i,0 (−Z ^2N ) and Z ^−N・G _Ni,1 (−Z ^2N ),
This corresponds to the Polyphase digital filter 40(i). The two outputs 40(i)0 and 40(i)1 of the polyphase digital filter 40(i) are, respectively,
Transfer functions G _i,0 (−Z ^2N ) and Z ^-N・G _Ni,1 (−Z ^2N )
corresponds to the output of Also, when i=0, the second term on the right side of equation (9) is zero, so the transfer function of the polyphase digital filter 40(0) is G _i,0 (−Z ^2N )
And it is sufficient.

Next, a method for realizing the polyphase digital filter will be described. As is clear from equations (12) and (13), the transfer functions G _i,0 (−Z ^2N ) and G _Ni,1 (−
Since the coefficients of the numerator term of Z ^2N ) have symmetry (however, when i≠0) and the coefficients of the denominator are the same, we can construct a polyphase digital filter as shown in Figure 2a. Can be done.

FIG. 2a shows the configuration of the polyphase digital filter 40(i) (where i≠0) shown in FIG.

In FIG. 2a, 10 is an input terminal, and 71 and 72 are output terminals. 21, 22, 23 and 24 are multipliers for multiplying the coefficients of the numerator of the transfer function; 31, 32, 33, 34, 35 and 3;
6 is a multiplier for multiplying the coefficient of the denominator of the transfer function. Also, 41, 42,..., 47 and 48
are adders/subtractors, 51, 52,..., 55 and 56 are
Z ^-2N delay element 61 is a Z ^-N delay element.
The signal R _e [A _i (Z ^N )] input from the input terminal 10 is input to multipliers 21, 22, 23, and 24, and is multiplied by the numerator coefficient. Multipliers 21, 22, 23
and 24 outputs from adder/subtractors 41 and 48, 42 and 47, 43 and 46, 44, respectively.
and 45 inputs. On the other hand, the output of the adder/subtractor 44 becomes the input of the multipliers 31, 32, and 33, and is multiplied by the denominator coefficient. Furthermore, multiplier 3
The outputs of 1, 32 and 33 are respectively added to the adder/subtractor 4.
1, 42 and 43 are input. Adder/subtractor 4
1, delay element 51, adder/subtractor 42, delay element 5
2. The input and output of the adder/subtractor 43, delay element 53, and adder/subtractor 44 are connected in this order. Therefore, the transfer function from the input terminal 10 to the output terminal 71 receiving the output of the adder/subtractor 44 is G _i,0 (−
Z ^2N ).

On the other hand, the output of the adder/subtractor 48 becomes an input to the delay element 61, and also serves as an input to the multipliers 34, 35, and 36.
is input and multiplied by the denominator coefficient. Furthermore, the outputs of multipliers 34, 35 and 36 become inputs of adder/subtractors 45, 46 and 47, respectively. The input and output of the adder/subtractor 45, delay element 54, adder/subtractor 46, delay element 55, adder/subtractor 47, delay element 56, and adder/subtractor 48 are connected in this order.
Therefore, the transfer function from the input terminal 10 to the output terminal 72 that receives the output of the delay element 61 is Z ^-N・G _Ni,1
(−Z ^2N ).

FIG. 2b shows the structure of the polyphase digital filter 40(0) shown in FIG. In FIG. 2b, 10 and 71 indicate an input terminal and an output terminal, respectively. 21, 22
and 23 are multipliers for multiplying the coefficients of the numerator of the transfer function; 31, 32, and 33 are multipliers for multiplying the coefficients of the denominator of the transfer function; 41, 4;
2, 43 and 44 are adders/subtractors, and 51, 52 and 53 are Z ^-2N delay elements. The configuration shown in FIG. 2B is exactly the same as that of one side of the block diagram shown ⁱⁿ _FIG . In Figures 2a and b, filters G _i,0 (-Z ^2N ) and G _Ni,1
(−Z ^2N ) is shown as a third-order example, but a similar configuration can be easily considered even when the order increases.

In the block diagram for explaining the functions of the present invention shown in FIG. 1, the polyphase circuit has the configurations shown in FIGS. 2a and 2b. In Figure 2a, if the number of multipliers for multiplying the coefficient of the transfer function of the numerator term is m, the number of multipliers for multiplying the coefficient of the transfer function of the denominator term is 2×(m-1). Therefore, with the current configuration, the number of multipliers is still large. Furthermore, 2×(m−1) Z ^−2N delay elements are required. Furthermore, as is clear from FIG. 2, since the polyphase digital filter has a so-called direct type configuration, the required coefficient accuracy is increased and the hardware of each multiplier increases. Therefore, we will consider the time division multiplexing configuration of the block diagram shown in FIG. 1, and at the same time try to reduce the coefficient accuracy.

FIG. 3 is a block diagram showing an embodiment of the present invention, in which 10 is an input terminal, 20 is a spectrum inversion circuit, 30 is an offset discrete Fourier processing circuit, and 4 is a block diagram showing an embodiment of the present invention.
0 is a polyphase circuit, and 50 is an output terminal.

This figure is a block diagram when the circuit of FIG. 1 is configured in a multiplexed manner. That is, N baseband signals are time-division multiplexed and input to the input terminal 10 every _fs . Therefore, one frame is 1/f _s seconds,
During this time, N pieces of data are time-division multiplexed.
The spectrum inversion circuit 20 multiplies predetermined N/2 signals by (-1) for odd (or even) frames. The output of the spectrum inversion circuit 20 is input to an offset discrete Fourier processing circuit 30, where the following calculation is performed.

A ^R _i (Z ^N )=R _e [ _N-1 〓 ^k=0 X _k (Z ^N ) exp ( _j2π4k +1/4Ni)] (14) However, in equation ( ¹⁴ ), The output of circuit 20 is shown. Therefore, in the output of the offset discrete Fourier processing circuit 30, one frame consists of N pieces of data A ₀ ^R (Z ^N ), A ₁ ^R (Z ^N ), ..., A _N-1 ^R (Z ^N ). The signals are time-division multiplexed and input to the polyphase circuit 40. polyphase circuit 4
SSB-FDM is connected to the output terminal 50 that receives the output of 0.
I get a signal.

Next, the polyphase circuit 40 shown in FIG. 3 will be explained in detail.

FIG. 4 shows a block diagram of the polyphase circuit shown in FIG. 3, and FIG. 5 is a timing chart for explaining the operation of FIG. 4. 1
10 and 190 are input terminals and output terminals, respectively, 131, 132, 133 and 134 are
a multiplier for multiplying the coefficient of the numerator term of the transfer function,
141, 142 and 143 are multipliers for multiplying the coefficients of the denominator term of the transfer function;
153, 154, 155, 156 and 157 are
Z ^-N delay element, 161, 162, 163, 16
4, 165, 166 and 167 are adders/subtractors, 1
71, 172, 173 and 174 are switches,
120 and 180 are array conversion memories. In addition, 200 is a delay element, and 300 is an input data
2 ^-l is a scaler for multiplying. However, l is a positive integer.

The output of the offset discrete Fourier processing circuit 30 shown in FIG. 3 is input to the input terminal 110. Here, it is assumed that the frame configuration of the input terminal 10 is a timing chart as shown in FIG. 5A. The numbers in Figure 5A are R _e [A _c (Z ^N )] in equation (6).
It corresponds to i. 1 frame (=Z ^-N =1/
f _s ) is assumed to be time-division multiplexed N pieces of data. The data input to the input terminal 110 is
It is input to the array conversion memory 120. In the array conversion memory 120, for the data input to the input terminal 110, even (or odd) frame data is converted into (N-1) pieces of data in reverse order as shown in the timing chart of FIG. 5B. Perform array conversion. The numbers in Figure 5B are i in R _e [A _i (Z ^N )] of equation (6).
It corresponds to At this time, the order of data in odd (or even) frames is the same as the input data order. The output of the array conversion memory 120 becomes the input of the multiplier 131 and the delay element 200.
The coefficients of multipliers 131, 132, 133, and 134 are 2 ^l ·a _i , 3 which are 2 ^l times the zero-order coefficient of the numerator term of the transfer function G _i,0 (Z ^2N ) shown in equation (12), respectively. Order coefficient・
a _i+6N , a first-order coefficient a _i+2N and a second-order coefficient a _i+4N , each of which changes in a time-division manner N times within one frame.

Here, since the absolute value of the 0th-order coefficient a _i is smaller than that of the first, second, and third-order coefficients, after scaling only a _i by a factor of 2 ^l , the other coefficients If quantization is performed in the same way, it becomes possible to reduce the required coefficient precision. Instead, as shown in FIG. 4, the output of the multiplier 131 is used as the input.
Requires 300 scalers of 2 ^-l times. Furthermore, the scaler 30 is configured so that the amount of delay from the output of the array conversion memory to the output of the scaler 300 is the same as the amount of delay from the output of the array conversion memory 120 to each output of the multipliers 132, 133, and 134.
A delay element 200 is required to compensate for the delay of 0. Therefore, the output of the delay element 200, which receives the output of the array conversion memory 120, is sent to the multiplier 13.
2, 133 and 134 are input.

The output of the scaler 300 is input to the Z ^-N delay element 151 via the switch 171, and at the same time is input to the adder/subtractor 167. Multiplier 13
The output of 2 is input to the adder/subtracter 161 and, at the same time, is also input to the adder/subtracter 166 via the switch 174. The output of multiplier 133 is
The signal is input to the adder/subtractor 162 via the adder/subtractor 72 and at the same time, it is also input to the adder/subtractor 165 . Further, the output of the multiplier 134 is input to the adder/subtracter 163 and at the same time, is also input to the adder/subtracter 164 via the switch 173. Further, the output of the adder/subtractor 167 is input to multipliers 141, 142, and 143. Each output of multipliers 141, 142 and 143 is input to adder/subtractor 161, 163 and 165, respectively.

Here, multipliers 131, 132, 133 and 134 are G _i,0 (-Z ^2N ) and G _Ni,1 (-
This is a multiplier for multiplying the coefficient of the numerator term of Z ^2N ). However, as mentioned above, the coefficient of the multiplier 131 is the original value multiplied by 2 ^l . As is clear from equations (12) and (13), G _i,0 (−Z ^2N ) and G _{Ni, 1} (−Z ^2N )
Since the coefficients of the numerator terms have symmetry with each other, it is possible to reduce the number of multiplications to 1/2.
It is necessary that the coefficients of multipliers 131, 132, 133 and 134 change in a time-sharing manner. On the other hand, multipliers 141, 142 and 143 are G _i,0 in equation (9)
(−Z ^2N ) and G _Ni,1 (−Z ^2N ) by the coefficients of the denominator terms. As is clear from equation (12), the coefficients of the denominator terms of G _i,0 (−Z ^2N ) and G _Ni,1 (−Z ^2N ) are the same and do not depend on i, so the multipliers 141 and 142 The coefficients of and 143 may always be constant.

When configured as shown in Fig. 4, the output of the filter G _i,0 (-Z ^2N ) of the first term on the right side of equation (9) is virtually expressed in the form as shown in the timing chart shown in Fig. 5C. appears at the output of the adder/subtractor 167. Also, since the second term on the right side of equation (9) is zero when i=0, switches 171, 172, 173 and 174 are open at this time. When i=1, 2, . . . , N-1, switches 171, 172, 173 and 174 operate to close. Filter Z ^-N of the second term on the right side of equation (9)
The output of G _Ni,1 (-Z ^2N ) virtually appears at the output of the adder/subtractor 167 in a form like the timing chart shown in FIG. 5D. Actually, adder/subtractor 1
61, 162, 163, 164, 165, 166
and 167, the operation on the right side of equation (9) is performed and output to the adder/subtracter 167.

The numbers shown in FIG. 5C, D, and E correspond to i in equation (5). The output of the adder/subtractor 167 is input to the array conversion memory 180. Array conversion memory 180
Then, for even (or odd) frames, an array transformation that is completely opposite to that of the array transformation memory 120 is performed.

Therefore, when the right side of equation (9) is expressed as the following equation, 2・Y(Z)= _N-1 〓 ⁱ⁼⁰ Z ^-i Y _i (Z ^N )...(15) At the output terminal 190 is N Y _i (Z ^N ) in Figure 5F
A timing chart like the one shown is output. In Figure 5F, the numbers are Y _i (Z ^N ) of equation (15)
It corresponds to i.

Although FIG. 4 shows a third-order polyphase digital filter to simplify the explanation, a similar configuration can be easily considered even when the number of orders increases. Furthermore, depending on the characteristics of the designed polyphase digital filter, the number of multipliers to be scaled may be not just one but multiple in order to shorten the required coefficient precision; in this case, Also, since only one delay element is required to compensate for the delay of the scaler, the increase in hardware is only the increase in the number of scalers. In addition, the configuration of the scaler is as follows in the serial calculation format using this complement representation:
This can be easily achieved by simply inhibiting the flip-flop clock.

As described above, if the present invention is used, the amount of multiplication required for a polyphase digital filter can be reduced to half that of the conventional one, and the coefficient accuracy can also be reduced. A multiple signal modulation device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the functions of the present invention.
0 (N-2) and 10 (N-1) are input terminals,
200 is a spectrum inversion circuit, 300 is an offset discrete Fourier processing circuit, 40(0), 40(1),
40(2),...,40(N-2) and 40(N-
1) Polyphase digital filter, 50
(1), 50(2), ..., 50(N-2) and 50(N
-1) is a subtracter, 600 is a multiplexing circuit, and 700 is an output terminal. FIG. 2 is a block diagram for explaining the polyphase digital filter of FIG. 1, where 10 is an input terminal, 21, 22, 23, 24, 31, 32,
33, 34, 35 and 36 are multipliers, 41, 4
2, 43, 44, 45, 46, 47 and 48 are adders/subtractors; 51, 52, 53, 54, 55 and 56 are Z ^-2N delay elements; 61 is a Z ^-N delay element;
71 and 72 are output terminals. FIG. 3 is a block diagram showing an embodiment of the present invention, in which 10 is an input terminal, 20 is a spectrum inversion circuit, 30 is an offset discrete Fourier processing circuit, and 4 is a block diagram showing an embodiment of the present invention.
0 is a polyphase digital filter, and 50 is an output terminal. FIG. 4 is a block diagram for explaining the polyphase digital filter of FIG. 3, in which 110 is an input terminal, 120 is an array conversion memory, 131, 13
2,133,134,141,142 and 14
3 is a multiplier, 151, 152, 153, 154,
155, 156 and 157 are Z ^-N delay elements;
161, 162, 163, 164, 165, 16
6 and 167 are adders/subtractors, 171, 172 and 173 are switches, 180 is an array conversion memory,
190 is an output terminal, 200 is a delay element, and 300 is a scaler. FIG. 5 is a timing chart for explaining the operation of FIG. 4.

Claims (1)

[Claims] 1 a spectrum inversion circuit, an offset discrete Fourier processing circuit that receives the output signal of the spectrum inversion circuit, and a first circuit that receives the real part output signal of the offset discrete Fourier processing circuit and performs array conversion of time-division multiplexed data; an array conversion memory; a digital filter circuit that receives the output signal of the first array conversion memory as an input and performs arithmetic operations on a plurality of digital filters by time-division processing; The second part performs array conversion of the data
In the single sideband frequency division multiplexing signal modulation device for obtaining an N channel single sideband frequency division multiplexed signal from an N channel baseband signal by digital signal processing using a polyphase circuit consisting of an array conversion memory and a polyphase circuit comprising A circuit includes a first group of m ₁ (positive integer) multipliers receiving the output signal of the first array conversion memory;
Receives the output signal of _one first multiplier group
m ₁ scaler, a first delay element that receives the output signal of the first array conversion memory and compensates for the delay of the scaler, and m ₂ (positive an integer) second multiplier group, (m ₁ +m ₂ ) switches that receive the outputs of the first and second multiplier groups, respectively, a 1-sample delay element, and an adder that receives the output thereof. The delay element/adder unit consisting of (2m ₁ + 2m ₂
-1) comprising a group of delay elements _and adders connected in cascade, and a third group of n third multipliers that receive the outputs of the delay elements and _adder group; The output of one of the switches is the delay element.
In addition to supplying the input of the adder group, the remaining (m ₁
The outputs of the +m ₂ -1) switches are respectively supplied to the adders of the even-numbered units of the (2m ₁ +2m ₂ -1) delay elements/addition units, and
The m ₁ scaler outputs and the m ₂ second multiplier group outputs are supplied to the odd-numbered unit adder of the (2m ₁ +2m ₂ -1) delay element/adder group; Furthermore, the outputs of the n third multiplier groups are each configured to be supplied to adders in units two units apart from the rear of the delay element/adder unit group, and the _m multiplier groups and the _m2 second multipliers are each supplied with coefficients that change in a time-division manner to perform multiplication of the numerator coefficients of the plurality of digital filters, and the n third multipliers 1. A single sideband frequency division multiplex signal modulation device, characterized in that said digital filter circuit is configured by supplying a fixed coefficient to each group and performing multiplication by denominator coefficients of said plurality of digital filters.