JPS567544A - Modulator for single-sideband frequency division multiplex signal - Google Patents

Modulator for single-sideband frequency division multiplex signal

Info

Publication number
JPS567544A
JPS567544A JP8308479A JP8308479A JPS567544A JP S567544 A JPS567544 A JP S567544A JP 8308479 A JP8308479 A JP 8308479A JP 8308479 A JP8308479 A JP 8308479A JP S567544 A JPS567544 A JP S567544A
Authority
JP
Japan
Prior art keywords
circuit
frequency division
output
frame
division multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8308479A
Other languages
Japanese (ja)
Other versions
JPS6324333B2 (en
Inventor
Akira Kanemasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8308479A priority Critical patent/JPS567544A/en
Publication of JPS567544A publication Critical patent/JPS567544A/en
Publication of JPS6324333B2 publication Critical patent/JPS6324333B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details
    • H04J1/04—Frequency-transposition arrangements
    • H04J1/05—Frequency-transposition arrangements using digital techniques

Abstract

PURPOSE:To reduce the number of times of multiplication and to decrease the scale of the hardware, by sequentially connecting the spectrum inversion circuit, offset discrete Fourier processing circuit and polyphase circuit. CONSTITUTION:The base band signals of N sets are in time-sharing and multiplex at the input terminal 10 and are input every sampling frequency fs. Accordingly, one frame is 1/fs seconds. In the spectrum inversion circuit 20, the multiplication of (-1) is made to an odd or even number frame to the signals of N/2 sets predetermined. In the offset discrete Fourier processing circuit 30, the operation expressed in equation (14) is made. Where; XK(Z<n>) in equation (14) is the output of the circuit 20. Accordingly, in the output of the circuit 30, N sets of data of A0R(Z<n>), A1R(Z<n>),...An-1R(Z<n>) are in time sharing multiplex in one frame. This output is obtained at the terminal 50 via the polyphase circuit 40 as single-sideband frequency division multiplex signal.
JP8308479A 1979-06-29 1979-06-29 Modulator for single-sideband frequency division multiplex signal Granted JPS567544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8308479A JPS567544A (en) 1979-06-29 1979-06-29 Modulator for single-sideband frequency division multiplex signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8308479A JPS567544A (en) 1979-06-29 1979-06-29 Modulator for single-sideband frequency division multiplex signal

Publications (2)

Publication Number Publication Date
JPS567544A true JPS567544A (en) 1981-01-26
JPS6324333B2 JPS6324333B2 (en) 1988-05-20

Family

ID=13792305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8308479A Granted JPS567544A (en) 1979-06-29 1979-06-29 Modulator for single-sideband frequency division multiplex signal

Country Status (1)

Country Link
JP (1) JPS567544A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177291U (en) * 1985-04-24 1986-11-05
JPH1011571A (en) * 1996-06-20 1998-01-16 Mitsubishi Electric Corp Binary picture multi-valuing and reducing processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528356Y2 (en) * 1988-03-18 1993-07-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177291U (en) * 1985-04-24 1986-11-05
JPH0514073Y2 (en) * 1985-04-24 1993-04-14
JPH1011571A (en) * 1996-06-20 1998-01-16 Mitsubishi Electric Corp Binary picture multi-valuing and reducing processor

Also Published As

Publication number Publication date
JPS6324333B2 (en) 1988-05-20

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