JPH1011571A - Binary picture multi-valuing and reducing processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a binary picture reducing processor for speedily realizing the processing of reducing a binary picture by making multilevel by minimum number of arithmetic times whatever filter is used. SOLUTION: A 2N:1 multi-valuing and reducing part 14 filters the binary picture expressed by one pixel and one bit through the use of a filter for 2:1 reduction to generate multilevel to accelerate processing until reducing an inputted picture to 2:1. In addition, the processing is repeated by the number of times (N-1 times) decided by a thinning rate dividing control part 12 to generate an M-level picture of 2N:1 reduction to generate an M-level reduced picture by small number of product sum arithmetic times. In addition, an additional reducing processing part 17 reduce-processes the picture generated by the part 14 by the magnification decided by the part 12 to generate the M-level reduced picture of an inputted and desired magnification.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention realizes high-speed processing for reducing a binary image to high image quality by allowing generation of halftones, mainly for display on a display having multi-gradation display capability. The present invention relates to a binary image multi-level reduction processing device.

[0002]

2. Description of the Related Art FIGS. 17 (a) and 17 (b) show, for example,
FIG. 17 is a block diagram of a binary image enlarging / reducing apparatus disclosed in Japanese Unexamined Patent Application Publication No. 7-37272, in which FIG. Unit, 125 is an output control unit, 1
26 is an overall control unit. The binary image input to the input control unit 122 is subjected to enlargement or reduction processing only in the vertical direction by a vertical OR reduction unit 123, and the image generated here is subjected to a horizontal enlargement / reduction unit 124. Performs enlargement or reduction processing only in the horizontal direction to obtain an image enlarged or reduced in both directions. Here, the output control unit 1
25, and stops the enlargement / reduction processing when outputting the image obtained by the horizontal enlargement / reduction unit 124, and transfers the control to the input control unit 122 when performing further enlargement / reduction processing. 124, the output control unit 12
Enlargement or reduction processing is performed on the image output in step 5.

In such a binary image enlarging / reducing apparatus, a vertical or horizontal logical OR reduction processing section comprising a logical operation section 127 and a register 128 as shown in FIG. To generate an enlarged or reduced binary image.

[0004]

SUMMARY OF THE INVENTION As described above, the conventional 2
In the value image enlargement / reduction apparatus, since both the input and the output are binary images, the processing speed can be easily increased by realizing the horizontal / vertical direction enlargement / reduction processing using the logical OR operation. . However, in a process of generating a halftone in a binary image and generating an enlarged / reduced image as a multivalued image (multivalued enlargement / reduction process), if this is to be realized by a logical OR operation, the number of gradations is reduced. With the increase, the logical formula became very complicated, or the conversion could not be expressed by the logical formula, and it took time and effort to change the conversion formula.

If the filtering portion of the reduction process is replaced by a process based on a product-sum operation from a logical operation, a multi-valued enlargement / reduction process using an arbitrary filter can be performed only by changing the filter coefficient. Therefore, implementation using a DSP (Digital Signal Processor) or the like becomes possible, and versatility is remarkably improved. In particular, in the case of implementation using s / w, since a product-sum operation is used, a logical operation is performed. However, there is a problem that the processing speed is dramatically increased as compared with the conventional method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and realizes a process of reducing a binary image by increasing the number of gradations with a minimum number of operations even when any filter is used. An object of the present invention is to provide a high-speed apparatus for performing a binary image reduction process for enabling the image processing.

[0007]

According to the present invention, there is provided a binary image multi-valued reduction processing apparatus which receives an input reduction rate (thinning rate; a:
1) The 2 ^N: 1 and a / 2 ^N: divided into 1, the latter of thinning ratio a / 2 ^N: 1 to P: Q (P, Q are relatively prime,
A thinning rate division control unit approximating to (2: 1), and 2:
A filter selection unit for selecting a 2: 1 reduction filter used for the 1 reduction processing and a P: Q reduction filter used for the P: Q reduction processing, and a 2: 1 reduction filter using the selected 2: 1 reduction filter. 2 in the repetitive processing of the multi-valued reduction processing of 1
^N: 2 ^N performs first multi-value reduction processing: performs reduction processing for Q: per each of the longitudinal and transverse direction P with Q reduction filter: 1 and multilevel reduction processing unit, P selected Thinning rate ≠ 2: 1
, And in the case of P: Q ≠ 1: 1, the input binary image is first subjected to multi-level reduction processing to 2 ^N : 1 and then P:
The image processing apparatus further includes a multi-level reduction processing control unit that controls the input binary image to perform the multi-level reduction processing at 2 ^N : 1 when P: Q = 1: 1.

[0008] Further, as a 2 ^N : 1 multilevel reduction processing section,
The vertical or horizontal direction of the binary image represented by 1 bit per pixel is multi-valued and reduced by 2: 1 to generate an image of 1 pixel M gradation and expressed by 1 pixel B (≧ 2 ^M ) bits. A vertical or horizontal 2: 1 multi-level reduction processing unit for outputting an image, and an M-gradation image output from the vertical or horizontal 2: 1 multi-level reduction processing unit in a horizontal or vertical 2: 1 ratio. Horizontal or vertical 2: 1 reduction processing unit for reduction processing, and vertical 2: 1 reduction processing for reducing the output image of the horizontal or vertical 2: 1 reduction processing unit alternately vertically and horizontally to 2: 1. A 2: 1 repetition reduction processing unit that repeatedly applies the direction 2: 1 reduction processing (N−1) times is used.

Further, the reduction filter selected by the filter selection section is a one-dimensional filter.

The input binary image is represented by P: Q (≠ 2: 1).
And the pre-multi-value reduction processing unit for reducing multi-valued to, 2: 2 ^N by repeating the first reduction process: and a first reduction processing unit: 2 ^N to reduce the image to a desired magnification reduced to 1 Things.

Also, as a 2 ^N : 1 reduction processing section, the M gradation image expressed by one pixel B (≧ 2 ^M ) bits obtained by the pre-multi-valued reduction processing section is alternately arranged in the vertical and horizontal directions. A 2: 1 repetition reduction processing unit that applies N-times 2: 1 reduction processing in the vertical direction and N-times 2: 1 reduction processing in the horizontal direction is used.

[0012] A vertical 2: 1 multi-level reduction processing section, a horizontal 2: 1 multi-level reduction processing section, a vertical 2: 1 reduction processing section, and a horizontal 2: 1 reduction processing section are used as filters. By using the polyphase expression, filtering operations to obtain pixel values that are discarded by the thinning process are eliminated in advance, and the number of product-sum operations is minimized within a range that does not depend on the filter shape and filter coefficient value. It has been reduced to:

The apparatus further includes a filter symmetry determining section for determining the symmetry of the filter selected by the filter selecting section, wherein the determination result of the filter symmetry determining section is even symmetric,
When the filter length is an odd number, the fact that even symmetry holds for each polyphase component obtained by polyphase representation of the filter is used, and the determination result in the filter symmetry determination unit is even symmetric. In addition, when the filter length is an even number, the fact that the polyphase components obtained by expressing the filter in a polyphase form mirror images of each other is used.

Further, the product-sum operation in filtering for converting a binary image into a multi-valued image and reducing it is replaced with a table conversion.

Further, the product-sum operation in all the filterings is replaced with a table conversion.

Also, it is determined whether or not all the pixel values in the filtering range of the target pixel are “white”. If “all white”, the reduction processing by filtering is not performed and “0” is set as the output value, and If it is not 0 ", a filtering target pixel control unit for performing a reduction process by filtering is provided.

Further, the pre-multi-valued reduction processing unit may perform a pre-reduction processing based on the SPC method or the projection method for generating a binary reduced image from a binary image using a high-speed binary image reduction processing based on the SPC method or the projection method. Part.

Further, a filter having an integer coefficient (in general, the norm is not 1) is used, and each time filtering is performed, a normalizing unit that divides by a filter norm, or at the end of filtering, collectively divides by (filter norm) ^2N It is provided with a normalization unit for normalizing.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a block diagram showing the configuration of a first embodiment of a binary image multi-level reduction processing high-speed realization apparatus according to the present invention. The binary image signal input unit 11 includes an image reading device such as a character generation circuit, a scanner, a facsimile device, or a file of an image on a PC or WS, and converts a monochrome binary image into an image of binary image raw data. The input is received as data in a format, that is, one-bit 1-bit representation data, and this is sent to the 2 ^N : 1 multi-value reduction processing unit 14. The thinning rate division control unit 12 receives a user's desired image reduction rate as an input, and
a, the thinning rate a: 1) is 1 / Nth power of 2, ie, 2
^N : 1 and 1 / (a ÷ 2 N), that is, a / 2
^N : 1 and the latter thinning rate a / 2 ^N : 1
By P: Q (P and Q are relatively prime positive integers, P> Q, P: Q
≠ 2: 1). The filter selection unit 13
The tap length and the filter coefficient of a filter used in advance according to a thinning rate are used for a 2: 1 reduction two-dimensional filter used for ^N : 1 reduction processing and a P: Q reduction two-dimensional filter used for P: Q reduction processing, respectively. Is searched for a thinning rate that matches 2: 1, P: Q, and a filter coefficient corresponding to the thinning rate that matches that is selected from the table. Table 1 shows an example of the filter selection table.

[0020]

[Table 1]

Table 1 shows that 2: 1 corresponds to a thinning ratio of 2: 1.
This indicates that the reduction filter has, for example, a tap length of 3 taps and a filter coefficient having a value as shown in the table. Next, an example of a 4: 3 reduction processing filter corresponding to a thinning ratio of 4: 3 is shown. In addition,
A 2: 1, P: Q (P and Q are positive integers) reduction filter is, for example, to reduce the frequency band of an image to 、 and Q / P, respectively.
This is a low-pass filter that restricts The 2 ^N : 1 multi-level reduction processing section 14 includes a 2: 1 multi-level reduction processing section 15, a 2: 1 reduction processing section 16 a and a counter 16 b as its constituent elements.
And a 2: 1 iterative reduction processing unit 16. 2: 1
The multi-valued reduction processing unit 15 uses the 2: 1 reduction filter selected by the filter selection unit 13 to express two pixels represented by one bit per pixel received as an input from the binary image signal input unit 11. The value image is subjected to filtering for 2: 1 reduction processing using, for example, a convolution circuit of a FIR filter or a DSP as shown in FIG. 2 so that each pixel of the input image expressed in black and white is converted to black and white. Pixel values having halftone values other than the above, and the image size is 2: 1
Is reduced. Such a process of generating a halftone other than black and white from an image expressed in black and white binary is called multi-gradation or multi-level conversion, etc., in which a multi-gradation is generated in a binary image. The process of reducing the size is called a multi-value reduction process. Note that the image at the time of input to the 2: 1 multi-level reduction processing unit 15 is represented by one bit per pixel, but the image at the time of output has a predetermined value as the number of halftone levels to be output. M, that is, an image expressed by one pixel B (≧ 2 ^M ) bits by the number of bits sufficient to express the M gradation image. In the 2: 1 repetition reduction processing unit 16 following the 2: 1 multilevel reduction processing unit 15, the 2: 1 reduced image (gradation number = M, image data Is 1
For the pixel B (≧ 2 ^M ) bit representation, a filter selection unit 13 similar to that used in the 2: 1 multi-value reduction processing unit 15
The reduction processing using the 2: 1 reduction filter selected in step 2b is performed by the 2: 1 reduction processing section 16a, and the same processing is repeatedly performed, and the counter 16b in which the number of processing has been initialized to 0
By counting each time the same processing is performed and performing the processing until it reaches (N-1) times, M gradation 2 ^N : 1 reduced image (gradation number = M, image data is one pixel B (≧ 2 ^M ) Bit representation). The image thus obtained is the output image of the 2: 1 repetition reduction processing unit 16 and, at the same time, the output of the 2 ^N : 1 multilevel reduction processing unit 14. The input / output of the 2: 1 reduction processing unit 16a receives as an input an M gradation image represented by B (≧ 2 ^M ) bits per pixel, and reduces the size by half.
In this manner, an M gradation image represented by one pixel B (≧ 2 ^M ) bits is output. Then, 2 ^N : 1
The image output from the multi-level reduction processing unit 14 is input to the additional reduction processing unit 17. The additional reduction processing unit 17
^{When the} 2 ^N : 1 multi-level reduction processing is performed by the ^N : 1 multi-level reduction processing unit 14, an image reduced to 2 ^N : 1 (one pixel B (≧ 2 ^M ) bits is expressed. A / 2 output from the thinning rate division control unit 12 for the M gradation image)
^N: P 1 is approximated by integer ratio: subjected to reduction processing for realizing the thinning rate of Q, 2 ^N: 2 in 1 multilevel reduction processing unit 14
^N : 2 when multi-level reduction processing is not performed
For a black-and-white binary image represented in the 1 bit / pixel representation format input to the value image signal input unit 11, 2 ^N :
(1) A reduced image having a reduction ratio approximating a user-desired reduction ratio a: 1 input to the thinning-out ratio division control unit 12 is subjected to a reduction process for realizing a reduction ratio similar to the case where the multi-valued reduction process is performed. (M gradation image expressed by one pixel B (≧ 2 ^M ) bits) is generated. The multivalued reduced image generated by the 2: 1 repetitive reduction processing unit 16 is input to the image display unit 19 and displayed on the display as an output. It should be noted that the image display section 19 may be any display having multi-gradation display capability, and is not limited to a PC or WS display. When 2 ^N : 1 N1: 1, the 2 ^N : 1 multi-level reduction processing unit 14 performs the 2 ^N : 1 multi-level reduction processing, where P: In the case of Q = 1: 1, the generated multi-valued image is passed to the image display unit 19 without performing the additional reduction processing by the additional reduction processing unit 17, and P: Q ≠ 1:
In the case of 1, the 2 ^N : 1 multilevel reduction processing section 14 and the additional reduction processing section 17 are controlled so that the result of the additional reduction processing performed by the additional reduction processing section 17 is passed to the image display section 19.
^{In the case of N} : 1 = 1: 1, 2 ^N : 1 multi-level reduction processing section 14
No reduction processing is performed. Here, when P: Q = 1: 1, the additional reduction processing unit 17 does not perform the additional reduction processing, and
The image data expressed in the data format of one bit per pixel (data format of a binary image) is converted into image data having the data format of a multi-valued image and passed to the image display unit 19, where P: Q ≠ 1: 1 In this case, the 2 ^N : 1 multi-level reduction processing unit 14 generates a reduced image having a data format of a multi-level image which is multi-level reduced to P: Q directly from image data of a data format of 1 bit per pixel.
In addition, it controls the additional reduction processing unit 17 so as to control the input image to multi-value reduction processing at a desired reduction ratio with high efficiency.

In the first embodiment, the 2 ^N : 1 multi-valued reduction processing section 14 explicitly converts an image expressed in the binary image format into an M gradation image and then performs the reduction processing. This is taken into the multi-valued reduction process without receiving, and a 1-bit 1-bit representation is received as an input.
The speed is increased by performing a filtering operation for realizing (≧ 2 ^M ) bit representation output. Furthermore, as a filtering method used in the multi-value reduction processing unit 14,
The 2: 1 repetition reduction processing section 16 is used for 2: 1 reduction processing.
By using the repetition processing of the two-dimensional convolution using the two-dimensional filter (the number of repetition N times), the two-dimensional for 2 ^N : 1 reduction processing can be performed without using the repetition processing such as the 2: 1 repetition reduction processing unit 16. 2 using a filter
Compared to the case where dimensional convolution is used, the number of times of multiplication can be reduced, that is, filtering of the entire image can be realized at high speed. Table 2 shows the relationship between the filtering method and the number of times of multiplication.

[0023]

[Table 2]

In Table 2, L is the filter length (changes in accordance with the reduction ratio, matches L ₂ when the reduction is 2: 1), L ₂ is the filter length for 2: 1 reduction, and 2 ^D is the thinning ratio , D are positive integers. From the following equation 1, it can be seen that the two-dimensional repetition processing is faster than the two-dimensional processing.

[0025]

(Equation 1)

Embodiment 2 FIG. FIG. 3 is a block diagram showing Embodiment 2 of the present invention. In the second embodiment,
2 ^N : 1 multi-level reduction processing section 14 in the first embodiment,
2 and an additional reduction processing unit 17 as shown in FIG. 3 ^N: 1
It is changed to a multi-value reduction processing unit 21 and an additional reduction processing unit 25. Also, the filter selection unit 13 of the second embodiment uses a one-dimensional filter selection table instead of the two-dimensional filter selection table in the first embodiment. The reduction processing has been speeded up. Table 3 shows an example of a one-dimensional filter selection table.

[0027]

[Table 3]

In FIG. 3, the 2 ^N : 1 multi-valued reduction processing unit 21 firstly receives the 2: 1 multi-valued reduction processing unit 22 in the vertical direction.
By applying a one-dimensional filter for 2: 1 reduction processing to the vertical direction of the input binary image expressed in the format of one bit per pixel, multi-gradation is generated, and , An M gradation image expressed by 1 pixel B (≧ 2 ^M ) bits reduced to 1: 1. Subsequently, the horizontal 2: 1 reduction processing unit 23 applies two pixels to the horizontal direction of the 1-pixel B (≧ 2 ^M ) -bit M gradation image obtained by the vertical 2: 1 multi-value reduction processing unit 22. 1: 1 reduction processing is performed in the horizontal direction while applying a one-dimensional filter for reduction processing. Next, the 2: 1 repetition reduction processing unit 24 applies a vertical 2: 1 reduction processing unit 24a to the image generated by the horizontal 2: 1 multilevel reduction processing unit 23 in the vertical direction of the image. 1 reduction processing, followed by 2: 1 horizontal reduction processing by the horizontal 2: 1 reduction processing unit 24b, and such processing is performed by the counter 16 of the first embodiment.
The image is reduced to a desired magnification by repeating this process until the counter 24c, which operates in the same manner as b, counts up to N-1 times. As shown in FIG. 3, the additional reduction processing unit 25 first applies an image to the image input by the vertical additional reduction processing unit 25 a using the filter selected by the filter selection unit as in the first embodiment. Of the image in the vertical direction, and then the horizontal additional reduction processing section 25b performs the horizontal reduction processing of the image in the same manner, thereby generating an image to be output on the image display section. I do. In the second embodiment, instead of performing two-dimensional convolution on a two-dimensional image to be processed using a two-dimensional filter,
By performing one-dimensional convolution in the vertical and horizontal directions of a two-dimensional image using a two-dimensional filter, not only the number of product-sum operations required to obtain a filtering result is reduced, but also the vertical and horizontal directions are reduced. Immediately after filtering (convolution) in each direction or by performing reduction processing in each direction at the same time as filtering, for example, when filtering is performed in the vertical and horizontal order, the number of pixels to be subjected to horizontal filtering, which is the subsequent stage, is reduced, and the product-sum operation is performed. The speed of the reduction process is further reduced by further reducing the number of times. As in the case of the first embodiment, Table 2 shows the number of calculations (number of multiplications) of the filtering by the repetitive processing using the one-dimensional filter (one-dimensional separation filter). Equation 1 shows that one-dimensional repetition processing is faster than one-dimensional processing, and equation 3 shows that one-dimensional repetition processing is faster than two-dimensional repetition processing. Is the fastest.

[0029]

(Equation 2)

[0030]

(Equation 3)

According to Table 2 and Equations (1) to (3), a one-dimensional filter is used instead of a two-dimensional filter. It is shown that the number of operations can be reduced by repeating the processing of. In addition,
The order of processing in the vertical / horizontal direction in the 2: 1 repetition reduction processing unit 24 and the additional reduction processing unit 25 can be switched.

Embodiment 3 FIG. FIG. 4 is a block diagram showing Embodiment 3 of the present invention. In the third embodiment,
In the first embodiment, the 2 ^N : 1 multi-valued reduction processing unit 14 performs 2 ^N : 1 multi-valued reduction processing, and then the additional reduction processing unit 1
The order in which the desired reduced image was obtained by performing the additional reduction processing in step 7 is changed. First, the binary image represented in the data format of one bit per pixel by the pre-multi-valued reduction processing unit 31. Is reduced to P: Q and one pixel B (≧ 2
^M ) An M gradation reduced image in bit representation is generated, and then reduced to 2 ^N : 1 by repeating the 2: 1 reduction processing in the 2 ^N : 1 reduction processing unit 32 to obtain a desired reduced image. Generate Except for the above, the configuration is the same as that of the first embodiment.

Embodiment 4 FIG. FIG. 5 is a partial block diagram showing Embodiment 4 of the present invention. In the fourth embodiment, the processing speed is improved by repeating the one-dimensional reduction processing for each direction in the second embodiment, as compared with the repetition processing using the two-dimensional filter described in the first embodiment. The pre-multivalued reduction processing units 31 and ^2N : 1 reduction processing unit 32 in the third embodiment are changed to pre-multivalued reduction processing units 41 and ^2N : 1 reduction processing unit 42 as shown in FIG. It was done. In FIG. 5, the pre-multivalued reduction / reduction processing unit 41 realizes reduction processing separately for each direction using a vertical pre-multivalued reduction processing unit 41a and a horizontal pre-reduction processing unit 41b. Reduce the number of product-sum operations and increase speed. In the 2 ^N : 1 reduction processing unit 42,
This can be realized by repeating vertical and horizontal reduction processing by the vertical 2: 1 reduction processing unit 42a and the horizontal 2: 1 reduction processing unit 42b, and is two-dimensional as in the case described in the second embodiment. Rather than performing repetitive processing using a filter, the number of product-sum operations in filtering is reduced,
Speed up the binary image multi-level reduction processing. Note that the processing order in the vertical and horizontal directions in the repetitive processing can be changed.

Embodiment 5 FIG. 6 is a partial block diagram showing Embodiment 5 of the present invention, which realizes high-speed processing by polyphase expression. In the fifth embodiment, the 2 ^N : 1 multi-valued reduction processing unit 2 in the second embodiment
As shown in FIG. 6, the 1 ^N and the additional reduction processing unit 25 have a 2 ^N : 1 multi-value reduction processing unit 51 and an additional reduction processing unit 55, each of which is a configuration of a reduction process in which the speed is increased using polyphase expression. It has been changed to. In FIG.
The 2 ^N : 1 multi-valued reduction processing unit 51 includes a vertical 2: 1 multi-value reduction processing unit 52 using polyphase expression, a horizontal 2: 1 reduction processing unit 53 using polyphase expression, and a polyphase expression usage It comprises a vertical 2: 1 reduction processing section 54a, a horizontal 2: 1 reduction processing section 54b utilizing polyphase expression, and a 2: 1 repetition reduction processing section 54 comprising a counter 54c. The inputs and outputs of these components are the same as those of the components of the 2 ^N : 1 multilevel reduction processing unit 21 of the second embodiment. The operation of the counter 54c is the same as that of the counter 24c of the second embodiment. The additional reduction processing section 55 includes a vertical additional reduction processing section 55a using polyphase expression and a horizontal additional reduction processing section 55b using polyphase expression. And
The input and output of these components are the same as those of the vertical additional reduction processing unit 25a and the horizontal additional reduction processing unit 25b of the second embodiment.

In the second and fourth embodiments, the vertical 2: 1 multilevel reduction processing section or the horizontal 2: 1 multilevel reduction processing section, the vertical 2: 1 reduction processing section, the horizontal 2: (1) The reduction process is such that the reduction processing unit performs filtering by the filtering unit and then thins out by the thinning reduction processing unit.
In this method, since filtering is performed on all pixels, as is apparent from FIG. 7 showing, for example, a 2: 1 reduction process, a product-sum operation 500b2 for obtaining a pixel value to be discarded as a result of the thinning process Is also being done. Here, FIG. 7 shows pixels that need to be filtered and pixels that do not need to be filtered, and only the sum-of-products operation 500b1 is required as a result of the reduction process, and the sum-of-products operation 500b2 completely reduces the image quality of the reduced image. Since there is no influence, removal in advance can greatly reduce the number of product-sum operations. Polyphase representation is a theoretical method that omits all multiplications that are not necessary to obtain a reduced image. FIG. 8 shows a filtering system using the polyphase expression. FIG. 8A shows a reduction processing system using normal filtering thinning, FIG. 8B shows a reduction processing system in a case where filtering is expressed in polyphase, and FIG.
(C) shows a reduction processing system in a case where the speed is increased by using the polyphase expression. 8, reference numeral 56 denotes a filter, 5
7 is a 2: 1 decimation processing unit, 58 is a polyphase component 0 of the filter, 59 is a polyphase component 1 of the filter, 66 is a filter obtained by up-sampling the polyphase component 0 by 1: 2, 67 is a polyphase component 1 1: 2 up-sampled filter. However, H (z) is _{h 0, h 1, h 2} , ... h L-1
(Coefficient of filter H) E ₀ (z) is h ₀ , h ₂ , h ₄ , h ₆ ,... (Coefficient of polyphase component of filter H) E ₁ (z) is h ₁ , h ₃ , h ₅ , h ₇ ,... (coefficients of the polyphase component of the filter H) E ₀ (z ² ) is h ₀ , 0, h ₂ , 0, h ₄ , 0, h ₆ ,
0,... E ₁ (z ² ) are h ₁ , 0, h ₃ , 0, h ₅ , 0, h ₇ ,
0,..., Z ⁻¹ is a delay for one pixel. Next, the reduction in the number of times of multiplication by polyphase decomposition will be examined in accordance with an equation. The filter H (z) is represented by Expression 5.

[0036]

(Equation 4)

The filter H (z) can be expressed by dividing it into even and odd terms as shown in the following equation (5). This is called a polyphase expression.

[0038]

(Equation 5)

The procedure for applying the filter expressed in polyphase as described above and subsequently performing the 2: 1 decimation can be described as in the following equation (6).

[0040]

(Equation 6)

The first term in Equation 14 means that the filter E ₀ is applied to the even-numbered pixels of the signal, and the second term means that the filter E ₁ is applied to the odd-numbered pixels of the signal.
As can be seen from the equation, since filtering is performed after thinning out instead of thinning out after filtering, in the polyphase expression, filtering is performed to obtain only pixel values that remain without being thinned out. From Equations 5 to 14, it can be seen that the number of multiplications in the polyphase expression can be reduced by 表現 in the one-dimensional direction, that is, １ ／ as a whole, as compared with the case where no polyphase is used. In this way, since the polyphase decomposition performs filtering by setting filtering and thinning as a set, the problem that the processing time of filtering to obtain pixel values that are thinned is wasted is eliminated, and efficient filtering is performed. Can be realized. If the polyphase expression of the filter is used, an unnecessary operation is systematically removed by considering the filtering and the decimation process as a set, and a system for performing the reduction process with the minimum number of product-sum operations is obtained.

Embodiment 6 FIG. FIG. 9 shows Embodiment 6 of the present invention.
FIG. In the sixth embodiment, in addition to the reduction of the product-sum operation by using the polyphase expression of the filter shown in the fifth embodiment, the number of operations is further reduced by utilizing the symmetry of the filter. In FIG. 9, reference numeral 61 denotes a ^2N : 1 multi-value reduction processing unit using polyphase expression, and 62 denotes an additional reduction processing unit using polyphase expression, and 2 ^N : 1 multi-value reduction processing unit 5 according to the fifth embodiment.
1. The same as the additional reduction processing unit 55. Reference numeral 63 denotes a filter symmetry determination unit that determines the symmetry of the filter selected by the filter selection unit 13. The filter symmetry determination unit 63 determines the symmetry of the one-dimensional filter selected by the filter selection unit 13. When the filter has an odd number of taps and the filter has even symmetry, the polyphase components E ₀ and E ₁ also have symmetry as shown in FIG. When the tap length of the filter is an even number and the filter has even symmetry, symmetry is not established for each of the components E ₀ and E ₁ , but FIG.
As shown in (b), since the components E ₀ and E ₁ are mirror images of each other, the components E ₀ and E ₁ are symmetrical with respect to the dotted line. In the sixth embodiment, in addition to the use of the polyphase expression of the filter, when the filter is symmetric, this is used to realize a further higher speed. The principle thereof will be described below.
In the case of an odd tap filter (N = 2K + 1), the speed is increased using the symmetry of the filter.

[0043]

(Equation 7)

When K = 2M, the component E ₀ is an odd tap filter (odd symmetric), and the component E ₁ is an even tap filter (even symmetric). First, component E
Looking at the filtering of ₁ using symmetry, Equation 17
Becomes

[0045]

(Equation 8)

Here, filter symmetry e ₁ (k) = e
_{1 When} (2M-1-k) is applied to the second term on the right side,

[0047]

(Equation 9)

Is as follows. As a result, the number of multiplications component E ₁ is, M = K / 2, that is, can be halved in the case of not utilizing symmetry. Similarly, using symmetry to filter component E ₀ ,

[0049]

(Equation 10)

Thus, the number of multiplications of the component E ₀ can be reduced to 1 + M = 1 + K / 2, that is, about half of the case where the symmetry is not used. As described above, by using the symmetry, the total number of multiplications becomes 1 + 2M = 1 + K = 1 + (N−1) / 2 = (N + 1) / 2 (Equation 20), which is about half of the case where the symmetry is not used. You can see that it can be done.

On the other hand, when K = 2M + 1, the component E ₀ is an even tap filter (even symmetric) and the component E
₁ is an odd tap filter (odd symmetry). First, because the component E ₁ is the odd symmetry of the filter are available,

[0052]

[Equation 11]

Is as follows. Number of multiplications component E ₁ is, 1 + M = 1 + ( K-1) / 2 = (K + 1) / 2, that is, is about half of the case of not using the symmetry. Even symmetry is available for component E ₀ ,

[0054]

(Equation 12)

Is as follows. The number of multiplications of the component E ₀ is 1 + M = (K + 1) / 2, that is, about half of the case where no symmetry is used. As described above, the total number of multiplications is 1 + 2M = (K + 1) / 2 + (K + 1) / 2 = K
+ 1 = (N + 1) / 2, and it can be seen that it can be reduced to about half by using the symmetry.

In the case of an even tap filter (N = 2
K) speeds up using the fact that components E ₀ and E ₁ are mirror images of each other. In the case of an even tap filter, the symmetry of the filter cannot be used for each of the polyphase components E ₀ and E ₁ . However, instead the polyphase components E ₀ , E ₁
By using the fact that the two become mirror images of each other, the number of times of multiplication can be reduced as in the case of the odd tap filter. However, when a mirror image is used, it is necessary to filter E ₀ and E ₁ collectively instead of filtering for each polyphase component E ₀ and E ₁ . Each polyphase component E ₀ ,
E ₁ can be written as follows.

[0057]

(Equation 13)

These are summarized, and the result of using the mirror image is shown below.

[0059]

[Equation 14]

When the second term on the right side is a mirror image, e ₁ (k) = e ₀ (K−1−k),

[0061]

(Equation 15)

It can be seen that the number of multiplications can be reduced to K = N / 2, that is, half of the case where the mirror image is not used.

Embodiment 7 FIG. FIG. 11 is a partial block diagram showing a seventh embodiment of the present invention. Embodiment 1
6 to 6, the 2 ^N : 1 multi-valued reduction processing unit implements the 2 ^N : 1 multi-valued reduction processing based on filtering, that is, a product-sum operation, but in the seventh embodiment, a table operation is performed. That is, since the sum of products for realizing the reduction processing conversion using the 2: 1 multi-valued reduction processing conversion table is not explicitly performed, the processing can be speeded up. In the seventh embodiment, for example, the ^2N : 1 multilevel reduction processing section 51 using the polyphase expression in the vertical direction 2: 1 multilevel reduction processing section 52 of the fifth embodiment is used.
Is replaced by a table conversion vertical direction 2: 1 multi-value reduction processing unit. In FIG. 11, reference numeral 71 denotes a 2 ^N : 1 multi-level reduction processing unit, and reference numeral 72 denotes a table conversion vertical direction 2: 1 multi-level reduction processing unit. In the table conversion vertical direction 2: 1 multilevel reduction processing unit 72, instead of calculating the input pattern and the output pattern each time, the input pattern and the output pattern are calculated in advance, and the input and output are made to correspond one-to-one in advance. Instead of using the conversion pattern table to perform a multiply-accumulate operation on the input to obtain an output, an input / output relationship that matches the input pattern is searched from the table, thereby obtaining a 2: 1 multiplication in the vertical direction. Perform value reduction processing. Table 4 shows an example of this conversion pattern table.

[0064]

[Table 4]

In Table 4, the underlined portion of the input pattern represents the pixel of interest. More specifically, the operation of the table conversion vertical direction 2: 1 multi-value reduction processing unit 72 will be described. The length matches the tap length of the 2: 1 reduction processing filter, and each element value is 0,
If the input pattern represented by 1 (binary representation) is, for example, 0, 0, 0, instead of obtaining the output as 0 by performing a convolution operation, the input pattern 0,
Search for 0,0 and output an output value 0 corresponding to the same pattern. In the seventh embodiment, in order to reduce the size of the conversion table and the capacity for storing the table, the table conversion operation is applied only to the vertical 2: 1 multi-value reduction processing unit 52 in the fifth embodiment. . For the other processing, that is, the vertical 2: 1 reduction processing, the horizontal reduction processing, and the additional reduction processing, the same filtering calculation as in the first to sixth embodiments is used. The conversion table size in the case where the binary image is reduced and converted into the image of M gradation at a ratio of 2: 1 is 2 ^L or less when the tap length of the filter is L. For example, if L = 3, a very small table size of 8 is sufficient.

Embodiment 8 FIG. FIG. 12 is a partial block diagram showing Embodiment 8 of the present invention. In the above-described seventh embodiment, the table conversion operation is performed in the vertical direction 2: 1 multi-value reduction processing (when the reduction processing is performed in the vertical and horizontal order) or in the horizontal direction 2:
Although the case of 1-valued reduction processing (case of performing reduction processing in the horizontal and vertical order) has been described, the eighth embodiment is also applied to the 2: 1 reduction processing in the vertical direction and the 2: 1 reduction processing in the horizontal direction. Since the table operation is performed instead of the product-sum operation as in the seventh embodiment, the speed can be increased. In this case, it is necessary to separately prepare a conversion table for 2: 1 multilevel reduction processing in the vertical or horizontal direction and a conversion table for 2: 1 reduction processing in the vertical and horizontal directions similar to those used in the seventh embodiment. . The former requires a table that maps a binary input pattern to a certain value of M gradations, while the latter requires a table that maps an input pattern of M gradations to a certain value of M gradations. Because it is necessary. The table size of the latter table, that is, the number of input patterns, is M ^L or less, where M is the number of gray levels and L is the tap length of the filter, whereas the table size of the former is 2 ^L or less. . In FIG. 12, reference numeral 81 denotes a 2 ^N : 1 multi-level reduction processing unit, 72 denotes the same table conversion vertical direction 2: 1 multi-level reduction processing unit as in the seventh embodiment, and 82 denotes table conversion horizontal direction 2: 1 reduction processing. , 83 is a 2: 1 repetition reduction processing unit, 83a is a table conversion vertical 2: 1 reduction processing unit, 8
3b is a table conversion horizontal 2: 1 reduction processing unit, and 83c is a counter which is the same as the counter 54c of the seventh embodiment. In the eighth embodiment, the vertical / horizontal direction 2 shown in Table 5:
(1) High-speed processing is performed by table calculation using a conversion table for reduction processing. In the eighth embodiment, it is preferable to use high-speed binary image multi-level reduction processing when the memory size for storing the conversion table is large.

[0067]

[Table 5]

Embodiment 9.2 In a binary image, the combination of white and black pixels generally makes up the majority of the white pixels as the background color. Since the reduction processing result for the background color portion is always "background color (white)", if it is known in advance that filtering is performed on the background portion, it is not necessary to obtain the reduction processing result for this portion by a product-sum operation.
Therefore, in the ninth embodiment, it is determined whether or not all the pixel values within the filtering range of the target pixel are “background color (white)”. White) ”is output as the reduction result, and in other cases, if the output result is obtained by the same filtering as described in the first to sixth embodiments, the“ background color ( By omitting the sum-of-products operation for "white"), the reduction processing can be speeded up.
FIG. 13 is a block diagram showing a ninth embodiment of the present invention, wherein the same components as those in the first and sixth embodiments are denoted by the same reference numerals. In FIG.
Reference numeral 91 denotes a filtering target pixel control unit that selects whether to perform filtering or to use the background color as it is, thereby omitting the product-sum operation for the background color and achieving high-speed reduction processing.

Embodiment 10 FIG. FIG. 14 is a block diagram showing a tenth embodiment of the present invention, wherein the same components as those in the first embodiment are denoted by the same reference numerals. FIG.
In FIG. 4, reference numeral 101 denotes a pre-reduction processing unit based on the SPC method or the projection method. The pre-multi-value reduction processing unit 31 in the third embodiment converts a binary image into a multi-valued image and reduces it. In this case, the process is reduced to a process of reducing the binary image without performing the process. In this way, a conventional method of reducing a binary image at high speed (SPC method, projection method, etc.) can be used. As a result, it is possible to perform the binary image multi-level reduction processing by directly utilizing the conventional high-speed method of the binary image reduction processing. The pre-reduction processing unit 10
Since the reduction ratio P: Q at 1 is larger than 2: 1 (Q / P
> 1/2) There is almost no demerit that image quality is reduced by generating a reduced image with binary values.

Embodiment 11 FIG. In the above embodiment,
For example, as shown in Table 3, a filter whose filter norm is 1 (a filter with normalization) is used. In this case, the product-sum operation is a floating-point operation. Instead, in the eleventh embodiment, a filter selection table in which filter coefficients without normalization are expressed by integers as shown in Table 6 as an example is used, and an integer operation faster than a floating-point operation is performed. Performs a product-sum operation and normalizes the result. By doing so, the product-sum operation in filtering is speeded up.

[0071]

[Table 6]

Table 7 shows a comparison of the filter coefficients with and without normalization.

[0073]

[Table 7]

FIGS. 15 and 16 show Embodiment 1 of the present invention.
FIG. 15 and 16, the same components as those of the second embodiment are denoted by the same reference numerals. As shown in FIG. 15, normalization may be performed by the normalization units 111 to 114 each time each filtering (reduction process) is performed. Alternatively, as shown in FIG. Although the reduction may be performed by the normalization unit 115, the method of normalizing immediately before overflow in the product-sum operation can minimize the number of times of normalization.

[0075]

Since the present invention is configured as described above, it has the following effects.

A binary image represented by one bit per pixel is input, and the binary image is filtered by a 2: 1 multilevel reduction processing unit without being explicitly changed to an 8-bit representation per pixel, and the halftone M Generate a level and reduce it by 2: 1 to 1
By converting to an N-bit pixel (N is 2 ^M or more) representation, the processing speed is faster than explicitly converting the input image represented by 1-bit per pixel to N-bit representation per pixel and then reducing. it can. Further, the obtained 2: 1 multi-value reduced image is repeatedly subjected to the desired number of times of the 2: 1 reduction processing, and finally the additional reduction processing at an arbitrary reduction ratio is performed, so that one multi-reduction processing is performed without using the repetition processing. Compared with the case where reduced images with the same magnification are generated by the value reduction processing, the reduction processing can be realized with a smaller number of product-sum operations.

Further, if the filtering of the multi-value reduction processing by the repetition processing is performed by a one-dimensional filter, a reduced image is generated by one multi-value reduction processing without using the one-dimensional filter and the repetition processing. In addition, reduction processing can be realized with a smaller number of product-sum operations than using repetition processing using a two-dimensional filter.

Further, the multi-valued reduction processing at an arbitrary magnification is realized, and the multi-valued reduction processing at the same magnification as the additional reduction processing is input.
By applying the processing to the value image and reducing it to a desired magnification by a (power of 2): 1 reduction processing, it is possible to realize high-speed processing with a ^2N : 1 reduction processing unit having a small number of components.

Further, by realizing the multivalued image reduction processing by iterative reduction processing using a one-dimensional filter, the number of times of product-sum operations required for filtering can be reduced as compared with the case of using iterative processing using a two-dimensional filter, and high-speed Can be Furthermore, even when a one-dimensional filter is used, a ^2N : 1 reduction processing unit can be realized with a small number of components.

Also, by using the polyphase expression of the filter in the filtering part of the multi-valued reduction processing and the reduction processing, the product-sum operation which does not affect the image quality of the reduced image obtained as a result of the processing is removed in advance. Can be realized, and the speed of the binary image multi-level reduction processing can be significantly increased.

Further, in addition to reducing the number of product-sum operations by using the polyphase expression, the number of product-sum operations is further reduced by utilizing the symmetry of the filter to be used. High speed can be realized.

Further, a part where a 2: 1 reduced image of M gradations is generated from a binary image by a 2 ^N : 1 multi-value reduction processing unit or a pre-reduction processing unit is input instead of the product-sum operation. By substituting the table conversion according to the image pattern, it is possible to further speed up the binary image multi-value reduction processing.

Further, by replacing all filtering portions with table operations and eliminating all product-sum operations for filtering, it is possible to further speed up the binary image multi-value reduction processing.

Also, since the reduction result for the background portion (white), which occupies most of the pixel values of the binary image, is always the background color (white), the filtering for those is omitted, so that the binary image is multi-valued. Significant speed-up of the reduction process can be realized.

The result of the reduction processing by the pre-reduction processing section is 2
By generating a value image, the pre-reduction processing unit can perform high-speed S processing which has been studied in the field of reduction processing of a binary image.
A high-speed method such as a PC method or a high-speed projection method can be used, and high-speed binary image multi-level reduction processing can be realized.

Also, by using an integer coefficient filter, the product-sum operation of the filtering can be performed in the integer type, and the reduced result by the filtering is normalized later without narrowing the selection range of the filter. The speed of the binary image multi-level reduction processing can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram of filtering used in Embodiment 1 of the present invention.

FIG. 3 is a block diagram of a 2 ^N : 1 multilevel reduction processing unit and an additional reduction processing unit according to Embodiment 2 of the present invention;

FIG. 4 is a block diagram showing Embodiment 3 of the present invention.

FIG. 5 is a block diagram of a 2 ^N : 1 reduction processing section and a pre-multi-valued reduction processing section according to Embodiment 4 of the present invention.

FIG. 6 is a block diagram of a 2 ^N : 1 reduction processing unit and an additional reduction processing unit according to Embodiment 5 of the present invention.

FIG. 7 is a block diagram showing pixels that need to be filtered and pixels that do not.

FIG. 8 is a block diagram showing a filtering system using a polyphase expression according to the fifth embodiment of the present invention.

FIG. 9 is a block diagram showing Embodiment 6 of the present invention.

FIG. 10 is a characteristic diagram showing a case where a filter for which symmetry is determined in Embodiment 6 of the present invention has an odd tap / even symmetric filter and an even tap / even symmetric filter.

FIG. 11 is a block diagram of a 2 ^N : 1 multilevel reduction processing unit using table conversion according to Embodiment 7 of the present invention;

FIG. 12 is a block diagram of a 2 ^N : 1 multilevel reduction processing unit using table conversion according to Embodiment 8 of the present invention;

FIG. 13 is a block diagram showing Embodiment 9 of the present invention.

FIG. 14 is a block diagram showing a tenth embodiment of the present invention.

FIG. 15 is a block diagram showing an eleventh embodiment of the present invention.

FIG. 16 is a different block diagram showing the eleventh embodiment.

FIG. 17 is a block diagram showing a conventional binary image reduction processing device.

[Explanation of symbols]

11 binary image signal input unit, 12 thinning rate division control unit, 13 filter selection unit, 14, 21, 51, 71,
81 2 ^N : 1 multi-level reduction processing section, 15 2: 1 multi-level reduction processing section, 16, 24, 54, 83 2: 1 repetition reduction processing section, 16a 2: 1 reduction processing section, 16 b, 24
c, 42c, 54c, 83c counters, 17 additional reduction processing units, 18 multi-value reduction processing control units, 19 image display units, 22 vertical 2: 1 multi-value reduction processing units, 23, 24
b, 42b Horizontal 2: 1 reduction processing unit, 24a, 42a
Vertical 2: 1 reduction processing unit, 25, 55 additional reduction processing unit, 25a Vertical additional reduction processing unit, 25b Horizontal additional reduction processing unit, 31, 41 pre-multilevel reduction processing unit, 3
2,422 2 ^N : 1 reduction processing section, 41a vertical pre-multilevel reduction processing section, 41b horizontal pre-multilevel reduction processing section, 52 vertical 2: 1 multi-level reduction processing section using polyphase expression, 53, 54b Horizontal 2: 1 reduction processing section using polyphase expression, 54a Vertical 2: 1 reduction processing section using polyphase expression, 55a Additional vertical processing section using polyphase expression, 55b Horizontal addition using polyphase expression Reduction processing unit, 56 filters, 57 2: 1 decimation processing unit, 58 filter polyphase component 0, 59 filter polyphase component 1, 61 use of polyphase expression 2 ^N : 1 multi-value reduction processing unit, 62 poly Phase expression use additional reduction processing unit,
63 filter symmetry determination unit, 64 polyphase component of odd tap even symmetric filter, 65 polyphase component of even tap even symmetric filter, 66
Filter in which polyphase component 0 is upsampled by 1: 2, 67 Filter in which polyphase component 1 is upsampled by 1: 2, 72 Table conversion vertical direction 2: 1 multilevel reduction processing section, 82, 83b Table conversion horizontal direction 2 1: 1 reduction processing section, 83a Table conversion vertical direction 2: 1 reduction processing section, 91 filtering target pixel control section, 101 SPC or pre-reduction processing section by projection method, 111-115 normalization section.

Claims (12)

[Claims] 1. An input reduction ratio (thinning ratio; a: 1)
Is divided into 2 ^N : 1 and a / 2 ^N : 1 and the latter thinning rate a / 2 ^N : 1 is defined as P: Q (P and Q are relatively prime integers, P> Q, P: Q間 2: 1), a thinning rate division control unit, and a filter selection for selecting a 2: 1 reduction filter used for 2: 1 reduction processing and a P: Q reduction filter used for P: Q reduction processing, respectively Part and selected 2:
1 for reduction using the filter 2: 1 2 iterating multilevel reduction process ^N: 2 for 1 of the multi-level reduction process ^N: 1
Multi-valued reduction processing unit, 2 ^N : 1 when P: Q ≠ 1: 1
The input binary image that has been multivalued and reduced to 2 ^N : 1 by the multivalued reduction processing unit is reduced to P: Q in each of the vertical and horizontal directions using a P: Q reduction filter. Processing unit, 2
^{In the case of N} : 1 ≠ 1: 1, the reduction processing is performed by the 2 ^N : 1 multilevel reduction processing section, and then the processing is shifted to the additional reduction processing section. Here, when P: Q = 1: 1, The image is transferred to the image display unit without performing the additional reduction process, and when P: Q ≠ 1: 1, the additional reduction processing unit is controlled to perform the additional reduction process, and 2 ^N : 1 = 1: 1 In the case of 1, 2 ^N : 1 multi-level reduction processing is not performed. Here, in the case of P: Q = 1: 1, input image data expressed by one bit per pixel without additional reduction processing. Is converted to an image in the data format of a multi-valued image and passed to the image display unit. In the case of P: Q ≠ 1, the image data having the data format of the multi-valued image is directly obtained from the image data expressed by one bit per pixel. A multi-valued reduction processing control unit that controls the additional reduction processing so as to generate a reduced image of P: Q and pass it to the image display unit; Comprising ,, any magnification multilevel reduction processing 2 ^N: 1 multilevel reduction process and the additional reduction processing binary image multivalue reduction processing apparatus characterized by speeding combined by the process of. 2. A ^2N : 1 multi-level reduction processing unit for converting the vertical or horizontal direction of a binary image represented by one bit per pixel into 2:
The multi-value reduction processing is performed to generate an image of 1 pixel M gradation,
A vertical or horizontal 2: 1 multi-level reduction processing unit that outputs an image expressed by one pixel B (≧ 2 ^M ) bits, and an M-th floor output from the vertical or horizontal 2: 1 multi-level reduction processing unit A horizontal or vertical 2: 1 reduction processor for reducing the toned image horizontally or vertically 2: 1 and an output image of the horizontal or vertical 2: 1 reduction processor alternately vertically and horizontally 2: 1. 2. A 2: 1 repetition reduction processing unit which repeatedly applies a vertical 2: 1 reduction process and a horizontal 2: 1 reduction process to (N-1) times. Binary image multilevel reduction processing device. 3. The binary image multi-level reduction processing device according to claim 2, wherein the reduction filter selected by the filter selection unit is a one-dimensional filter. 4. An input reduction rate (thinning rate; a: 1)
Is divided into 2 ^N : 1 and a / 2 ^N : 1 and the latter thinning rate a / 2 ^N : 1 is defined as P: Q (P and Q are relatively prime integers, P> Q, P: Q間 2: 1), a thinning rate division control unit, and a filter selection for selecting a 2: 1 reduction filter used for 2: 1 reduction processing and a P: Q reduction filter used for P: Q reduction processing, respectively , A pre-multi-valued reduction processing unit that multi-values and reduces the input binary image to P: Q (≠ 2: 1), and reduces to 2 ^N : 1 by repeating the 2: 1 reduction process to obtain a desired value A 2 ^N : 1 reduction processing unit for reducing the image to the magnification, and a multi-value reduction processing unit for controlling the pre-multi-value reduction processing unit and the 2 ^N : 1 reduction processing unit, respectively, multilevel reduction processing and the pre-multi-level reduction process to 2 ^N: characterized in that the speed of the process by a combination of 1 reduction process Value image multivalued reduction processor. 5. A ^2N : 1 reduction processing unit, in which the M gradation image expressed by one pixel B (≧ 2 ^M ) bits obtained by the pre-multi-valued reduction processing unit is alternately arranged in the vertical and horizontal directions. 2:
2: 1 reduction processing in the vertical direction to reduce to 1 and 2:
5. The binary image multi-valued reduction processing apparatus according to claim 4, wherein a 2: 1 repetition reduction processing unit that repeatedly applies one reduction processing N times is used. 6. A filter as a vertical 2: 1 multilevel reduction processing section, a horizontal 2: 1 multilevel reduction processing section, a vertical 2: 1 reduction processing section, and a horizontal 2: 1 reduction processing section. By using the polyphase expression, filtering operations for obtaining pixel values that are discarded by the thinning process are excluded in advance, and the number of product-sum operations is minimized within a range that does not depend on the filter shape or filter coefficient value. 6. The binary image multi-value reduction processing apparatus according to claim 2, wherein the reduction processing is performed to a minimum. 7. A filter symmetry judging unit for judging the symmetry of a filter selected by a filter selecting unit, wherein the judgment result of the filter symmetry judging unit is even symmetric, and the filter length is odd. In some cases, the fact that even symmetry holds for each polyphase component obtained by expressing the filter in polyphase is utilized, and the determination result in the filter symmetry determination unit is even symmetric, and
When the filter length is an even number, the fact that each polyphase component obtained by expressing the filter in polyphase forms a mirror image with each other, and a vertical 2: 1 multilevel reduction processing unit using polyphase expression or 7. The method according to claim 6, further comprising reducing the sum-of-products operation in the filtering of the horizontal 2: 1 multilevel reduction processing unit, the vertical 2: 1 reduction processing unit, and the horizontal 2: 1 reduction processing unit. Value image multilevel reduction processing device. 8. A vertical conversion 2: 1 multilevel reduction processing section or a horizontal 2: 1 multilevel reduction processing section, and a table conversion vertical 2: 1 multilevel reduction processing section or a table conversion horizontal direction. 8. The image processing apparatus according to claim 2, wherein a 2: 1 multi-level reduction processing unit is used, and a product-sum operation in filtering for multi-level reduction of a binary image is replaced with a table conversion. 2. The binary image multi-value reduction processing device according to 1. 9. A vertical 2: 1 multilevel reduction processing section, a horizontal 2: 1 multilevel reduction processing section, a vertical 2: 1 reduction processing section, and a horizontal 2: 1 reduction processing section each include a table. A conversion vertical direction 2: 1 multilevel reduction processing section, a table conversion horizontal direction 2: 1 multilevel reduction processing section, a table conversion vertical direction 2: 1 reduction processing section, and a table conversion horizontal direction 2: 1 reduction processing section; 8. The binary image multi-value reduction processing apparatus according to claim 2, wherein a product-sum operation in all filtering is replaced with a table conversion. 10. It is determined whether or not all pixel values within a filtering range of a target pixel are “white”. If “all white”, a reduction process by filtering is not performed and “0” is set as an output value. If the value is not 0 ", a filtering target pixel control unit for performing a reduction process by filtering is provided, and the number of times of filtering for generating a reduced image is reduced.
The value image multi-level reduction processing device according to any one of the above. 11. A pre-multi-valued reduction processing section for multi-valued reduction of a binary image generates a binary reduced image from a binary image by using a high-speed binary image reduction processing by an SPC method or a projection method. A pre-reduction processing unit using the SPC method or the projection method,
The thinning-out ratio 2 ^N : 1 reduction processing unit is replaced with the thinning-out ratio 2 ^N : 1 multi-value reduction processing unit, and the reduction processing is speeded up by multi-value reduction processing of a binary reduced image to a desired reduction rate. 6. The binary image multi-value reduction processing apparatus according to claim 4, wherein the processing is performed. 12. A filter having an integer coefficient (in general, the norm is not 1), a vertical 2: 1 multilevel reduction processing section, a horizontal 2: 1 multilevel reduction processing section, and a vertical 2: 1 reduction. A normalizing unit that divides by a filter norm every time filtering is performed by a processing unit or a horizontal 2: 1 reduction processing unit, or
After the 2 ^N : 1 multi-valued reduction processing or the 2 ^N : 1 reduction processing, (filter norm) is provided with a normalization unit that divides by ^2N to normalize and replaces floating-point arithmetic with integer arithmetic. 2. The method according to claim 2, wherein the processing is speeded up.
A binary image multilevel reduction processing device according to claim 11.