JPH0540825A - Image processor - Google Patents

Abstract

PURPOSE:To suppress the scale increase of a circuit at the time of realizing hardware, to reduce the disappearance of fine lines at the time of reduction and to enable excellent conversion of pseudo-intermediate tones. CONSTITUTION:A pattern detection processing part 12 detects a pattern preliminarily set based on an original image, a conversion picture element value calculation pad 11 performs the reduction conversion of the picture element of the original image based on a projection method, a picture element value reduction processing part 13 further reduces the picture element value reduced in the conversion picture element value calculation part 11, and a detection result reduction processing part 14 reduces the detection result obtained in the pattern detection processing part 12. A concentration retention binaryzing processing part 18 binaryzes the picture element value reduced in the picture element value reduction processing part 13, a simple binaryzing processing part 16 binaryzes the picture element value similar to that used when the binaryzation was conducted in the concentration retention binaryzing processing part 18, a selection part 19 selects the binaryzation result obtained in the simple binaryzing processing part 16 when the pattern was detected in the pattern detection processing part 12 one hand and selects the binaryzation result obtained in the concentration retention binaryzing processing part 18 on the other hand when the pattern was not detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and, more particularly, to an image processing apparatus for performing resolution conversion and enlargement / reduction conversion of a binary image in which characters and line drawings and pseudo-halftone images are mixed in facsimile and the like.

[0002]

2. Description of the Related Art In the case of performing communication between facsimiles having different resolutions and enlarging / reducing image data in an image editing apparatus or the like, a pixel density conversion process of an image is required. Conventionally, as a pixel density conversion method for a binary image, as described in IPSJ Journal Vol.25 No.5, SPC is used.
Various methods such as a method, a logical sum method, a 9-division method, a projection method, a linear interpolation method, and a distance inverse proportion method have been proposed. Among these methods, it is known that the projection method and the linear interpolation method are methods that are excellent in the preservation of the geometrical shape due to the conversion and that the thin line disappears relatively at the time of reduction.

[0003]

However, even in the above-mentioned method, there is a drawback in that when the conversion magnification is small, linear omission or crushing occurs, and it is not sufficient when targeting characters or the like. The logical sum method was devised from this point of view, but it had drawbacks such as crushed characters and thick lines at any conversion ratio. Further, in the above-mentioned conventional examples, when processing is performed on an image which has been subjected to pseudo halftone processing in any of the methods, there are major drawbacks such as change in gradation characteristics and moire.

Further, when the projection method or the like is realized by hardware, if the reduction ratio is 1/2 or less, there is a drawback that the circuit scale increases significantly with an increase in the number of reference pixels. The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to suppress an increase in the circuit scale at the time of hardware realization, reduce thin line disappearance at the time of reduction, and a good pseudo intermediate. The point is to provide an image processing apparatus capable of converting tones.

[0005]

[Means for Solving the Problems]
To achieve the object, an image processing apparatus according to the present invention includes a detection unit that detects a preset pattern based on an original image, a first reduction unit that reduces a pixel value of the original image, and the first reduction unit. Second reducing means for reducing the pixel value reduced by the reducing means, third reducing means for reducing the detection result obtained by the detecting means, and binary pixel values reduced by the second reducing means. First binarizing means for binarizing, and a pixel value similar to the pixel value when binarizing by the first binarizing means based on the detection result reduced by the third reducing means. 1
Second binarizing means for binarizing by a method different from that of the binarizing means, and a binarizing result obtained by the second binarizing means when the pattern is detected by the detecting means. Selection means for selecting and selecting the binarization result obtained by the first binarization means when the pattern is not detected by the detection means.

[0006]

According to this structure, the detection means detects a preset pattern based on the original image, the first reduction means reduces the pixel value of the original image, and the second reduction means the first reduction. The pixel value reduced by the means is reduced, the third reducing means reduces the detection result obtained by the detecting means, and the first binarizing means is the second.
The pixel value reduced by the reducing means of 2 is binarized, and the second binarizing means binarizes the pixel value by the first binarizing means based on the detection result reduced by the third reducing means. The same pixel value is binarized by a method different from that of the first binarizing means, and the selecting means generates the second pixel value when the detecting means detects the pattern.
The binarization result obtained by the binarization means is selected, and the binarization result obtained by the first binarization means is selected when the pattern is not detected by the detection means.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. <First Embodiment> FIG. 1 is a block diagram showing the arrangement of a first embodiment of the image processing apparatus according to the present invention. In the figure, 11 is a converted pixel value calculation unit, 12 is a pattern detection processing unit, 13 is a pixel reduction processing unit, 14 and 15 are detection result reduction processing units, 16 is a simple binarization processing unit, and 17 is a binarization. A threshold processing unit, 18 is a density storage binarization processing unit, and 19 is a selection unit.

Next, the operation of the above configuration will be described. FIG. 2 is a timing chart of signals and data according to the first embodiment. As shown in FIG. 2, for example, as the input image, one line of image data is input in synchronization with the line synchronization signal, and one page of image data is input in synchronization with the page synchronization signal in synchronization with the image synchronization clock. Shall be. In the case of FIG. 2, an image in which one line is composed of 7 pixels is shown for the sake of explanation.

The conversion pixel value calculation unit 11 calculates a conversion pixel value and controls each synchronization signal by, for example, a projection method, etc., and performs a fractional conversion with a magnification greater than ½. The pattern detection processing unit 12 performs pattern matching between a preset pattern and an original image pattern to detect thin lines, edges of characters, and the like. The conversion pixel value reduction processing unit 13 multiplies the conversion image obtained by the conversion pixel value calculation unit 11 by 1 / n (n:
(Integer) signal processing for conversion and control of synchronization signal. The final conversion magnification is determined by the product of the conversion magnification in the conversion pixel value calculator 11 and the 1 / n times processor. The detection result reduction processing unit 14 performs processing for converting the pattern detection result (thin line pattern) obtained by the pattern detection processing unit 12 into 1 / n times. The detection result reduction processing unit 15 performs processing for converting the pattern detection result (edge pattern) obtained by the pattern detection processing unit 12 into 1 / n times. The simple binarization processing unit 16 performs binarization processing of the converted pixel value using the threshold value determined by the selection unit 17 that selects the binarization threshold value from the pattern detection processing result and the reduction conversion processing result. The density storage binarization processing unit 18 stores the pixel value reduction processing result in the density storage 2
Quantize. The selection unit 19 selects the two binarization results according to the reduction processing result of the pattern detection result.

Next, the details of each part will be described step by step. FIG. 3 is a diagram for explaining the principle of the projection method according to the first embodiment, and FIG. 4 is a diagram for explaining the principle of the projection method according to the first embodiment.
It is a figure which shows the example at the time of referring to a pixel. Here, for the sake of explanation, the case where the magnifications of both the main scanning and the sub scanning are 2/3 is shown. First, the converted image is projected on the original image, and one pixel is set as a rectangular area, and original pixels having a pixel surface overlapping the pixel surface of the converted pixel A which is the target pixel are defined as P, Q, R, and S. Here, the area occupied by the pixel planes of the original pixels P, Q, R, and S in the projected pixel plane of the converted pixel A is S _P , S _Q , S
_{Assuming R} and S _S , the average density I _{A of the} pixel of interest is expressed by the following equation (1)
It is represented by. That is,

[0011]

[Equation 1] Is. The density of the converted pixel is determined by binarizing this I _A.

FIG. 3 shows an example of conversion when the number of reference pixels is 4, but the number of reference pixels changes according to the conversion magnification (the smaller the conversion magnification, the larger the number of reference pixels). For example, in the case of a conversion magnification of 1/3 (both main scanning and sub-scanning), a maximum of 16 pixels may be referred to as shown in FIG. Therefore, when it is realized by hardware, the circuit scale is significantly increased, for example, 16 multiplication circuits are required for obtaining the average density of the converted pixels. Therefore, in the projection method of the present embodiment, only four pixels are referred to, and the conversion pixel value obtained here is converted into a multiple of 1 to obtain the final conversion magnification. For example, in the case of performing 1/3 times conversion, the projection method processing unit performs 2/3 times conversion and the pixel value reduction processing unit performs 1/3 times conversion.
/ 2 times conversion is performed.

FIG. 5 is a block diagram showing the configuration of the conversion pixel value calculation unit 11 by the projection method according to the first embodiment, and FIG. 6 is a block diagram showing the configuration of the synchronization signal control unit according to the first embodiment. is there. In the figure, 51 is a conversion pixel position calculation unit, which is a relative position (X,
Y) is calculated. Reference numeral 52 denotes a reference pixel extraction unit that extracts an original pixel having a pixel surface that appears in the pixel surface of the converted pixel. Specifically, in the case of the example shown in FIG. 3, I _P , I _Q , I _R , I
_Take out _S. An area calculator 53 calculates the pixel surface area of the original image included in the pixel surface of the converted pixel. In the case of the example shown in FIG. 3, S _P , S _Q , S _R , and S _S are calculated. An average density calculator 54 calculates the average density of the converted pixels using the reference pixel value and the area calculation result. In the example of FIG. 3, (1)
Calculates the expression. Reference numeral 55 is a synchronization signal control unit, for example, as shown in FIG.
As shown in, the pixel number counter 61 and the line counter 6
4, ROM (read only memories) 62 and 65, and AND gates 63 and 66. The output of each counter (to the lower address) and the conversion ratio (to the higher address) are given as the ROM address, and the periodic thinning pattern according to the previously programmed ratio is output. Furthermore, a thinning-out synchronizing signal (conversion synchronizing signal) required at the time of reduction conversion is obtained by a logical product with the thinning-out pattern.

FIG. 7 shows a conversion ratio 2/3 according to the first embodiment.
This is a timing chart for main scanning at double time. As shown in the figure, the image synchronization clock is thinned to 2/3. In the sub-scanning direction, similar processing may be performed on the line synchronization signal. FIG. 8 is a block diagram showing the configuration of the pixel value reduction processing unit according to the first embodiment.
FIG. 9 is a diagram illustrating reference pixels of the pixel value reduction processing unit of FIG. 8. In FIG. 8, reference numeral 81 is a line buffer that delays the converted pixel data string calculated by the projection method by one line. Reference numerals 82a to 82d denote 1-pixel delay elements, and the line buffers 81 and 82 extract the reference pixels shown in FIG. 9 from the image data string. An average value processing unit 83 performs calculation according to the following equation (2) according to the reduction ratio. In other words, IV = (A + B + C + D) / 4 (main scanning 1/2 times, sub scanning 1/2 times) IV = (A + B) / 2 (main scanning 1/2 times, sub scanning 1 time) IV = (B + D) / 2 (1x main scan, 1 / 2x subscan) IV = B (1x main scan, 1x subscan) (2). In the sync signal thinning-out processing unit 84, the image sync clock and the line sync signal are thinned out according to the conversion magnification. A register 85 strobes the averaged image data with the thinned output synchronizing signal. Performing such average value processing for the projection method is
This is equivalent to expanding the number of reference pixels. By the above processing, the pixel value of the converted pixel whose pixel density has been converted to the final conversion magnification is obtained.

Next, the binarization process will be described. Figure 1
0 is a block diagram showing the configuration of the pattern detection processing unit according to the first embodiment, and FIG. 11 is a block diagram showing the configuration of the pattern detection processing unit according to the first embodiment.
It is a figure explaining the reference pixel point in the pattern detection process part of 0, and FIG. 12 is a figure which shows an example of the thin line and edge pattern by a 1st Example. In FIG. 10, 101a
Numerals 101 to 101c are one-line delay elements, which are composed of line memories and the like, and delay the image data by one line. 102a ~
102m is a 1-pixel delay element, which delays image data by 1 clock. With such a configuration, 16 pixels shown in FIG. 11 can be referred to from the serial image data. 103 is R
By providing the reference pixel value as the ROM address in the OM, pattern matching with a preset pattern becomes possible. For example, when the reference pixel is the black thin line pattern shown in FIG. 12, the ROM output is set to 1, the white thin line pattern is set to 2, the edge pattern is set to 3 and the other cases are set to 0 in advance. Program. A register 104 strobes the obtained determination result with a synchronization signal.

FIG. 13 is a block diagram showing the structure of the detection result reduction processing unit according to the first embodiment. In the figure,
A line buffer 131 delays the data string of the pattern detection result determined by the pattern detection unit by one line. Reference numerals 132a to 132d denote 1-pixel delay elements, and the reference data shown in FIG. 9 is extracted from the data string by 131 and 132 as in the pixel reduction processing unit. Reference numeral 133 is a detection result conversion calculation unit, and in the case of the detection result reduction processing unit 14, for example, calculation according to the following formula (3) is performed according to the reduction ratio. That is, PV1 = A / B + C / D + A / C + B / D (main scanning 1/2 times, sub scanning 1/2 times) PV1 = A / B (main scanning 1/2 times, sub scanning 1 time) PV1 = B D (1 × main scanning, 1/2 × subscanning) PV1 = B (1 × main scanning, 1 × subscanning) (3). Each value of A, B, C and D is 1 or 0, + is a logical sum operation, and · is a logical product operation.

The above calculation is performed for each of the determination results of the black thin line and the white thin line (1 is determined when each thin line is determined). Further, it is set to 1 when it is determined that the thin line is both black and white as a result of the calculation. If the result of the calculation is that both the black and white thin lines are determined, the black thin line is given priority. In the case of the detection result reduction processing unit 15, for example, calculation according to the following formula (4) is performed according to the reduction ratio. That is, PV1 = A + B + C + D (1/2 main scan, 1/2 sub scan) PV1 = A + B (1/2 main scan, 1 sub scan) PV1 = B + D (1 main scan, 1/2 sub scan) PV1 = B (1 × main scanning, 1 × sub-scanning) (4). The above calculation is performed on the result determined to be edge (the multiplication factor determined to be edge is 1).

The calculated result is strobed to the register 134 with the same synchronizing signal as the output timing of the pixel value reduction processing section 13. By the reduction by the above calculation, it is possible to prevent the loss of the pattern detection information during the 1 / n times processing.

The threshold value of the simple binarization process and the selection of the two binarization means are performed using the result of the reduction judgment. Specifically, when a black thin line pattern is used, a simple binarization process with a threshold value lower than usual is performed, and when a white thin line pattern is used, a thin line is saved by a simple binarization process with a threshold value higher than a normal threshold value. At the time of edge pattern, simple binarization processing is performed with a normal threshold value to prevent the edge notch caused by the density storage processing. In other cases, the density-preserving binarization process is performed to prevent moiré that occurs when processing a pseudo-halftone image.

FIG. 14 is a block diagram showing the configurations of the binarization threshold value selection unit and the simple binarization processing unit according to the first embodiment. In the figure, the binarization threshold selection unit 17 is
It has three threshold value storage registers 141 to 143 corresponding to white thin lines and other cases, and a selection unit 144 for selecting a threshold value based on the pattern detection result. For example, the thresholds T-
a, T + a, T are set, and the selection unit 144 selects the register 1 (T-a) for the black thin line, the register 3 (T + a) for the white thin line, and the register 1 (T) for other cases based on the pattern result. Select with. In the simple binarization processing unit 16, 145 is a comparator, which compares the threshold value selected by the selection unit 144 and the converted pixel average density obtained by the projection method, and sets the result as binarized data.

FIG. 15 is a diagram showing an example of black thin line disappearance by the projection method in the first embodiment, and FIG. 16 is a diagram showing an example of black thin line storage according to the first embodiment. In particular,
The conversion as shown in FIG. 15 (both main scanning and sub-scanning is 1 /
(3 times), first, 2/3 times conversion is performed by the projection method, and then reduction processing of 1/2 times is performed on the obtained conversion pixel value. In this case, if conversion is performed with a normal threshold value, the result shown in FIG.
The thin line disappears as shown in (the density value in the figure is expressed by normalizing the maximum value to 1). Therefore, in the present invention, FIG.
As shown in FIG. 6, the thin line is detected by pattern detection synchronized with the projection method process, and the detection result is saved by performing the reduction conversion process on the detection result. In this case, the black line is saved in the above example by setting the threshold value to a value lower than the normal threshold value.

Next, the density storage binarization processing unit will be described. When a projection method or other interpolation method is applied to an image that has been subjected to pseudo halftone processing, if the converted pixel value that is the calculation result is simply binarized, moire is emphasized due to a quantization error, resulting in severe image quality deterioration. In the present invention, the pattern detection processing result is used to perform density preservation processing on portions other than the thin line and the edge portion of the character image to suppress the occurrence of moire.

In the embodiment, as an example, a density storage binarization processing unit using the error diffusion method will be described. FIG. 17 shows the first
19 is a block diagram showing a configuration of a binarization processing unit according to the embodiment of FIG. 18, and FIG. 18 is a diagram explaining an error diffusion position according to the first embodiment. In FIG. 17, 171a to 171e are 1-pixel delay elements, 172a to 172d are adders, and 173.
Is a line buffer, 174 is a binarization processing unit, and 175 is 2
The digitization error calculation unit and 176 are error distribution units, respectively.

With respect to the operation of the above configuration, the average density AD which is the converted pixel value obtained by the projection method is one pixel delay element 171a to 171e, and the line buffer 173 and adder 172a to 172a to 1 are three pixels less than one line.
Quantization error e ₁ to e ₄ generated during binarizing of previous neighboring pixels while passing through the 72d is added. The binarization processing unit 174 binarizes the densities including the quantized pixels of the surrounding pixels with a constant threshold value to obtain pixel data.

Next, the quantization error generated by this binarization is set to 2
Calculated by binarization error calculating unit 175, distributed as e ₁ to e ₄ by the error distribution processing unit 176. In the binarization error calculation unit 175, if the binarization error is e, the input density to the binarization processing unit is I _ED , the threshold value is T, and the binarization output is “1” or “0”, then As in (5),

[0026]

[Equation 2] Becomes In the error distribution unit, for example, e1 to e
4 is calculated. That is, e ₁ = E / 6, e ₂ = 2 ×
E / 6, e ₃ = E / 6, e ₄ = 2 × E / 6, and e ₁
As shown in FIG. 18, the symbols e to e ₄ are distributed to the pixels around the pixel of interest. In the example shown in FIG. 17, the error is diffused to the surrounding four pixels, but the present invention is not limited to this and may be determined in consideration of the image quality and the circuit scale. However, in order to eliminate moiré properly, 2
It is necessary to diffuse the digitization error 100% to the surroundings. That is, Σe _n = E (n: number of surrounding pixels for distributing error)
Determine e _n so that By the above processing, the density-preserving binarization processing is realized, and good conversion can be performed on the image subjected to the pseudo halftone processing.

The selecting unit 19 selects the simple binarization process for the pixels which are determined to be thin lines or edges based on the reduction result of the pattern detection result, and selects the binarization result by the error diffusion method in other cases. ..

As described above, in the first embodiment,
By binarizing the average density of the converted pixels obtained by the projection method with the threshold value selected by the pattern of the original image,
It is possible to prevent the thin lines from falling out during reduction. Further, by selecting the binarization result by the error diffusion method except for the thin line and the edge portion according to the pattern detection result, it is possible to perform excellent conversion processing even on an image in which pseudo halftones are mixed.

Further, by dividing the projection method into a fractional multiplication processing and an integral multiple processing, the increase in the circuit scale when realized by hardware is reduced, and the pattern detection result is also divided into an integral portion. It is possible to prevent the loss of the detection result information at the time of the separation processing by performing the 1 × processing.

<Second Embodiment> The present invention is not limited to the projection method for the processing of the conversion pixel value computing section, and various other interpolation methods may be used, which is an example of the second embodiment. The case where the linear interpolation method is used will be described as an example.

FIG. 19 is a diagram for explaining the principle of the linear interpolation method according to the second embodiment. In the linear interpolation method, the converted pixels are projected on the original image as shown in FIG. 19, and the densities of the four original pixels P, Q, R, and S that are in the vicinity of the converted pixels on the projection surface and the original image grid. From the relative coordinates (x, y) of the converted pixel A in the
Is a method of determining the concentration of. _{That, I A = (1-x} ) · (1-y) · I P + x · (1-y) · I Q + (1-x) · y · I R + x · y · I S ... (6) However, the I _n the density of a pixel n, the I _a get converted image by binarization.

FIG. 20 is a diagram showing an example of black thin line disappearance by the linear interpolation method according to the second embodiment, and FIG. 21 is a diagram showing an example of black thin line storage according to the second embodiment. Even when the above interpolation method is used, for example, both main scanning and sub scanning are 1/3.
In the case of double, as shown in FIG. 20, the thin line disappears by the conversion. However, according to the present invention, as shown in FIG. 21, since a low threshold value is selected by the pattern detection process, the thin line is saved.

As described above, according to the second embodiment, any density conversion processing method can be used as long as the conversion pixel value is once converted into multi-valued data in the process of processing. Applicable.

By the way, the pattern detection processing section is provided with the first and second patterns.
The method is not limited to the method described in the embodiment, and any method may be used. For example, the window size of the reference pixel is not limited to 4 × 4 shown in the embodiment and may be any size.
Further, the thin line pattern is not limited to the case shown in the embodiment, and various patterns such as a slanted line pattern and a thin line pattern having a width of 2 pixels may be applied. Further, not only simple pattern detection by template matching, but also pattern detection by characteristic parameters such as periodicity and spatial frequency in the reference window can be considered.

Further, the pixel value reduction processing unit is not limited to the average value processing shown in the first and second embodiments, and the simplest example may be any processing such as thinning processing.
Further, the detection result reduction processing is not limited to the examples shown in the first and second embodiments, and various ones can be considered in consideration of the image quality. Further, in the embodiment, the case where the above two reductions are 1/2 times has been described, but it is possible to convert to a smaller magnification by expanding the reference window. Further, the density-preserving binarization process is not limited to the error diffusion method as in the first and second embodiments, and any process can be used as long as it is the density-preserving binarization process.

FIG. 22 shows the density storage 2 by the minimum mean error method.
It is a block diagram which shows a digitization part. The average density of the converted pixels obtained by the pixel value calculation processing unit is the error data e between the previously generated input data X _{i, j} and output data Y _{i, j} stored in the error buffer memory 220. _The value obtained by multiplying _{i, j} by the weighting coefficient a _{i, j} designated by the weighting generator 221 for generating the weighting coefficient is standardized, and the adder 2
It is added at 22. When this is written as an expression, it becomes as shown in the following expression (7). That is,

[0037]

[Equation 3] Is. FIG. 23 shows an example of the weighting coefficient applied to the above equation (7).

The correction data X _{i, j '} is compared with a threshold value in the binarization circuit 223, and output data Y _{i, j} is output. Where Y
_{i, j} are binarized to "1" or "0". On the other hand, in the calculator 224, the difference e between the correction data and the output data Y _{i, j
i, j} is calculated and the result is stored in the corresponding pixel location 225 in the error buffer memory. By repeating the above operation, the density preservation binarization process is executed, and an effect of suppressing moire when the pseudo halftone image is converted is obtained.

<Third Embodiment> Next, a third embodiment will be described. FIG. 24 is a block diagram showing the structure of the image processing apparatus according to the third embodiment. In the figure, 24
1 is a converted pixel value calculation unit, 242 is a pattern detection processing unit,
243 is a pixel value reduction processing unit, 244 is a detection result reduction processing unit, 245 is a simple binarization processing unit, 246 is a density storage binarization processing unit, and 247 is a selection unit. In the above structure, as shown in FIG. 2, the input image is synchronized with the line synchronizing signal, the image data for one line is synchronized with the page synchronizing signal, and the image data for one page is synchronized with the image synchronizing clock. It is input in synchronization with.

More specifically, the converted pixel value calculator 24
1, the calculation of the converted pixel value and the control of each synchronization signal are performed by the projection method or the like. Here, singular multiple conversion with a magnification larger than ½ is performed. The pattern detection processing unit 242 performs pattern matching between a preset pattern and the original image pattern to detect thin lines, edges of characters, and the like. The pixel value reduction processing unit 243 performs signal processing for converting the conversion pixel obtained by the conversion pixel value calculation unit 241 to 1 / n times (n: integer) and control of the synchronization signal. The final conversion ratio is
It is determined by the product of the conversion magnification in the conversion pixel value calculation unit 241 and the magnification in the 1 / n times processing unit. Detection result reduction processing unit 244
Performs processing for converting the pattern detection result obtained by the pattern detection processing unit 242 to 1 / n times. The simple binarization processing unit 245 binarizes the pixel value reduction result. The density storage binarization processing unit 246 performs density storage binarization processing on the pixel value reduction processing result. The selection unit 17 selects one from the binarization results of the density-saving binarization processing unit 246 and the simple binarization processing unit 245 according to the reduction processing result of the pattern detection result.

In the first embodiment, as shown in FIG. 1, the threshold value of the simple binarization processing unit 16 is selected by the detection result reduction processing unit 14 and the binarization threshold value selection unit 17, and Although it operates as described above, in the third embodiment, the threshold value handled by the simple binarization processing unit 245 is fixed,
Other configurations and operations are similar to those of the first embodiment.

According to the third embodiment described above, the projection method is divided into the fractional multiplication processing and the integral division processing to reduce the increase in the circuit scale when implemented by hardware. By performing the integral multiple processing also on the pattern detection result, it is possible to prevent the loss of the detection result information at the time of the separation processing, and it is possible to improve the image in which the character image and the pseudo halftone image are mixed. It becomes possible to easily realize a processing device.

<Fourth Embodiment> Next, a fourth embodiment will be described. FIG. 25 is a block diagram showing the structure of the image processing apparatus according to the fourth embodiment. In the figure, 25
1 is a converted pixel value calculation unit, 252 is a pattern detection processing unit,
253 is a pixel value reduction processing unit, 254 is a detection result reduction processing unit, 255 is a simple binarization processing unit, and 256 is a binarization threshold value selection unit. In the above configuration, the input image is synchronized with the line sync signal as shown in FIG.
Image data for lines is synchronized with the page sync signal,
Image data for one page is input in synchronization with the image synchronization clock.

More specifically, the converted pixel value calculation unit 25
1, the calculation of the converted pixel value and the control of each synchronization signal are performed by the projection method or the like. Here, singular multiple conversion with a magnification larger than ½ is performed. The pattern detection processing unit 252 performs pattern matching between a preset pattern and the original image pattern. The pixel value reduction processing unit 253 multiplies the conversion pixel obtained by the conversion pixel value calculation unit 251 by 1 / n (n: integer)
The signal processing for converting to and the control of the synchronizing signal are performed. The final conversion magnification is determined by the product of the conversion magnification in the conversion pixel value calculator 251 and the magnification in the 1 / n times processor. The detection result reduction processing unit 254 performs processing for converting the pattern detection result obtained by the pattern detection processing unit 252 into 1 / n times. The simple binarization processing unit 255 uses the binarization threshold selection unit 256 based on the pattern detection processing result and the reduction conversion processing result.
Binarization processing of the converted pixel value is performed using the threshold value determined in.

FIG. 26 is a diagram showing a fine line detection pattern according to the fourth embodiment. In the pattern detection processing unit 252, the reference pixel is detected as either a black thin line pattern or a white thin line pattern.

As described above, in the fourth embodiment,
Unlike the first embodiment, the density preserving binarization process is not provided, and the threshold value when performing the simple binarization process can be made variable to reduce omissions and collapses of thin lines at the time of reduction. In other words, the average density of the converted pixels obtained by the projection method is reduced to an integer fraction by the average value processing, and the reduced pixel value is binarized by the threshold value selected by the pattern of the original image. It is possible to perform thin line saving reduction conversion that suppresses an increase in hardware scale when the reduction ratio is small. Furthermore, by performing reduction conversion processing on the pattern detection result as well, it becomes possible to prevent the loss of detection result information when the reduction ratio is small.

<Fifth Embodiment> Next, a fifth embodiment will be described. FIG. 27 is a block diagram showing the structure of the image processing apparatus according to the fifth embodiment. In the figure, 27
1 is a converted pixel value calculation unit, 272 is a pattern detection processing unit,
273 is a simple binarization processing unit, 274 is a binarization threshold value selection unit, and 275 is a density storage binarization processing unit.

In this embodiment, the pixel value reduction processing unit 1 shown in FIG.
Pixel density conversion is performed by the configuration excluding 3 and the detection result reduction processing units 14 and 15. Therefore, the operation will be briefly described first. In the above structure, as shown in FIG. 2, the input image is synchronized with the line synchronizing signal, the image data for one line is synchronized with the page synchronizing signal, and the image data for one page is synchronized with the image synchronizing clock. It is input in synchronization with.

More specifically, the converted pixel value calculation unit 27
Reference numeral 1 calculates a converted pixel value by a projection method or the like and controls each synchronization signal. The pattern detection processing unit 272 performs pattern matching between a preset pattern and the original image pattern. The simple binarization processing unit 273 performs binarization processing of the converted pixel value using the threshold value determined by the binarization threshold value selection unit 274 from the pattern detection processing result. The density storage binarization processing unit 275 performs density storage binarization processing on the converted pixel values obtained by the converted pixel value calculation unit 271. The selection unit 276 selects one from the binarization results of the simple binarization processing unit 273 and the density storage binarization processing unit 275 based on the pattern detection result.

Next, the thin line processing method of this embodiment will be described. 28 is a diagram showing an example of black thin line disappearance by the projection method, FIG. 29 is a diagram showing an example of black thin line storage according to the fifth embodiment, FIG. 30 is a diagram showing an example of white thin line disappearance by the projection method, and FIG. 31 is a diagram showing an example of white thin line storage according to the fifth embodiment.

When performing the conversion shown in FIG. 28,
Normally, when conversion is performed with a threshold value, thin lines disappear as shown in the figure (the density value in the figure is expressed by normalizing the maximum value to 1). Therefore, in the fifth embodiment, fine lines are detected by pattern detection. For example, in the case of a black fine line, the threshold value is set to a value lower than a normal threshold value.
A black line is stored as shown in FIG. Further, in the case of a white thin line as shown in FIG. 30, the thin line disappears with a normal threshold value, but in the present embodiment, a low threshold value is selected from the pattern detection results, and the white line is saved as shown in FIG.

As described above, according to the fifth embodiment, the average density of the converted pixels obtained by the projection method is binarized by the threshold value selected by the pattern of the original image, so that the reduced density is reduced. It is possible to prevent the thin lines from coming off. Furthermore, by selecting the binarization result by the error diffusion method except for the thin line and the edge portion according to the pattern detection result, it is possible to perform excellent conversion processing even on an image in which pseudo halftones are mixed.

<Sixth Embodiment> The present invention is not limited to the projection method for the processing of the conversion pixel value calculation section, and various other interpolation methods may be used, and the sixth embodiment is one example. The case where the linear interpolation method is used will be described as an example.

FIG. 32 is a diagram showing an example of disappearance of a black thin line,
FIG. 33 is a diagram showing an example of black thin line storage according to the sixth embodiment. In the conversion shown in FIG. 32, the thin line disappears due to the conversion. On the other hand, according to the method shown in FIG.
Since the low threshold is selected by the pattern detection process,
The thin line is saved. Furthermore, for pixels other than those determined to be thin lines and edges, by performing density preservation processing,
Moire that occurs when a pseudo intermediate image is processed can be reduced. As described above, the density conversion processing method can be applied to any method as long as the density conversion processing method is such that the changed pixels are once converted into multi-valued data in the process.

<Seventh Embodiment> Next, a seventh embodiment will be described. FIG. 34 is a block diagram showing the structure of the image processing apparatus according to the seventh embodiment. In the figure, 34
1 is a converted pixel value calculation unit, 342 is a pattern detection processing unit,
Reference numeral 343 represents a simple binarization processing unit, and 344 represents a binarization threshold value selection unit. In the above configuration, as shown in FIG. 2, the input image is synchronized with the line sync signal, and the image data for one line is synchronized with the page sync signal to
Image data for a page is input in synchronization with the image synchronization clock.

More specifically, the converted pixel value calculation unit 34
Reference numeral 1 calculates a converted pixel value by a projection method or the like and controls each synchronization signal. The pattern detection processing unit 342 performs pattern matching between a preset pattern and the original image pattern. The simple binarization processing unit 343 performs binarization processing of the converted pixel value using the threshold value determined by the binarization threshold value selection unit 344 from the pattern detection processing result. As described above, in the present embodiment, an example of the image processing apparatus that does not include the density storage binarization processing unit, the pixel value reduction processing unit, and the detection result reduction processing unit will be given.

FIG. 35 is a block diagram showing the structure of the converted pixel value calculation unit 341 according to the seventh embodiment. In the figure, 351 is a conversion pixel position calculation unit, 352 is a reference pixel extraction unit, 353 is an area calculation unit, 354 is an average density calculation unit,
Reference numerals 355 respectively indicate the synchronization signal control units.

In the above configuration, the converted pixel position calculation unit 3
51 calculates the relative position of the converted pixel projected on the original image. The reference pixel position calculation unit 352 extracts an original pixel having a pixel surface that appears in the pixel of the conversion pixel according to the conversion magnification. Specifically, in the case shown in FIG. 3, I _P , I _Q , and I
_Take out _R and I _S. The area calculation unit 353 calculates the pixel surface area of the original image included in the pixel surface of the converted pixel. Figure 3
In the case of the example shown in, the calculation of S _P , S _Q , S _R , and S _S is performed. The average density calculator 354 calculates the average density of the converted pixels using the reference pixel value and the area calculation result. In the example of FIG. 3, the calculation of the expression (1) is performed. Generally, the number of pixels referred to varies depending on the conversion magnification, and the average density of the converted pixels is obtained by the calculation represented by the following equation (8). That is,

[0059]

[Equation 4] Is. Here, I _n is the average density or brightness of the target pixel n, I _K is the density or brightness of the original pixel K having a pixel surface overlapping the pixel surface of the target pixel n on the projection surface, and S _K is the original pixel K. Area of the pixel surface of the converted pixel n.

FIG. 36 is a block diagram showing the structure of the synchronizing signal controller according to the seventh embodiment. In the figure, 36
1 is a pixel number counter, 362 and 365 are ROMs, 36
Reference numeral 3366 indicates a logical product gate and reference numeral 364 indicates a line counter.

In the above configuration, each counter output (to the address below) and conversion rate (to the higher address) are stored in the ROM.
, And outputs a periodic thinning pattern according to a preprogrammed magnification. Further, the logical product of the thinning pattern and the thinning pattern is used to obtain the thinning sync signal (output sync signal) necessary for the reduction conversion.

As described above, according to the seventh embodiment, the average density of the converted pixels obtained by the projection method is binarized by the threshold value selected according to the pattern of the original image, thereby reducing It is possible to prevent the thin lines from coming off.

The pattern detection processing unit is not limited to the method described in the above-mentioned first to seventh embodiments, but may be any method. For example, the window size of the reference pixel is not limited to 4 × 4 shown in the embodiment and may be any size. Further, the thin line pattern is not limited to the case shown in the embodiment, and various patterns such as a slanted line pattern and a thin line pattern having a width of 2 pixels may be applied. Further, not only simple pattern detection by template matching, but also pattern detection by characteristic parameters such as periodicity and spatial frequency in the reference window can be considered.

Further, the pixel value reduction processing unit is not limited to the average value processing shown in the above-described first to seventh embodiments, and the simplest example may be any processing such as thinning processing. Further, the detection result reduction processing is not limited to the examples shown in the above-mentioned respective embodiments, and various ones can be considered in consideration of image quality. Furthermore, although the above two reductions have been described in the case of 1/2 times, in the present invention, it is possible to convert to a smaller magnification by expanding the reference window.

Further, the density preservation binarization process is not limited to the error diffusion method as in the first to seventh embodiments, and any process can be used as long as it is a concentration preservation binarization process. .. FIG. 22 is a block diagram showing the density storage binarization unit by the minimum average error method. The average density of the converted pixels obtained by the pixel value calculation processing unit is the error data e between the previously generated input data X _{i, j} and output data Y _{i, j} stored in the error buffer memory 220. _The weighting coefficient a designated by the weighting generator 221 for generating the weighting coefficient for _{i, j}
A value obtained by multiplying _{i, j} is standardized and added by the adder 222. When this is written as an expression, it becomes as shown in the following expression (9). That is,

[0066]

[Equation 5] Is. FIG. 23 shows an example of the weighting coefficient applied to the above equation (9).

The correction data X _{i, j '} is compared with a threshold value in the binarization circuit 223, and output data Y _{i, j} is output. Where Y
_{i, j} are binarized to "1" or "0". On the other hand, in the calculator 224, the difference e between the correction data and the output data Y _{i, j
i, j} is calculated and the result is stored in the corresponding pixel location 225 in the error buffer memory. By repeating the above operation, the density preservation binarization processing is executed, and an effect of suppressing moire when the pseudo halftone image is converted is obtained.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0069]

As described above, according to the present invention,
In a pixel density conversion device that uses a projection method or other interpolation method, it is possible to reduce thin lines that are missing or collapsed at the time of reduction, and it is also possible to perform good pixel density conversion processing on documents that include pseudo-halftone images. become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart of signals and data according to the first embodiment.

FIG. 3 is a diagram illustrating the principle of the projection method according to the first embodiment.

FIG. 4 is a diagram showing an example in which 16 pixels are referred to by a projection method in the first embodiment.

FIG. 5 is a block diagram showing a configuration of a conversion pixel value calculation unit 11 by a projection method according to the first embodiment.

FIG. 6 is a block diagram showing a configuration of a synchronization signal controller according to the first embodiment.

FIG. 7 is a timing chart regarding main scanning at a conversion magnification of 2/3 according to the first embodiment.

FIG. 8 is a block diagram showing the configuration of a pixel value reduction processing unit according to the first embodiment.

9 is a diagram illustrating reference pixels of the pixel value reduction processing unit in FIG.

FIG. 10 is a block diagram showing the configuration of a pattern detection processing unit according to the first embodiment.

FIG. 11 is a diagram illustrating reference pixel points in the pattern detection processing unit of FIG. 10 according to the first embodiment.

FIG. 12 is a diagram showing an example of a thin line and an edge pattern according to the first embodiment.

FIG. 13 is a block diagram showing the configuration of a detection result reduction processing unit according to the first embodiment.

FIG. 14 is a block diagram showing a configuration of a binarization threshold value selection unit and a simple binarization processing unit according to the first embodiment.

FIG. 15 is a diagram showing an example of black thin line disappearance by a projection method in the first embodiment.

FIG. 16 is a diagram showing an example of saving a black thin line according to the first embodiment.

FIG. 17 is a block diagram showing a configuration of a binarization processing unit according to the first embodiment, and FIG. 18 is a diagram explaining an error diffusion position according to the first embodiment.

FIG. 18 is a diagram illustrating an error diffusion position according to the first embodiment.

FIG. 19 is a diagram illustrating the principle of the linear interpolation method according to the second embodiment.

FIG. 20 is a diagram showing an example of disappearance of a black thin line by the linear interpolation method according to the second embodiment.

FIG. 21 is a diagram showing an example of saving a black thin line according to the second embodiment.

FIG. 22 is a block diagram showing a density storage binarization unit by the minimum average error method.

FIG. 23 is a diagram showing an example of weighting coefficients.

FIG. 24 is a block diagram showing the configuration of an image processing apparatus according to a third embodiment.

FIG. 25 is a block diagram showing the configuration of an image processing apparatus according to a fourth embodiment.

FIG. 26 is a diagram showing a fine line detection pattern according to the fourth embodiment.

FIG. 27 is a block diagram showing the configuration of an image processing apparatus according to a fifth embodiment.

FIG. 28 is a diagram showing an example of black thin line disappearance by a projection method.

FIG. 29 is a diagram showing an example of saving a black fine line according to the fifth embodiment.

FIG. 30 is a diagram showing an example of white thin line disappearance by a projection method.

FIG. 31 is a diagram showing an example of white thin line storage according to the fifth embodiment.

FIG. 32 is a diagram showing an example of disappearance of a black thin line.

FIG. 33 is a diagram showing an example of saving a black fine line according to the sixth embodiment.

FIG. 34 is a block diagram showing the configuration of an image processing apparatus according to a seventh embodiment.

FIG. 35 is a conversion pixel value calculation unit 341 according to the seventh embodiment.
3 is a block diagram showing the configuration of FIG.

FIG. 36 is a block diagram showing the configuration of a synchronization signal controller according to the seventh embodiment.

[Explanation of symbols]

11, 241, 251, 271, 341 Converted pixel value calculation unit 12, 242, 252, 272, 342 Pattern detection processing unit 13, 243, 253 Pixel value reduction processing unit 14, 15, 244, 254 Detection result reduction processing unit 16 , 245, 255, 273, 343 Simple binarization processing unit 17, 256, 274, 344 Binarization threshold value selection unit 18, 246, 275 Concentration preservation binarization processing unit 19, 144, 247, 276 selection unit 51, 351 Conversion pixel position calculation unit 52,352 Reference pixel extraction unit 53,353 Area calculation unit 54,354 Average density calculation unit 55,355 Synchronous signal control unit 61,361 Pixel counter 62,65,103,362,365 ROM 63 , 66, 365, 366 AND gate 64 line counter 81, 131, 173 line buffer 82a to 82d, 102a to 102m, 132a to 13
2d 1-pixel delay element 83 Average value processing section 84 Sync signal thinning-out processing section 85, 104, 134, 141-143 Registers 101a-101c 1-line delay element 133 Detection result conversion operation section 145 Comparator 171a-171d 1-pixel delay element 172a To 172d, 222 adder 174 binarization processing unit 175 binarization error calculation unit 176 error distribution unit 220 error buffer memory 221 weighting circuit 223 binarization circuit 224 calculator 225 pixel position

Claims (9)

[Claims] 1. A detecting means for detecting a preset pattern based on an original image, a first reducing means for reducing a pixel value of the original image, and a pixel value reduced by the first reducing means. Second reducing means for reducing, a third reducing means for reducing the detection result obtained by the detecting means, and a first binarizing means for binarizing the pixel value reduced by the second reducing means. A method different from that of the first binarizing unit for the same pixel value as the pixel value when binarizing by the first binarizing unit based on the detection result reduced by the third reducing unit. Second binarizing means for binarizing with, and the binarizing result obtained by the second binarizing means when the pattern is detected by the detecting means is selected, and the pattern is detected by the detecting means. Selection means for selecting the binarization result obtained by the first binarization means when not detecting The image processing apparatus according to claim and. 2. The second binarizing means comprises a storage means for storing a plurality of threshold values in advance, and a plurality of threshold values stored in the storage means based on a detection result reduced by the third reducing means. A threshold value selecting means for selecting one threshold value and a simple binarizing the pixel value similar to the pixel value when binarizing by the first binarizing means based on the threshold value selected by the threshold value selecting means. The image processing apparatus according to claim 1, further comprising a simple binarization unit. 3. A detecting means for detecting a preset pattern based on an original image, a first reducing means for reducing a pixel value of the original image, and a pixel value reduced by the first reducing means. Second reducing means for reducing, a third reducing means for reducing the detection result obtained by the detecting means, and a first binarizing means for binarizing the pixel value reduced by the second reducing means. A second binarizing means for binarizing the pixel value reduced by the second reducing means by a method different from the first binarizing means,
When the pattern is detected by the detecting means, the second
Selecting means for selecting the binarization result obtained by the binarization means and selecting the binarization result obtained by the first binarization means when the pattern is not detected by the detection means. An image processing device characterized by the above. 4. A detecting means for detecting a preset pattern based on an original image, a first reducing means for reducing a pixel value of the original image, and a pixel value reduced by the first reducing means. Second reducing means, a third reducing means for reducing the detection result obtained by the detecting means, and a pixel reduced by the second reducing means based on the detection result reduced by the third reducing means. An image processing apparatus, comprising: a binarizing unit that binarizes a value. 5. The binarizing means stores a plurality of threshold values in advance, and one threshold value among the plurality of threshold values stored in the storage means based on the detection result reduced by the third reducing means. 5. The image processing apparatus according to claim 4, further comprising: a threshold value selecting unit for selecting the pixel value, and a simple binarizing unit for binarizing the pixel value based on the threshold value selected by the threshold value selecting unit. 6. A detection means for detecting a preset pattern based on an original image, a reduction means for reducing the pixel value of the original image, and a first means for binarizing the pixel value reduced by the reduction means. The binarization means and the first binarization means have the same pixel value as the pixel value when binarized by the first binarization means based on the detection result obtained by the detection means. Second binarizing means for binarizing by a different method, and a binarizing result obtained by the second binarizing means when the pattern is detected by the detecting means is selected by the detecting means. An image processing apparatus comprising: a selection unit that selects a binarization result obtained by the first binarization unit when the pattern is not detected. 7. The second binarizing means stores a plurality of threshold values in advance, and one threshold value from the plurality of threshold values stored in the storage means based on a detection result obtained by the detecting means. And a simple binary for binarizing a pixel value similar to the pixel value when binarizing by the first binarizing means based on the threshold selected by the threshold selecting means. The image processing device according to claim 6, further comprising: 8. A detecting means for detecting a preset pattern based on the original image, a reducing means for reducing the pixel value of the original image, and a reducing means for reducing the pixel value based on the detection result obtained by the detecting means. An image processing apparatus, characterized by: a binarizing unit that binarizes the pixel value. 9. The binarizing means selects one threshold value from a plurality of threshold values stored in the storage means based on a detection result obtained by the detection means and a storage means for storing a plurality of threshold values in advance. 9. The image processing according to claim 8, further comprising: threshold value selecting means; and simple binarizing means for binarizing the pixel value reduced by the reducing means based on the threshold value selected by the threshold value selecting means. apparatus.