JPS6255334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes digital signal processing to perform single sideband frequency division multiplexing (hereinafter referred to as SSB-) of baseband signals.
The present invention relates to a single sideband frequency division multiplexing signal modulation device for multiplexing a signal (abbreviated as FDM signal).

In recent years, digital signal processing has enabled SSB-FDM
Attempts have been made to realize modulation and demodulation of signals. As a well-known method for modulating SSB-FDM signals through digital signal processing, IEEE
TRANSACTION ON COMMUNICATIONS,
VOL.COM−26, No.5, MAY1978, PP720−725
“An Improved Method for Digital SSB”
−FDM Modulation and Demodulation”.

Here, the principle of the above method will be briefly explained. Now, the sampling frequency of the baseband signal is s (the unit Hz is omitted below), SSB−FDM
Let the sampling frequency of the signal be N·s. However, N is a positive integer. Let the Z transformation of the sample value sequence of N baseband signals be X _k (Z ^N ) (where k = 0, 1, ..., N-1), and SSB-
Let the sample value sequence of the FDM signal be Y(Z).

Since the baseband signal has a spectrum with a periodic structure that repeats at a frequency s, N bandpass filters each having a bandwidth s/2 whose center frequency is shifted by s/2 are prepared, and each filter filters the N baseband signals into the above band. After inputting the signal to the filter, the SSB-FDM signal can be obtained by adding the N filter outputs.

Here, as the N band filters, consider a real low-pass filter G(Z) with a bandwidth of s/4, and a complex band filter H k (Z) with a bandwidth of s/2 which is obtained by frequency shifting the real low-pass filter _G (Z). Can be used. In other words, the center frequency of _k (Z) is (4k+
1) When s/4, the filter G(Z)
If we apply a frequency shift of (4k+1)・s/4 to H _k (Z) = H _k [exp{j2π/N・s}] = G[exp{j2π(−4k+1/4・s)/N・s}] = G[Z・exp{−j2π4k+1/4N}] …(1) Here, the complex band filter H expressed by equation (1)
Although _k (Z) operates at the sampling frequency N・s, the input is only given at the frequency s, so H _k (Z) is realized by decomposing it into N sets of filters that operate at the sampling frequency s. can do.

Real low-pass filter G with bandwidth s/4
When (Z) is decomposed into N sets of filters, the result is as follows.

Substituting equation (2) into equation (1), we get get. SSB-FDM signal sample value series Y
(Z) is X _k for k=0, 1, ..., N-1
(Z ^N ) is passed through a filter H _k (Z) and the outputs are added, so holds true. Substituting equation (3) into equation (4), however is obtained. The complex band filter bank of G _i (-jZ ^N ) in equation (5) is called a polyphase digital filter.

Here, the complex band filter G _i (−jZ ^N ) is expressed by the formula (2)
The transfer function is defined by substituting -jZ ^N in place of Z ^N in the transfer function of the real low-pass filter G _i (Z ^N ) defined by .

As mentioned above, the complex band filter G _i (−
jZ ^N ) requires the same amount of multiplication as two sets of real band filters because the filter coefficients are real numbers or pure imaginary numbers.

By the way, SSB by digital signal processing
In modulation and demodulation systems for FDM signals, the scale of the equipment and, in turn, the price of the equipment are determined by the number of multiplications required per unit time, so a hardware configuration with essentially a small number of multiplications per unit time is required. Ru. In particular, the amount of multiplication required for a polyphase digital filter is considerably larger than that of the offset discrete Fourier operation expressed by equation (6), so
It is desired to reduce this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single sideband frequency division multiplex signal modulation device that requires fewer multiplications per unit time than the prior art and has a small hardware scale.

First, let us consider dividing the complex band filter G _i (-jZ ^N ), which is a component of a polyphase circuit, into a real part and an imaginary part and realizing it as two real band filters.

From equations (5) and (6), if expressed using complex conjugate, Y
(Z) is as shown in the following equation.

Here, if G _i (−jZ ^N ) and G _i (+jZ ^N ) are each further decomposed into two, get. In equation (6), since X _k (Z ^N ) is a real number, I _n [Ai ^* (Z ^N )] = R _e [A _N-1 (Z ^N )] (where i≠0), and this relationship Using equation (8), equation (7)
If you transform is obtained. However, R _e [ ] and I _n [ ]
denote the real and imaginary parts, respectively. Also expression
In (9), when i=0, the second term on the right side is zero.

As is clear from equation (8), the complex band filter G _i
(-jZ ^N ) is two real band filters G _i , ₀ (-Z ^2
N ) and G _i , ₁ (−Z ^2N ).

Next, the real band filter G _i , ₀ (−Z ^2N ) and G
A method for reducing the amount of multiplication of _i , ₁ (-Z ^2N ) will be described. Transfer function G of the real low-pass filter shown by equation (2)
(Z) is expressed as follows.

G(Z)={a ₀ Z ⁰ +a ₁ Z ^-1 +a ₂ Z ^-2 +...+a _2nN-1 Z ^-(2mN-1) }/U(Z ^2N )...(10) However, m is positive be an integer.

In equation (10), it is possible to design a filter G(Z) in which the coefficient of the numerator term satisfies the condition of the following equation.

From equation (10), when i=0, the transfer function of each sub-filter in equation (9) is as shown in the following equation.

In equation (12), the following function holds true from conditional equation (11).

Therefore, in equation (12), G _i , ₀ (Z ^2N ) and G _Ni ,
The coefficients of the numerator terms of ₁ (Z ^2N ) are mutually symmetric functions, and the transfer functions of the denominators are the same. Furthermore, as is clear from equation (9), since the inputs of the two sub-filters are the same, it is possible to reduce the amount of multiplication by utilizing the symmetry of the coefficients.

The present invention based on the above principle will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining the functions of the present invention. In Figure 1, 10 (0), 10
(1), 10 (2), ..., 10 (N-2), 10
(N-1) is an input terminal, 200 is a spectrum inversion circuit, 300 is an offset discrete Fourier processing circuit, 40(0), 40(1), 40(2),...,
40(N-2), 40(N-1) are polyphase digital filters, 40(0)0, 40(1)
0,40 (1) 1,40 (2) 0,40 (2)
1,...,40(N-2)0,40(N-2)
1,40(N-1)0,40(N-1)1 is the output of the polyphase digital filter, 50
(1), 50 (2), ..., 50 (N-2), 50
(N-1) is a subtracter, 600 is a multiplex circuit, 700
is the output terminal.

In FIG. 1, N baseband signals X _k
(Z ^N ) (k=0, 1, ..., N-1) are the input terminals 10 (0), 10 (1), 10 (2),
. The spectrum inversion circuit 200 performs a multiplication operation of (-1) ⁿ (where n is a time index) on predetermined N/2 baseband signals to invert the spectrum of the signal. The N outputs of the spectrum inversion circuit 200 are input to the offset discrete Fourier processing circuit 300, where the calculation of equation (6) is performed. Offset discrete Fourier processing circuit 30
Of the N complex outputs of 0, only the real part outputs are sent to the polyphase digital filter 40.
(0),40(1),40(2),...,40(N-
2), 40(N-1). Polyphase digital filter 40(0), 40(1), 4
0(2),...,40(N-2),40(N-1)
and subtractors 50(1), 50(2), ..., 50
(N-2), 50(N-2) performs the filter operation of equation (9). Furthermore, the output of the polyphase digital filter 40(0)0 and the subtracter 5
0 (1), 50 (2), ..., 50 (N-2), 5
The outputs of 0(N-2) become the inputs of the multiplexing circuit 600, and are respectively Z ⁰ , Z ^-1 , Z ^-2 , ..., Z ^-(N- 2 ⁾ ,
After receiving a delay of Z ^-(N-1) , the output terminal 700 receives
An SSB-FDM signal Y(Z) is obtained.

Next, the polyphase digital filters 40(0), 40(1), 40(2), . . . , 4 shown in FIG.
0(N-2) and 40(N-1) will be explained in detail. The calculation formula for the polyphase digital filter is expressed by formula (9).

However, in equation (9), when i=0, the second
The term is set to zero. From equation (9), when i≠0, R _e [A _i
(Z ^N )] is G _i , ₀
(-Z ^2N ) and Z ^-N・G _Ni , ₁ (-Z ^2N ), which is the polyphase digital filter 40
This corresponds to (i). Polyphase digital filter 40
The two outputs 40(i)0 and 40(i)1 of (i) have the transfer functions G _i , ₀ (−Z ^2N ) and Z ^−N ·G _N− respectively.
Corresponds to the output of _i , ₁ (-Z ^2N ). Furthermore, when i=0, the second term on the right side of equation (9) is zero, so the transfer function of the polyphase digital filter 40(0) may be G _i , ₀ (-Z ^2N ).

Next, a method for realizing the polyphase digital filter will be described. As is clear from equations (12) and (13), the transfer functions G _i , ₀ (−Z ^2N ) and G _N−
The coefficients of the numerator term of _i , ₁ (-Z ^2N ) have symmetry (however, when i≠0), and the coefficients of the denominator are the same, so as shown in Figure 2a, the polyphase digital Filters can be configured.
FIG. 2a shows a configuration of the polyphase digital filter 40(i) (where i≠0) shown in FIG.

In FIG. 2a, 10 is an input terminal, and 71 and 72 are output terminals. 21, 22, 23 and 24 are multipliers for multiplying the coefficients of the numerator of the transfer function; 31, 32, 33, 34, 35 and 36;
is a multiplier for multiplying the coefficient of the denominator of the transfer function. Also, 41, 42, ..., 47 and 48
are adders/subtractors, 51, 52, ..., 55 and 56
is a Z ^-2N delay element, and 61 is a Z ^-N delay element. Signal R _e [A _i
(Z ^N )] is input to multipliers 21, 22, 23 and 24 and is multiplied by the numerator coefficient. multiplier 21,
The outputs of 22, 23 and 24 become inputs of adders/subtractors 41 and 48, 42 and 47, 43 and 46, 44 and 45, respectively. On the other hand, the output of the adder/subtractor 44 becomes the input of the multipliers 31, 32, and 33, and is multiplied by the denominator coefficient. Further, the outputs of multipliers 31, 32 and 33 become inputs of adders/subtractors 41, 42 and 43, respectively. The input and output of the adder/subtractor 41, delay element 51, adder/subtractor 42, delay element 52, adder/subtracter 43, delay element 53, and adder/subtractor 44 are connected in this order.
Therefore, the transfer function from the input terminal 10 to the output terminal 71 receiving the output of the adder/subtractor 44 is G _i , ₀
(−Z ^2N ).

On the other hand, the output of the adder/subtractor 48 becomes an input to the delay element 61, and also serves as an input to the multipliers 34, 35, and 36.
is input and multiplied by the denominator coefficient. Furthermore, the outputs of multipliers 34, 35 and 36 become inputs to adders 45, 46 and 47, respectively. Adder/subtractor 4
5, delay element 54, adder/subtractor 46, delay element 5
5. The input and output of the adder/subtractor 47, the delay element 56, and the adder/subtractor 48 are connected in this order. Therefore, the transfer function from the input terminal 10 to the output terminal 72 that receives the output of the delay element 61 is Z ^-N・G _Ni , ₁
(−Z ^2N ).

FIG. 2b shows the structure of the polyphase digital filter 40(0) shown in FIG. In FIG. 2b, 10 and 71 indicate an input terminal and an output terminal, respectively. 21, 22
and 23 are multipliers for multiplying the coefficients of the numerator of the transfer function; 31, 32, and 32 are multipliers for multiplying the coefficients of the denominator of the transfer function; 41, 4;
2, 43 and 44 are adders/subtractors, and 51, 52 and 53 are Z ^-2N delay elements. The configuration shown in FIG _. 2B is exactly the same as the one side ^of the block diagram shown in _FIG . In Figures 2a and b, a third-order example is shown for the filters G _i , ₀ (-Z ^2N ) and G _Ni , ₁ (-Z ^2N ), but a similar configuration can be easily implemented even when the order increases. It is possible to think about it.

In the block diagram for explaining the functions of the present invention shown in FIG. 1, the polyphase circuit has the configurations shown in FIGS. 2a and 2b. In Figure 2a, if the number of multipliers for multiplying the coefficient of the transfer function of the numerator term is m, the number of multipliers for multiplying the coefficient of the transfer function of the denominator term is (2m-1). , In the current configuration, the number of multipliers is still large. Furthermore, the number of Z ^-2N delay elements is 2m.
Therefore, consider the time division multiplexing configuration of the block diagram shown in FIG.

FIG. 3 is a block diagram showing an embodiment of the present invention, in which 10 is an input terminal, 20 is a spectrum inversion circuit, 30 is an offset discrete Fourier processing circuit, and 4 is a block diagram showing an embodiment of the present invention.
0 is a polyphase circuit, and 50 is an output terminal.
This figure is a block diagram when the circuit of FIG. 1 is configured in a multiplexed manner. That is, N baseband signals are time-division multiplexed and input to the input terminal 10 every s. Therefore, one frame is 1/s second, during which N pieces of data are time-division multiplexed. The spectrum inversion circuit 20 multiplies predetermined N/2 signals by (-1) for odd (or even) frames. The output of the spectrum inversion circuit 20 is input to an offset discrete Fourier processing circuit 30, where the following calculation is performed.

However, in equation (14), X _k (Z ^N ) represents the output of the spectrum inversion circuit 20. Therefore, at the output of the offset discrete Fourier processing circuit 30, one frame consists of A ^R ₀ , (Z ^N ), A ^R ₁ (Z ^N ), ..., A
^RN _-1
N pieces of data (Z ^N ) are time-division multiplexed,
The signal is input to the polyphase circuit 40. The output terminal 50 that receives the output of the polyphase circuit 40 has an SSB
-FDM signal is obtained.

Next, the polyphase circuit 40 shown in FIG. 3 will be explained in detail. FIG. 4 shows a block diagram of the polyphase circuit shown in FIG. 3, and FIG. 5 is a timing chart for explaining the operation of FIG. 110 and 190 are input terminals and output terminals, respectively; 131, 132, 133 and 134 are multipliers for multiplying the coefficients of the numerator term of the transfer function; and 141, 142 and 143 are multipliers for multiplying the coefficients of the denominator term of the transfer function. multiplier, 1
51, 152, 153, 154, 155, 156
and 157 is a Z ^-N delay element, 161, 16
2,163,164,165,166 and 16
7 is an adder/subtractor, 171, 172, 173 and 1
74 is a switch, and 120 and 180 are array conversion memories.

The output of the offset discrete Fourier processing circuit 30 shown in FIG. 3 is input to the input terminal 110. Here, it is assumed that the frame configuration of the input terminal 10 is a timing chart as shown in FIG. 5A. The numbers in FIG. 5A are R _e [A _i
(Z ^N )]. 1 frame (=Z ^-
N = 1/s) assumes that N pieces of data are time-division multiplexed. Data input to the input terminal 110 is input to the array conversion memory 120. In the array conversion memory 120, for the data input to the input terminal 110, even number (or odd number) frame data is rearranged into (N-1) pieces of data in reverse order as shown in the timing chart of FIG. 5B. Do the following. The numbers in Figure 5B are R _e [A _i (Z
^N )] corresponds to i. At this time, the order of data in odd (or even) frames is the same as the input data order. The output of the array conversion memory 120 is sent to multipliers 131, 132, 133 and 13.
4 inputs. The output of the multiplier 131 is input to the Z ^-N delay element 151 via the switch 171, and is also input to the adder/subtractor 171 at the same time.
The output of the multiplier 132 is input to the adder/subtracter 161, and at the same time, the output is input to the adder/subtracter 161 via the switch 174.
66 is also input. The output of the multiplier 133 is input to the adder/subtracter 162 via the switch 172 and is also input to the adder/subtracter 165 at the same time. Furthermore, the output of the multiplier 134 is input to the adder/subtracter 163 and simultaneously passed through the switch 173 to the adder/subtractor 163.
4 is also input. Further, the output of the adder/subtractor 167 is input to multipliers 141, 142, and 143. The outputs of multipliers 141, 142 and 142 are outputted from adder/subtractors 161, 163 and 165, respectively.
is input.

Here, multipliers 131, 132, 133 and 1
34 is G _i , ₀ (−Z ^2N ) and G _Ni , ₁ of formula (9)
This is a multiplier for multiplying the coefficient of the numerator term of (-Z ^2N ). As is clear from equations (12) and (13), the coefficients of the numerator terms of G _i , ₀ (−Z ^2N ) and G _Ni , ₁ (−Z ^2N ) have symmetry with each other, so their multiplication It is possible to reduce the number of times to 1/2. Multiplier 1
The coefficients 31, 132, 133 and 134 need to be changed in a time-division manner. On the other hand, multiplier 14
1,142 and 143 are G _i , ₀ (−Z ²
This is a multiplier for multiplying the coefficients of the denominator terms of ^N ) and G _Ni , ₁ (-Z ^2N ). As is clear from equation (12), the coefficients of the denominator terms of G _i , ₀ (-Z ^2N ) and G _Ni (-Z ^2N ) are the same and do not depend on i, so multipliers 141, 142 and 143 The coefficient of can always be constant.

When configured as shown in Fig. 4, the output of the filter G _i , ₀ (-Z ^2N ) of the first term on the right side of equation (9) is as shown in Fig. 5 C
Virtually appears at the output of the adder/subtractor 167 in the form shown in the timing chart shown in FIG. Also, since the second term on the right side of equation (9) is zero when i=0, at this time switches 171, 172, 173 and 174
is open. When i=1, 2, . . . , N-1, switches 171, 172, 173 and 174 operate to close. The output of the filter Z ^-N G _Ni , ₁ (-Z ^2N ) in the second term on the right side of equation (9) is virtually the output of the adder/subtractor 167 in a form like the timing chart shown in FIG. 5D. appears in Actually, adders/subtractors 161, 162, 163, 164,
165, 166, and 167 perform the operation on the right side of equation (9), and output the result to adder/subtractor 167. The numbers shown in FIG. 5C, D, and E correspond to i in equation (5). The output of the adder/subtractor 167 is input to the array conversion memory 180. Array conversion memory 18
0, the array transformation that is completely opposite to that of the array transformation memory 120 is performed on even (or odd) frames.
Therefore, when the right side of equation (9) is expressed as the following equation, At the output terminal 190, N Y _i (Z ^N ) are connected to the fifth
The timing chart shown in Figure F is output. In Figure 5F, the numbers are Y _i of equation (14)
(Z ^N ) corresponds to i. Although FIG. 4 shows a third-order polyphase digital filter to simplify the explanation, a similar configuration can be easily considered even when the number of orders increases.

As described above, by using the present invention, it is possible to reduce the number of multipliers required for a polyphase digital filter to 1/2 that of the conventional one, and therefore, a single sideband frequency division multiplexing signal modulation device with small hardware scale can be realized. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the functions of the present invention.
..., 10(N-2) and 10(N-1) are input terminals, 200 is a spectrum inversion circuit, 300 is an offset discrete Fourier processing circuit, 40(0),
40(1), 40(2),..., 40(N-2) and 40(N-1) are polyphase digital filters, 50(1), 50(2),..., 50(N-1)
-2) and 50 (N-1) are subtracters, 600 is a multiplexing circuit, and 700 is an output terminal. FIG. 2 is a block diagram for explaining the polyphase digital filter of FIG. 1, where 10 is an input terminal, 21, 22, 23, 24, 31, 32,
33, 34, 35 and 36 are multipliers, 41, 4
2, 43, 44, 45, 46, 47 and 47 are adders/subtractors, 51, 52, 53, 54, 55 and 56 are Z ^-2N delay elements, 61 is a Z ^-N delay element, 71 and 72 are outputs It is a terminal. FIG. 3 is a block diagram showing an embodiment of the present invention, in which 10 is an input terminal, 20 is a spectrum inversion circuit, 30 is an offset discrete Fourier processing circuit, and 4 is a block diagram showing an embodiment of the present invention.
0 is a polyphase digital filter, and 50 is an output terminal. FIG. 4 is a block diagram for explaining the polyphase digital filter of FIG. 3, in which 110 is an input terminal, 120 is an array conversion memory, 131, 13
2,133,134,141,142 and 14
3 is a multiplier, 151, 152, 153, 154,
155, 156 and 157 are Z ^-N delay elements;
161, 162, 163, 164, 165, 16
6 and 167 are adders/subtractors, 171, 172 and 172 are switches, 180 is an array conversion memory,
190 is an output terminal. FIG. 5 is a timing chart for explaining the operation of FIG. 4.

Claims (1)

[Claims] 1. When obtaining an N-channel single sideband frequency division multiplexed signal from an N-channel baseband signal through digital processing using a spectrum inversion circuit, an offset discrete Fourier processing circuit, and a polyphase circuit consisting of a plurality of digital filters, 1.
When a frame is the reciprocal of the sampling frequency of each of the N-channel baseband signals, one frame consists of N multiplexed real signal sequences.The real part output of the offset discrete Fourier processing circuit is input, and even (or odd) frames a first array conversion memory that performs array conversion of N pieces of data; and a first array conversion memory that uses the output of the first array conversion memory as a common input and multiplies K types of coefficients that change in a time-division manner. Multiplier ({M _k }: k=1, 2,...
..., K) and K switches ({S _k }: k= ₁ , 2,...
..., K) and K adders/subtractors ({A _k }: k=1, 2,
..., K) and (K-1) switches ( _{{S k }} : k=2,
(K-1) adders/subtractors ({B _k }: k=2, 3, ..., K) whose inputs are the outputs of 3, ..., K)
The output of one adder/subtractor _A1 of the K adders/subtractors {A _k } is used as a common input, and each is multiplied by a constant coefficient, and the output of each adder/subtractor {A _k } is (K-1) adders/subtractors ({A
_k }:k=2,3,...,K) (K-
1) multipliers ({F _k }: k=1, 2, ..., K
-1), one switch S ₁ of the K switches, A K of the K adders/subtractors {A _k }, and A _K of the (K-1) adders/subtractors {B _k }. ,
B ₂ , A _K-1 , B ₃ ... _, (2K-1) delay elements ({D _k }: k=1 _, 2 ,...,2K−
1), and a second array transformation in which the output of one adder/subtractor _A1 of the K adders/subtractors {A _k } is input, and array transformation of N pieces of data is performed for an even (or odd) frame. The polyphase circuit is configured from a memory, and the output of each of the (2K-1) delay elements {D _k } is connected to the K adder/subtractor {A
_k } and A _K , B ₂ , A _K- 1 , B ₃ , ..., A ₂ , B _K and A ₁ of (K-1) adders/subtractors {B _k }
A single sideband frequency division multiplexing signal modulator, characterized in that the single sideband frequency division multiplexing signal modulator is connected so as to be an input of the signal.