JPS6331975B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single sideband frequency division multiplexing signal demodulation device that demodulates a single sideband frequency division multiplexing (hereinafter abbreviated as SSB-FDM) signal into a baseband signal by digital signal processing.

In recent years, digital signal processing has made SSB-FDM
Attempts are beginning to be made to realize signal modulation and demodulation. As a well-known method for demodulating SSB-FDM signals through digital signal processing, IEEE
TRANSACTION ON COMMUNICATIONS,
VOL, COM−26, No.25, MAY 1978, PP720−
“An Improved Method for
DigitalSSB−FDM Modulation and
There is “Demodulation”.

Here, the principle of the above method will be briefly explained.

Now set the sampling frequency of the baseband signal to f _s
(The unit Hz is omitted below), and the sampling frequency of the SSB-FDM signal is N· _fs . However, N is a positive integer. The Z transformation of the sample value series of N baseband signals is expressed as X _k (Z ^N ) (k=0, 1...
..., N-1), and the Z transformation of the sample value sequence of the SSB-FDM signal is Y(Z).

Here, it operates at a sampling frequency of N・f _s , the center frequency is (4k+1)・f _s /4, and the bandwidth is f _s /2.
Assuming a complex bandpass filter (CBPF) (sufficient attenuation is provided outside this bandwidth), this transfer function is expressed as H _k (Z).

The k-th channel signal is obtained as the real part of the filter output by passing the SSB-FDM signal through a filter H _k (Z), and is expressed as the following equation.

X _k (Z) = R _e [H _k (Z)・Y (Z)] ...(1) Complex band filter H _k (Z) is a real low-pass filter G (Z) with a band of f _s /4 It can be obtained by applying a frequency shift of (4k+1)·f _s /4 to . That is, H _k (Z) = H _k {exp(j2πf/N・f _s )}=G[exp{j2
π(f−(4k+1)f _s /4)/(N·f _s )}] = G{Z·exp(−j2π4k+1/4N)} (2).

Here, in equation (1), considering that X _k (Z) is sampled at the sampling frequency f _s of the baseband signal, G (Z) is sampled at the sampling frequency f _s
It can be constructed by N filters G _i (Z ^N ) operating at . The relationship between G(Z) and G _i (Z _UN ) is as follows: G(Z)= _N-1 〓 ⁱ⁼⁰ Z ^-i・G _i (Z ^N )...(3). Therefore, by substituting equation (3) into equation (2), H _k (Z)= _N-1 〓 〓 ⁱ⁼⁰ Z ^-i・exp(j2π4k+1/4Ni)・G _i (−jZ ^N )... …(Four
) can be expressed as Furthermore, from equations (1) and (4)
If X _k (Z ^N ) _{is the sample value series when X k} ⁽ _Z ⁾ is sampled at frequency _{f s} , then )・Gi(−jZ ^N )・Y _N-1-i (Z
^N )]...(5) can be obtained. However, Y(Z)= _N-1 〓 ⁱ⁼⁰ Z=n・_Yo (Z ^N )...(6) Here, the complex band filter bank of G _i (-jZ ^N ) in equation (5) is polyfiltered. It's called AIDS Digital.

By the operations briefly described above, SSB−
A baseband signal can be obtained from an FDM signal, but the complex band filter G _i (−jZ ^N ) requires the same amount of multiplication as two sets of real band filters because the filter coefficients are real numbers or pure imaginary numbers. shall be.
By the way, SSB-
In the modulation and demodulation system of FDM signals, the scale of the device and the cost of the device are almost determined by the number of multiplications required per unit time, so a hardware configuration that essentially requires a small number of multiplications per unit time is required. In particular, the amount of multiplication required for polyphase digital occupies more than half of the amount of multiplication for the entire SSB-FDM signal modulation device, and it is desired to reduce this amount.

Furthermore, since the hardware required for the multiplier depends on the coefficient bit length, it is necessary to take measures to shorten the coefficient bit length.

An object of the present invention is to provide a single-sideband frequency division multiplex signal demodulation device with small hardware scale, which allows the number of multiplications per unit time to be reduced and the coefficient precision to be reduced compared to the prior art. be.

First, equation (5) is transformed as follows.

X _k (Z ^N )Re[ _N-1 〓 ⁱ⁼⁰ B _i (Z ^N )・exp(j2π4k+1/4Ni)] …(7) B _i (Z ^N )=G _i (−jZ ^N )・Y _N-1-i
(Z ^N )...(8) However, B _i (Z ^N ) is a sample value sequence of a complex signal. ^Here , if _we further transform _equation ( ₇ ⁾ , _we ^{get :} I _n [B _i (Z ^N )]・Sin (2π4k+1/4Mi) ...(9) However, Re [B _i (Z ^N )] and I _n [B _i (Z ^N )] are respectively B _i ( The sample value series of the real part and imaginary part of Z ^N ) are shown. In equation (9), _N-1 ^{〓 i=0} I _n [B _i (Z ^N )]・Sin (2π4k+1/4Ni) = _N-1 〓 〓 ⁱ⁼⁰ I _n [B _N-1 (Z ^N )]・Sin{2π4k+1/4N(N-i)
} = _N-1 〓 〓 ⁱ⁼⁰ I _n [B _Ni (Z ^N )]・Cos(2π4k+1/4Ni)……(10
) (where I _n [B _N (Z ^N )] = 0), formula (10) can be transformed into
Substituting into (9), X _k (Z ^N ) can be expressed as follows.

X _k (Z ^N )=Re[ _N-1 〓 ⁱ⁼⁰ {R _e [B ⁱ [(Z ^N )]−I _n [B _Ni (Z ^N )]}10 ×exp(j2π4k+1/4Ni) ... (11) However, I _n [B _N (Z ^N )] = 0.

Here, the complex band filter Gi(−
jZ ^N ) is divided into two, G _i (-jZ ^N ) = G _i , ₀ (-Z ^2N ) + jZ ^-N・G _i , ₁
(−Z ^2N )……(12) Therefore, substituting equation (12) into equation (8), B _i (Z ^N )=G _i , ₀ (−Z ^2N )・Y _N-1-i (Z ^N ) +jG _i , ₁ (−Z ^2N )・Y _N-1-i (Z ^N ) ...(13) Therefore, from equations (11) and (13), X _k (Z ^N ) is as follows. It is expressed as

X _k (Z ^N )=Re[ _N-1 〓 ⁱ⁼⁰ C _i (Z ^N )・exp(j2π4k+1/4Ni)] ...(14) However, C _i (Z ^N )=G _i , ₀ (− Z ^2N )・Y _N-1-i (Z ^N )−Z ^-N・G _Ni
, ₁ (−Z ^2N ) Y _i-1 (Z ^N ) (15) In equation (15), when i=0, the second term on the right side is zero.

As is clear from equation (12), the complex band filter G _i
(−jZ ^N ) is two real band filters G _i , ₀ (−Z ^2N )
This can be realized by G _i , ₁ (−Z ^2N ).

Then the real band filters G _i , ₀ (−Z ^2N ) and G _i , ₁
A method for reducing the amount of multiplication (−Z ^2N ) will be described. Formula (3)
The transfer function G(Z) of the actual low-pass filter shown by is expressed as follows.

G (Z) = {a ₀ Z ^o +a ₁ Z ^-1 +a ₂ Z ^-2 +...+a _2nN-1
Z ^-(2mN-1) }/U(Z ^2N )...(16) However, m is a positive integer. It is possible to design a filter G(Z) in which the coefficient of the numerator term in equation (16) satisfies the conditions of the following equation.

a _p = 0 a _2nN-j = aj (j = 1, 2, ..., 2mN-1)
(17) From equation (17), when i≠0, the transfer function of each sub-filter in equation (15) is as shown in the following equation.

G _i , ₀ Y (Z ^2N ) = {aiZ ^o +a _i+2N N ^-2N …+a _i+(2o-2)N Z ^-(
am-2)N /U (Z ^2N ) G _Ni , ₁ (Z ^2N ) {a _2N-i Z ^o +a _4N-i Z ^-2N +...+a _2nN-i Z ^-
(2m-2)N /U(Z ^2N )...(18) In equation (12), the following function holds true from conditional equation (17).

a _2N-i = a _i + (2m-2)N a _2nN-i = a _i ...(19) Therefore, in equation (15), G _i , ₀ (-Z ^N ) and
The coefficients of the numerator terms of G _Ni , ₁ (−Z ^2N ) are symmetrical with each other, and the transfer functions of the denominators are the same. Therefore, it is possible to reduce the amount of multiplication by utilizing the symmetry of the coefficients.

The present invention based on the above principle will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining the functions of the present invention. In the same figure, 100 is an input terminal;
200 is a demultiplexing circuit, 300(0), 300
(1), 300 (2), ..., 300 _(N-2) and 3
00 _(N-1) is N outputs of the demultiplexing circuit 200,
400(0), 400(1), 400(2)...4
00 _(N-2) and 400 _(N-1) are N sub-filters, 500 is an offset discrete Fourier processing circuit,
600 is a spectrum inversion circuit, 700 (0), 7
00(1), 700(2), . . . , 700 _(N-2) and 700 _(N-1) are output terminals.

In FIG. 1, an SSB-FDM signal Y(Z) is input from an input terminal 100 and enters a demultiplexer circuit 200. In the demultiplexing circuit 200, N Y _i (Z ^N ) (i=0, 1, 2, . . . N-2, N-
1) Output can be obtained. Here, Y ₀ (Z ^N ), Y ₁ (Z ^N ),
……, Y _N-3 (Z ^N ), Y _N-2 (Z ^N ) and Y _N-1 (Z ^N )
are 300 (N-1) and 30 in Figure 1, respectively.
0(N-2),...,300(2),300(1)
and 300(0). The output 300(0) of the demultiplexing circuit 200 is sent to the sub-filter 4.
The input is 00 (0). In addition, the demultiplexing circuit 2
The output 300 (1) of 00 is the sub filter 400
(1), and also serves as the second input of sub-filter 400 (N-1). Generally speaking, how to connect the demultiplexing circuit and the sub-filter is that when i=1, 2, 3, ..., N, the output 300(i) of the demultiplexing circuit 200 is connected to the sub-filter 400.
(i) and the sub-filter 400
(N-i) is the second input. Also, i
= 0 is special, and as mentioned above, the output 300 (0) of the demultiplexer circuit 200 is sent to the sub-filter 4.
The input is 00 (0). Therefore, the connection is as shown in FIG. The sub-filter 400(i) is
A filter operation expressed by equation (15) is performed. However, when i=0, the second right-hand side of equation (15)
Note that the term is zero. Sub filter 4
00(i) will be explained in detail later.

N sub-filters 400(0), 400
The outputs of (1), 400(2), ..., 400(N-2) and 400(N-1) are each expressed by formula (15)
C ₀ , C ₁ , _{C 2 , .} The N outputs of the offset discrete Fourier processing circuit are input to a spectral inversion circuit 600. The spectrum inversion circuit 200 performs a multiplication operation of (-1) ⁿ (where n is a time index) on predetermined N/2 baseband signals to invert the spectrum of the signals.

Therefore, N output terminals 700(0), 700
(1), 700 (2), ..., 700 (N-2) and 700 (-1) respectively have baseband signals X ₀ , X ₁ , X ₂ , ..., X _N-2 and X _N-1 is obtained.

Next, the sub-filters 400(0), 40 in FIG.
0(1),400(2),...,400(N-2)
and 400(N-1) will be explained in detail. The arithmetic expression for each of the N sub-filters is expressed by equation (15).

Ci (Z ^N ) = G _i , ₀ (−Z ^2N )・Y _N-1-i (Z ^N ) −Z ^-N・G _Ni , ₁ (−Z ^2N )・Y _i-1 (Z ^N )... ...(15) (i=0, 1, 2,..., N-2, N-1) However, in equation (15), when i=0, the second term on the right side is zero.

The calculation of sub-filter 400(i) is based on i in equation (15).
It corresponds to Here, as is clear from equations (18) and (19), two real band filters G _i , ₀
(−Z ^2N ) and G _Ni , ₁ (−Z ^2N ) have the same denominator transfer function, and the coefficients of the numerator transfer function have symmetry, so the amount of multiplication can be reduced using symmetry. It is possible to consider a filter configuration that makes it possible.

FIG. 2 shows a block diagram of one sub-filter, where a is i=1, 2, ..., N-
2 shows a block diagram of a sub-filter used when i=0, and b shows a block diagram of a sub-filter used when i=0. However, i is the formula (15)
At the same time, the sub-filter 4 in FIG.
It also corresponds to 00(i).

In FIG. 2a, 10 and 20 are both input terminals, 30 is a Z ^-N delay element, 40, 41...,
49 and 50 are adders and subtracters, 51, 52, ...,
55 and 56 are Z ^-2N delay elements, 60, 6
1, 62, ..., 68 and 69 are multipliers, 70
is the output terminal.

The outputs 300(i) and 300(N-i) of the demultiplexing circuit 200 shown in FIG. 1 are input to the input terminals 10 and 20, respectively.

Here, 300(i) and (N-i) correspond to Y _N-1-i (Z ^N ) and Y _i-1 (Z ^N ) in formula (15), respectively. However, it is assumed that i≠0. The signal Y _N-1-i input from the input terminal 10 becomes one input of the adder 40 . Adder 40, Z _-2N delay elements 51, 52
and 53, input and output are connected in this order. The outputs of the Z ^-2N delay elements 51, 52 and 53 are input to multipliers 60, 61 and 62, respectively, and are multiplied by the coefficient of the transfer function of the denominator of the real band filter G _i , ₀ (-Z ^2N ). The outputs of multiplier 61 and 62 are input to adder/subtractor 42 . The output of the adder/subtractor 42 and the output of the multiplier 60 become inputs of the adder/subtractor 41. Further, the output of the adder/subtractor 41 serves as the other input of the adder/subtractor 40. On the other hand, the output of the adder/subtractor 40, Z ^-2N delay elements 51, 52
and 53, the adder/subtractor 46,
45, 44 and 43 are input. Furthermore, the outputs of the adders/subtractors 43, 44, 45, and 46 are input to multipliers 66, 67, 68, and 69, respectively, and multiplied by the coefficient of the numerator transfer function. The outputs of multipliers 66, 67, 68 and 69 are all input to adder/subtractor 50, and the output of adder/subtractor 50 is obtained at terminal 70. Therefore, it can be seen that the transfer function from the input terminal 10 to the output terminal 70 is G _i , ₀ (−Z _2N ).

On the other hand, the signal Y _i-1 is input to the input terminal 20.
It is delayed by the Z ^-N delay element 30. The input and output of the adder/subtractor 47 and the Z ^-2N delay elements 54, 55 and 56 are connected in this order. Delay element 5
The outputs of 4, 55 and 56 are respectively multiplier 6
3, 64 and 65 and are multiplied by the coefficient of the denominator transfer function. The outputs of multipliers 64 and 65 are input to adder/subtractor 49, and the outputs of multiplier 63 and the outputs of adder/subtractor 49 are input to adder/subtractor 47 to form a feedback loop. On the other hand, the output of the adder/subtractor 47, the Z ^-2N delay element 54,
The outputs of 55 and 56 are sent to the adder/subtractor 4, respectively.
3, 44, 45 and 46. Therefore, it can be seen that the transfer function from the input terminal 20 to the output terminal 70 is Z ^-N ·G _Ni , ₁ (-Z ^2N ).
Therefore, at the output terminal 70, C _i (Z ^N ) of equation (15)
can be obtained.

Next, FIG. 2b will be explained. Figure 2b is
This is a block diagram of the sub-filter for i=0 in equation (15).

When i=0, equation (15) becomes as follows.

C ₀ (Z ^N )=G ₀ , ₀ (−Z ^2N )・Y _N-1 (Z ^N ) ...(20) In Fig. 2b, 10 is the input terminal, 40, 4
1, 42, 43, 44 and 45 are adders/subtractors, 5
1, 52 and 53 are Z ^-2N delay elements, 60, 6
1, 62, 63, 64, 65 and 66 are multipliers, and 70 is an output terminal.

Y _N-1 (Z ^N ) of equation (20) is input from the input terminal 10 and becomes an input to the adder/subtractor 40 . Adder/subtractor 40,
The input and output of Z ^-2N delay elements 51, 52 and 53 are connected in this order. Z ^-N delay element 5
The respective outputs of 1, 52 and 53 are input to multipliers 60, 61 and 62, respectively, to obtain the transfer function
The coefficient of the denominator term of G ₀ , ₀ (−Z ^2N ) is multiplied. The output of the multiplier 61 and the output of the multiplier 62 are connected to the adder/subtractor 4.
2, and the output of the multiplier 60 and the output of the adder/subtractor 42 are input to the adder/subtractor 41. Furthermore, the output of the adder/subtracter 41 is input to the adder/subtracter 41 . Furthermore, the output of the adder/subtracter 41 is input to an adder/subtracter 40 to form a feedback loop.
On the other hand, the output of the adder/subtractor 40, the delay element 51 of Z ^-2N
The output of the Z ^-2N delay element 52 and the output of the Z ^-2N delay element 52 and the output of the Z ^-2N delay element 53 are input to multipliers 63, 64, 65 and 66, respectively, and the transfer function The coefficient of the numerator term of G ₀ , ₀ (−Z ^2N ) is multiplied. The output of the multiplier 63 and the output of the multiplier 64 are input to the adder/subtractor 43 , the output of the multiplier 65 and the output of the adder/subtractor 43 are input to the adder/subtractor 44 , and the output of the multiplier 66 and the output of the adder/subtracter 44 are input to the adder/subtracter 44 . The output is input to an adder/subtractor 45. The output of adder/subtractor 45 appears at output terminal 70. Therefore, it is clear that _the transfer function from the input terminal 10 to the output terminal 70 is _G0,0 ( ^-Z2N ).

In the above explanation, the sub-filter shown in FIG.
Although cubic/third-order examples have been given as shown in FIGS. and b, it is easy to consider similar configurations even when the order increases.

In the block diagram for explaining the functions of the present invention shown in FIG. 1, the polyphase circuit has the configurations shown in FIGS. 2a and 2b. In Figure 2a, if the number of multipliers for multiplying the coefficient of the transfer function of the numerator term is m, the number of multipliers for multiplying the transfer function of the denominator term is 2 × (m-1), and as it is, In this configuration, the number of multipliers is still large. Furthermore, 2×(m−1) Z ^−2N delay elements are required. Furthermore, as is clear from FIG. 2, since the polyphase digital filter has a so-called direct type configuration, the required coefficient accuracy becomes large and the hardware of each adder/subtractor increases. Therefore, the first
Considering the time division multiplexing configuration of the block diagram shown in the figure,
At the same time, we will try to reduce the coefficient accuracy.

FIG. 3 is a block diagram of an embodiment of the present invention.
1 is an input terminal, 2 is a polyphase circuit, 3 is an offset discrete Fourier processing circuit, 4 is a spectrum inversion circuit, and 5 is an output terminal. FIG. 3 shows a block diagram when the circuit of FIG. 1 is processed by time division multiplexing.

The SSB-FDM signal Y(Z) is input to the input terminal 1 and becomes an input to the polyphase circuit 2. The operation of the polyphase circuit will be explained in detail later. It is assumed that the output of the polyphase circuit 2 is multiplexed with N words in one frame (1/f _s seconds). In other words, one frame consists of N C _i (Z ^N ) (i=0, 1, 2, ..., N-1) in equation (15).
are multiplexed in ascending order of i. The output of the polyphase circuit 2 is input to an offset discrete Fourier processing circuit 3.

In the offset discrete Fourier processing circuit 3, the calculation of equation (14) is performed, and N baseband signals X _k (Z ^N ) (k=0, 1, 2, . . . , N-1) are obtained. The output of the offset discrete Fourier processing circuit 3 is input to a spectral inversion circuit 4. The spectrum inversion circuit performs a multiplication operation of (-1) ⁿ (where n is a time index) on predetermined N/2 signals, inverts the spectrum of the signal, and outputs the inverted signal. Therefore, the output terminal 5 has N
Baseband signals of channels are time-division multiplexed and output.

Next, the polyphase circuit 2 shown in FIG. 3 will be explained in detail. Figure 4 shows the polyphase circuit 2 of Figure 3.
FIG. 5 is a timing chart of FIG. 4. In FIG. 4, 1 is an input terminal, 6 is an array conversion memory, 7,
8, 9, 11, 12, 13, 14, 15, 16,
17 is an adder/subtractor, 18, 19, 21, 22, 2
3, 24, 25 are multipliers, 26, 27, 28, 2
9, 31, 32, 33 are Z ^-N delay elements, 3
4, 35, 36, and 37 are switches, 38 is an array conversion memory, and 39 is an output terminal.

Further, 41 is a scaler for multiplying input data by 2 ^-l , and 42 is a delay element. However, l is a positive integer. The SSB-FDM signal Y(Z) is input to the input terminal 1. According to equation (6), if Y (Z) is distinguished by N Y _o (Z ^N ) (n = 0, 1..., N-1), the timing chart of Y (Z) is the fifth one.
It will look like Figure A. In this case, the number is n of Y _o (Z ^N )
It corresponds to SSB input from input terminal 1
-FDM signal Y(Z) enters array conversion memory 6.
The array conversion memory 6 converts N data of one frame into even frames (or odd frames).
For , the array is completely reversed, and for parsimonious frames (or even frames), the array is shifted and rotated one word at a time. Therefore, the timing chart of the output of the array conversion memory 6 is as shown in FIG. 5B. At this time, the number corresponds to n in Y _o (Z ^N ). The output of the array conversion memory 6 is input to an adder/subtracter 7. The inputs and outputs of the adders and subtracters 7, 8 and 9 are connected in this order. Further, the output of the adder/subtractor 9 is input to the Z ^−N delay element 33 and the adder/subtractor 11 . Z ^-N delay elements 33, 32, 31, 29, 2
8, 27 and 26 have their inputs and outputs connected in this order. Z ^-N delay elements 32, 29 and 27
The respective outputs of multipliers 21, 19 and 1
8, the transfer function G _i , ₀ (−Z ^2N ) of equation (15)
and G _Ni , ₁ (−Z ^2N ) are multiplied by the coefficient of the denominator term. In equation (15), the denominator transfer functions of G _i , ₀ (−Z ^2N ) and G _Ni , ₁ (−Z ^2N ) are the same and do not depend on i, so the multiplier 18 in the multiprocessing circuit , 19 and 21 are constant. The outputs of multipliers 18, 19 and 21 are respectively input to adders and subtracters 7, 8 and 9,
A feedback loop is formed.

On the other hand, in equation (15), the transfer function G _i , ₀ (−
Since the numerator coefficient of Z ^2N ) and the numerator coefficient of G _Ni , ₁ (−Z ^2N ) have symmetry with each other, the multiplier can be halved. In FIG. 4, the outputs of Z ^-N delay elements 33, 31, 28 and 26 are input to switches 37, 36, 35 and 34, respectively. The output of the adder/subtracter 9 and the output of the switch 34 are input to the adder/subtracter 11. The output of the switch 37 and the output of the Z ^-N delay element 27 are connected to the adder/subtractor 12.
is input. The output of the Z ^−N delay element 32 and the output of the switch 35 are input to the adder/subtractor 13 . The output of the switch 36 and the output of the Z ^- N delay element 29 are input to the adder/subtractor 14.

Furthermore, adders/subtractors 11, 12, 13 and 14
The respective outputs are input to multipliers 22, 23, 24 and 25, respectively, and transfer functions G _i , ₀ (−Z ^2N )
and GN-i) 1(-Z ^2N ) is multiplied by the numerator coefficient. That is, G _i , ₀ (−Z ^2N ) and G _Ni , ₁
Since the numerator coefficients of (-Z ^2N ) have symmetry with each other, the same multipliers 22, 23, 24 and 2
5. here,
The numerator coefficients of G _i , ₀ (−Z ^2N ) and G _Ni , ₁ (−Z ^2N ) are
Since it depends on i, the multipliers 22, 23, 24
and 25 coefficients need to be changed N times within one frame. Each output of multipliers 25 and 24 is input to adder/subtractor 17. The output of the adder/subtracter 17 and the output of the multiplier 23 are input to the adder/subtracter 16 . The output of the adder/subtractor 16 is input to the delay element 42. Also, the coefficients of multipliers 22, 23, 24 and 25 are the transfer functions shown in equation (18), respectively.
^2l × 2l times the zero-order coefficient of the numerator term of G ₁ , ₀ (Z ^2N )
ai, a third-order coefficient ai+6N, a first-order coefficient ai+2N, and a second-order coefficient ai+4N, each of which changes in a time-division manner N times within one frame.

Here, the zero-order coefficient ai has a smaller absolute value than the first-, second-, and third-order coefficients, so after scaling only ai by 2 ^l , the quantum By doing so, it becomes possible to reduce the required coefficient precision. Instead, as shown in FIG. 4, a 2 ^-l scaler 41 is required which receives the output of the multiplier 22 as an input. Furthermore, multiplier 2
The scaler 41 is configured such that the delay amount from the input of the scaler 41 to the output of the scaler 41 is the same as the delay amount from the input of the multipliers 23, 24, and 25 to the output of the delay element 42 via the adders/subtractors 16 and 17. A delay element 42 is required to compensate for the delay.

The calculation of the numerator term of the transfer function G _i , ₀ (−Z ^2N ) in equation (15) is performed as follows. The output of the adder/subtractor 9 and the outputs of the Z ^-N delay elements 32, 29, and 27 are connected to the adder/subtractor 11, 13, 14, and 1, respectively.
2, multipliers 22, 24, 25 and 23
After being inputted to , it is output to the adder/subtractor 15 . FIG. 5C shows a timing chart of the output of the adder/subtractor 15 at that time, and the numbers correspond to i in the first term on the right side of equation (15).

On the other hand, the calculation of the numerator term of the transfer function G _Ni , ₁ (−Z ^2N ) in equation (15) is performed as follows. The outputs of switches 37, 36, 35 and 34 are input to multipliers 23, 25, 24 and 22 through adders/subtractors 12, 14, 13 and 11, respectively, and then output to adder/subtractor 15. where equation (15)
When i=0, the second term on the right side must be zero, so switches 37, 36, 35, and 34 open when i=0, and i=1, 2, . . .
..., N-1, it operates to close. Fifth
Figure D shows a timing chart of the output of the adder/subtractor 15 at this time, and the numbers correspond to i in the second term on the right side of equation (15).

Therefore, the adder/subtractors 11, 12,
13 and 15, the timing charts C and D in FIG.
Subtraction of terms is performed. Therefore, Ci(Z ^N ) of equation (15) is obtained as the output of the adder/subtractor 15. Fifth
FIG. E shows a timing chart of the output of the adder/subtractor 15, and the numbers correspond to i in C _i (Z ^N ).

The output of the adder/subtractor 15 is input to the array conversion memory 38. In the array conversion memory, (N-1) pieces of data are arrayed for odd (or even) frames. FIG. 5F shows a timing chart of the output of the array conversion memory 38, and the numbers correspond to i in C _i (Z ^N ) of equation (15). Therefore, the output terminal 39 has N C _i (Z ^N ) of equation (15).
are output in a frame configuration arranged in ascending order of i. In addition, in Fig. 4, G _i , ₀ (−Z ^2N ) and
Although a third-order example has been shown with G _Ni , ₁ (-Z ^2N ), a similar configuration can be easily considered even when the order increases.

Furthermore, depending on the characteristics of the designed polyphase digital filter, the number of multipliers that must be scaled to reduce the required coefficient precision may also be 1.
Although there may be cases in which not only one delay element but a plurality of delay elements are required, in this case as well, only one delay element is required to compensate for the delay of the scaler, so the increase in hardware is only the increase in the number of scalers. It should be noted that the structure of the scaler can be easily realized in a serial operation format using two's complement representation by simply inhibiting the flip-flop lock.

As described above, by using the present invention, the amount of multiplication required for a polyphase digital filter is reduced to 1/2 compared to the conventional one, and the coefficient accuracy can also be reduced, making it possible to use a single sideband frequency with small hardware scale. A division multiplex signal demodulator can be provided.

[Brief explanation of drawings]

FIG. 1 shows a block diagram for explaining the functions of the present invention, in which 100 is an input terminal, 20
0 is a demultiplexing circuit, 300(0), 300(1),
300 (2)..., 300 (N-2) and 30
0(N-1) are N outputs of the demultiplexing circuit 200, 400(0), 400(1), 400(2),
...400 (N-2) and 400 (N-1) are N sub-filters, 500 is an offset discrete Fourier processing circuit, 600 is a spectrum inversion circuit,
700 (0), 700 (1), 700 (2), ...,
700 (N-2) and 700 (N-1) are output terminals. FIG. 2 shows a block diagram of one sub-filter, where a is i=1, 2, ..., N-2,
b is a block diagram of a sub-filter used when i=0, 10 and 20 are both input terminals, 30 is a Z ^-N delay element, 40, 41, . . . ...,
49 and 50 are adders and subtracters, 51, 52, ...,
55 and 56 are Z ^-2N delay elements, 60, 61,
62, . . . , 68 and 69 are multipliers, and 70 is an output terminal. FIG. 3 shows a block diagram of an embodiment of the present invention, in which 1 is an input terminal, 2 is a polyphase circuit, 3 is an offset discrete Fourier processing circuit, and 4 is an offset discrete Fourier processing circuit.
is a spectrum inversion circuit, and 5 is an output terminal. FIG. 4 shows a block diagram of the polyphase circuit 2 of FIG. 3, where 1 is an input terminal, 6 is an array conversion memory, 7, 8, 9 and 11, 12, . . .
..., 17 is an adder/subtractor, 18, 19, 21, 22,
..., 25 is a multiplier, 26, ..., 29 and 3
1, ..., 38 are Z ^-N delay elements, 34, 35,
36 and 37 are switches, 38 is an array exchange memory, 39 is an output terminal, 41 is a scaler, and 42 is a delay element. FIG. 5 shows a timing chart of the circuit shown in FIG.

Claims (1)

[Claims] 1 A first array transformation memory that receives a sample value series of an N-channel single sideband frequency division multiplexed signal and performs array transformation of the input data; a polyphase circuit consisting of a digital filter circuit that performs operations on a plurality of digital filters; a second array conversion memory that receives the output signal of the digital filter circuit as input and performs array conversion of time-division multiplexed data; In a single sideband frequency division multiplexed signal demodulator for obtaining an N channel baseband signal from an N channel single sideband frequency division multiplexed signal by digital signal processing using a Fourier processing circuit and a spectrum inversion circuit, the digital filter circuit is a first group of n (positive integer) multipliers, a first group of n cascaded adders/subtractors each receiving the output of the first group of n multipliers, and a group of n first multipliers connected in cascade, and a first delay element with a tap output that receives the output of the first adder/subtractor group connected in cascade; and a 2i-th (i=1, 2, ..., m, m+1) tap of the first delay element. (m+1) switches receiving outputs (m is a positive integer); and (m+1) switches receiving the (m+1) switch outputs and the (2i-1) tap output of the first delay element, respectively. 2 adder/subtractor groups,
(m+1) second multiplier groups each receiving the outputs of the (m+1) second adder/subtractor groups; and j multipliers among the (m+1) second multiplier groups. j scalers each receiving an output,
a first adder that receives the outputs of the remaining (m-j+1) multipliers among the (m+1) second multiplier group; and a first adder that receives the outputs of the first adders and the m scalers that receive the outputs of the first adders. a second delay element for compensating for the delay of the first delay element; and a second adder receiving the output of the second delay element and the output of the j scalers, 2k+1) tap (k=
1, 2, ..., n) outputs respectively to the n first multiplier groups, and n
A constant coefficient is supplied to the first multiplier group to perform multiplication of the denominator coefficients of the plurality of digital filters, and a coefficient that changes in a time-division manner is supplied to each of the (m+1) multiplier groups. 1. A single sideband frequency division multiplex signal demodulation device, characterized in that the digital filter circuit is configured by supplying a plurality of digital filters and multiplying the numerator coefficients of the plurality of digital filters.