JPS63238767A - Binary data compression processor - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution while the high speed of a compression processing is executed by processing an image pattern in parallel. CONSTITUTION:At the time of a compression processing, an image pattern 104 of an encoding scanning line is set to a decoding part 4, every 8 bits are respectively taken out in parallel and sent to a buffer part 3 and a detecting part 2. The detecting part 2 detects a next changing picture element (a1 point) in the processing direction of a starting changing picture element (a0 point) from an image pattern 103 of 8 bits sent as encoding scanning line data and detects a next changing picture element (b1 point) in the processing direction from the a0 point from an image pattern 106 of 16 bits sent from the buffer part 3 as the referring scanning line data. Thus, the detecting part 2 detects a changing picture element while the image pattern 103 of an encoding at every scanning line is successively fetched 8 bits and the image pattern 106 of a referring scanning line is fetched at every 16 bits in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a binary data compression processing device for encoding binary data.

(Prior Art) As a method for compressing and decompressing binary data, the CCI TT (International Telegraph and Telephone Consultative Committee) recommends that coding methods such as the M11 method, MR method, and M2R method be used for facsimile. Recommended, internationally standardized and widely recognized. The Ml+ encoding method is a one-dimensional encoding method that focuses only on the line to be processed.
Compression efficiency is inferior to the R encoding method (two-dimensional encoding method). The M2R encoding method omits the end-of-line (EOL) code of the MR encoding method and uses the K parameter (K
By performing one-dimensional encoding for each line and setting the number of errors (to prevent error propagation) to infinity, the compression efficiency can be increased to MR.
It is higher than the encoding method.

Conventionally, compression/expansion processing of binary data using these methods has generally been performed by sequential software processing using a general-purpose microcomputer.

(Problems to be Solved by the Invention) In such processing, there is no problem in using it as a facsimile machine whose data transmission speed is limited. However, when attempting to use such a method to display image information on a computer system workstation, the operating speed is significantly reduced and a good man-machine interface cannot be achieved. In order to solve such problems, generally widely used methods are parallel processing, proactive processing, and pipeline processing. However, the desired speed has not yet been reached.

SUMMARY OF THE INVENTION An object of the present invention is to provide a binary data compression processing device that can simplify the circuit configuration and speed up compression processing.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, the next change on the processing direction side from the start change pixel (aO point) in the encoding scanning line When detecting pixels (81 points), there is a first register in which the position information of the starting change pixel (aO point) in the encoded scanning line is set, and a second register that holds the image pattern of the encoded scanning line in units of multiple bits. a second register, a signal indicating whether or not to invert the image pattern obtained via the second register, and an inversion circuit for inverting the image pattern obtained via the second register based on the signal; , detecting a change pixel (a 1 point) candidate on the processing direction side from the start change pixel of the image pattern obtained through the inversion circuit, based on the position information of the start change pixel set in the [-]th register. al, - obtained through a gate candidate detection circuit, a third register in which position information of a pixel (terminal point) located one bit on the side of the terminal pixel in the scanning line in the processing direction is set, and the second register. If the image pattern includes a terminal point, a virtual change pixel is placed at the terminal point position of the image pattern obtained via the second register based on the position information of the terminal point set in the third register. a termination processing circuit that supplements candidates, and an a1 inspection that detects a changed pixel candidate closest to a start changed pixel among changed pixel candidates detected by the a1 point candidate detection circuit and changed pixel candidates supplemented by the end processing circuit. Provided is a binary data compression processing device characterized by comprising an output circuit.

Furthermore, in the reference scanning line, the next changing pixel (
b 1 point) During detection, there is a first register in which the position information of the start change pixel (a O point) in the encoded scanning line is set, and a fourth register that holds the image pattern of the reference scanning line in units of multiple bits. a second signal indicating whether or not to invert the image pattern obtained via the fourth register; and inverting the image pattern obtained via the fourth register based on the second signal. and a second inverting circuit that performs the process, based on the position information of the start change pixel set in the first register, the position of the start change pixel of the image pattern obtained through the second inversion circuit on the side in the processing direction. Detecting changed pixel (b1 point) candidatesb
An image pattern obtained through a one-point candidate detection circuit, a third register in which position information of a pixel (terminal point) located one bit on the side of the terminal pixel in the scanning line in the processing direction is set, and the fourth register. includes a termination point, a second termination processing circuit supplements a virtual change pixel candidate at the position of the termination point set in the third register, and the change detected by the b1 point candidate detection circuit. A binary data compression processing device comprising a pixel candidate and a b1 point detection circuit that detects a changed pixel candidate closest to a start changed pixel among changed pixels supplemented by the second termination processing circuit. I will provide a.

(Function) In the device configured as described above, when the next change pixel (81 points) on the encoding scanning line is detected on the processing direction side from the start change pixel (aO point), the first change pixel (81 points) is stored in the first register. The position information of the start change pixel (aO point) is set in the register, and the position information of the end point is set in the third register. Further, the second register holds the image pattern of the encoded scanning line in units of multiple bits. The signal indicating whether or not to invert the image pattern obtained via the second register is the direction of color change of the pixel from point aO to point 81 (white-black,
It is used to unify the black and white) and is sent to the inverting circuit. The inversion circuit inverts the image pattern obtained via the second register based on this signal. The a1 point candidate detection circuit detects change pixel (81 points) candidates on the processing direction side from the start change pixel of the image pattern obtained through the inversion circuit, based on the position information of the start change pixel set in the first register. do. If the image pattern obtained through the second register includes a termination point, the termination processing circuit obtains the termination point through the second register based on the position information of the termination point set in the third register. A virtual change pixel candidate is supplemented at the end point position of the image pattern. The a point detection circuit detects the changed pixel candidate closest to the start changed pixel among the changed pixel candidates detected by the a1 point candidate detection circuit and the changed pixel candidates supplemented by the termination processing circuit.

On the other hand, when detecting the next change pixel (point b1) on the reference scanning line that is on the processing direction side from the start change pixel (point aO),
The position information of the start change pixel (point a) is set in the first register, and the position information of the end point is set in the third register. Further, the fourth register holds the image pattern of the reference scanning line in units of multiple bits. A second signal indicating whether or not to invert the image pattern obtained through the fourth register unifies the direction of color change of pixels (white-black, black-white) from point aO to point b1. and is sent to the second inversion circuit.

The second inversion circuit inverts the image pattern obtained via the fourth register based on this second signal. b
The one-point candidate detection circuit detects a changing pixel (point b1) on the processing direction side from the starting changing pixel of the image pattern obtained via the second inversion circuit, based on the position information of the starting changing pixel set in the first register. Detect candidates. When the image pattern obtained through the fourth register includes a termination point, the second termination processing circuit performs a process based on the position information of the termination point set in the third register.
A virtual change-change pixel candidate is added to the end point position of the image pattern obtained through the fourth register. b1
The point detection circuit detects the changed pixel candidate closest to the start changed pixel among the changed pixel candidates detected by the b1 point candidate detection circuit and the changed pixel candidates captured by the termination processing circuit.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing the overall configuration of the binary data compression/expansion processing device of this embodiment. The binary data compression/decompression processing device is composed of a decoding section 4, a generation section 5, a buffer section 3, a detection section 2, and a control section 1 that controls these, and each is connected via an internal bus 101. . The decoding unit 4 mainly decodes codes during decompression. The decoder 4 includes a register in which an image pattern to be compressed sent via the system bus 102 is set. The generation unit 5 generates an image pattern during decompression and a code during compression. The buffer section 3 holds the data of the scanning line one line before the scanning line to be processed during compression and expansion. The detection unit 2 detects changed pixels.

During the compression process, the image pattern 104 of the encoded scan line
is set in a register (not shown) of the decoder 4. The image pattern 104 set in this register is extracted 8 bits at a time in parallel and sent to the buffer section 3 and the detection section 2. In the buffer section 3, this image pattern 103
is saved as reference scan line data. The detection unit 2 detects the next change pixel (hereinafter referred to as 81 points) on the processing direction side of the starting change pixel (hereinafter referred to as point a) from the 8-bit image pattern 103 sent as encoded scanning line data. At the same time, image patterns 10G to a of IC bits sent from the buffer section 3 as reference scanning line data. The next changed pixel on the processing direction side from the point (hereinafter b1
(referred to as a point). In addition, the detection unit 2 detects the next changed pixel (hereinafter referred to as the 82nd point) located on the processing direction side from the 81st point of the encoded scanning line and the b
The next changed pixel (hereinafter referred to as b2 point) located on the processing direction side from the first point is detected. The detection unit 2 determines the encoding mode (bus mode, vertical mode, horizontal mode) from the position information of each point detected here, and sends the data 107 to the generation unit 5. The generation unit 5 generates a code based on this data 107.

In this manner, the detection unit 2 detects changed pixels while sequentially capturing the image pattern 103 of the encoded scanning line 8 bits at a time and the image pattern 106 of the reference scanning line 16 bits at a time in parallel.

The detection unit 2 will be described in detail below with reference to FIG. 22 is a start register (DSTAToo-02) in which the position information of the first aO point of one line is set as 3-bit data by the control unit 1 at the start of the compression process.
It is. Similarly to the start register 22, the control unit 1 sets the position information of the end point (pixel on the 1-bit processing side from the end pixel of one line) to 3 when starting the compression process.
Stop register (D
STOPOO-02). 26 is a reference line register (RREF) in which the image pattern of the reference scanning line is set as 19-bit data, as shown in FIG. 3(A).
-4-15), and R by the control signal from the control unit 1.
Among REFOO-07, RREPO4-07 is RREP
-4-1 byte by byte and transfer the image pattern 106 from the reference line buffer to RREPO.
Latch as 8-15. Then, the reference line register 26 outputs RREF-4-1t as a 16-bit image pattern 202. 25 is a coding line register (RD) in which the image pattern of the coding scanning line is set as 16-bit data as shown in FIG. 3(B).
Tloo-15), and the control signal i from the control unit 1:
Yol:) RDtlog-15 is RDTloo-07
The newly inputted image pattern 103 is latched as RDTI08-15.

Then, the encoding line register 25 is RDTloo-
07 is output as an 8-bit image pattern 201. 27 is a register (SLAPOO-03) in which the position information of point aO is set as 4-bit data, and 2g is data 203 (RBPAOO-03) from this register 27.
-03) and generates 11-bit data indicating the position of point aO, 29 is this decoder 28
Based on the data 204 from the reference line register 26
This is a mask pattern generation circuit that generates an 11-bit mask pattern (AOLS-3-07) for masking the image pattern on the processing direction side from the aO point in the image patterns 202 and 201 from the encoding line register 25. 30 is an image pattern 202.20 from the reference line register 2G and the encoded line register 25 based on the data 206 from the stop register 21.
At L, an 8-bit mask pattern (IENDPTOO
-07). This decoder 30
The data 207 from 207 becomes a mask pattern (11111111) that normally masks the entire image pattern according to the control signal 20B from the control unit 1, and only when processing the final 8 bits of the encoded scanning line, data other than the terminal point are This becomes a mask pattern that masks the image pattern. A comparator 31 compares the data 203 of the register 27 and the data 206 of the stop register 21, and the result is outputted as data B to the control unit 1.

24 is data 205 from the mask pattern generation circuit 29
Based on the data 207 from the decoder 30 and the data 202 from the reference line register 26, aO
This is a b1 point detection circuit that detects the next changed pixel (point b) located on the processing direction side from the point. The b1 point detection circuit 24 detects the next changed pixel (
b 2 points) is detected. Then, the detection result is output as 4-bit position information (BIDETOO-03). 23, similarly to the b1 point detection circuit 24, based on the data 205 and data 207, the encoded line register 25
In data 201 from a.

This is an a1 point detection circuit that detects the next changed pixel (a1 point) on the processing direction side from the point. The a1 point detection circuit 23 detects the next changed pixel (
a 2 points) is detected. Then, the detection result is output as 3-bit position information (AIDTOO-02).

The position information of the b1 point detected by the b1 point detection circuit 24 is output to the subtracter 32 and the selector 37. This point b1 is increased by +4 due to the register 26. The position information of the 81 points detected by the a point detection circuit is output to the selector 35 and the selector 38.

The selector 35 selects output data from the data from the at point detection circuit 23 and this data +4 in response to a control signal from the control unit 1 and outputs it to the subtracter 32. The subtracter 32 outputs the calculation result as data D to the generation unit 5. The selector 37 has the data 203 of the register 27 and the detection circuit 2
The position information of point b1 from control unit 1 is input to selector 3B.
ioo) is input, and data C from the generation unit 2 is input. The selectors 37 and 36 each select an output based on a control signal from the control section 1 and output it to the adder 33. Adder 33 outputs the calculation result to selector 38. The selector 38 receives the output DBPA from the arithmetic circuit 34.
OO-03, output A01BPOO-0 from adder 33
3. Output AIDTOO-02 from a1 point detection circuit 23
, the output from the start register 22 DSTATOO-0
2 is input, and the output is selected by a control signal from the control section 1. The output is output as data E to the generation section 5 and the decoding section 4. Furthermore, its output is a. It is latched in the register 27 as data 209 (SLAPOO-03) indicating the position information of the point. Based on the output 203 from the register 27, the arithmetic circuit 34 converts the position information of point a to f
Let it be lIax(a□ -8, -4).

As described above, image patterns are sequentially set in the reference line register 26 and the encoded line register 25, and the b point detection circuit 24 and the a1 point detection circuit 23 detect changed pixels in each image pattern. Based on the position information of each point detected by the b1 point detection circuit 24 and the a1 point detection circuit 23,
The calculation is performed and the result is sent to the generation section 5. The generation unit 5 generates a code from this calculation result.

The decoder 28 and mask pattern generation circuit 29 will now be described in detail with reference to FIG.

In FIG. 8(A) and (B), 4-bit data 203 indicating the position information of the a (+ point) set in the register 27 is shown.
(RBPAOO-03) and its data 203
11-bit data 204 is generated in which only the bit position indicated by is set to "0" and the rest are set to "■". Data 203 and 209 corresponding to each bit number -3-07 are shown in FIG. 8(C).

In FIG. 8(C), data 203 (1?13PAO
O-03) and data 209 (SLAPoo-03)
When is “0011”°, the bit number indicates 03. Therefore, when the decoder 28 inputs 0011, it generates data 204 in which bit number 03 is set to 0° and the others are set to 1. Furthermore, the mask pattern generation circuit 2
9 generates mask pattern data 205 (AOLS-3-07) based on the data 204, in which all data on the side of the processing direction from the ao point are set to "1" and the other data are set to "0".

Next, the decoder 30 will be explained in detail with reference to FIG. In FIG. 9(A), the decoder 30 generates 3-bit data 20B (D
STOPOO-02) and control signal 208 from control unit 1
and input the 8-bit mask pattern 207 (EN
DPTOO-07). A control signal 208 is a signal indicating whether or not an end point is included in the image pattern being processed, and is valid only when the end point is included. As shown in FIG. 9(B), the control signal 2
08 is “When data 200 (DSTOPOO-
According to the bit position indicated by 02>, a mask pattern is generated in which only the terminal point is set to 0" and the others are set to 1". Data 20B (
DSTOPOO-02) is shown in FIG. 8(C). 8th
In figure (C), data 20B (DSTOPOO-
02) is “011”, the corresponding bit number is 03
Therefore, mask pattern 207 (ENDPTOO-07) in which bit number 03 is set to “0” and the others are set to “■”
generate. On the other hand, as shown in FIG. 9(C), when the control signal 208 is "0", the data 20B (DSTOPOO
A mask pattern 207 (ENDPTOO-07) is generated in which all bits are set to "1" regardless of the contents of -02).

Hereinafter, the a1 inspection will be made without referring to the block diagram showing the configuration of the a1 point danger detection path 23 shown in FIG. 4 and the detailed circuit diagrams of each block shown in FIGS. 5 to 7 and 10. The output circuit 23 will be explained in detail. In FIG. 4, reference numeral 41 denotes an inverting circuit that inverts 8-bit parallel data 201 (RDTloo-07) sent from the encoding line register 25 in response to a control signal 404 (PBLKP) from the control unit 1. The control unit 1 generates a control signal 404 for unifying the direction of color change of pixels (color-black, black-white) from point aO to point 81.
(FI31, KP) is sent to the inversion circuit 41.

In this embodiment, the direction of color change of pixels is unified to black and white. The control signal 404 becomes "■" when the aO point is white, and becomes "0" when it is black.The inversion circuit 41 controls each bit of the image pattern 201 (RDTloo-07) as shown in FIG. 5(A). EX takes exclusive OR with signal 404
It is composed of a CLLISIVE OR gate circuit. Examples of input/output data are shown in FIGS. 5(B) and 5(C). In FIG. 5(B), when the aO point is white ("0"), the direction of color change of the pixel is from white to black, so the control unit 1 changes the control signal 404 (PBLKP) to "0". Therefore, the image pattern 201 is output as data 401 without being inverted.On the other hand, as shown in FIG. Since it becomes black-white, the control unit 1 outputs the control signal 404 (F
Bl, KP) are set to "1". Therefore, the image pattern 201 is inverted by the inverting circuit 41 and the data 40
1 and 17 are output.

Data 401 in which the direction of color change of the pixels is unified by the inversion circuit 41 is sent to the changed pixel candidate detection circuit 42. The changed pixel candidate detection circuit 42 inputs AOLSOO-07 out of the mask data 205 (AOLS-3-07) from the mask pattern generation circuit 29, and based on this, a. A candidate for a changed pixel (a i point) located in the processing direction from the point is detected. As shown in FIG. 6(A), the changed pixel candidate detection circuit 42 detects each bit of the data 401 and the mask data 205 (
N that is inverted after taking the AND with AOLSOO-07)
It is composed of an AND gate circuit. An example of human output data is shown in FIG. 6(B). If the at1 point is bit number 03, mask data 205 (AOLSOO-07)
sets the bits (04-07) on the processing direction side from the ao point to “1”
The data is set to °° and other values (oo-03) are "0". In other words, the mask data 205 is designed to detect black (1°) pixels on the processing direction side from point aO. In the data 401 from the inversion circuit 41, the black pixel (“1”) on the processing direction side from the ao point has bit number 05.
, OG, 07, the changed pixel candidate detection circuit 42
saves this and sets bit number 05.06.07 to “0”
Data 40 indicating change pixel candidates with binding and others set to “1”
Generate 2.

Data 402 indicating changed pixel candidates is sent to the termination processing circuit 43. Here, if the data 402 includes a termination point, termination processing is performed. Termination processing is a process of supplementing a virtual change pixel candidate to the pixel (termination point) next to the terminal pixel of one line, and this process is performed by CCITT (International Telegraph and Telephone Consultation Committee) MHlMR, M21? This is specified in the encoding rules. The termination processing circuit 43 receives the mask data 207 (ENDPTOO-) from the decoder 30.
07) to supplement virtual change pixel candidates. Figure 7 (A
), the termination processing circuit 43 inputs each bit of the data 402 indicating the changed pixel candidate and the mask data 20 frames (P, N
It is composed of an AND gate circuit that performs a logical product with DPTOO-07). Figure 7 (B) shows an example of human output data.
- Shown in (D). In FIG. 7(B), the termination point is at bit number 03, and bit number 0 of data 402
3 is not detected as a changed pixel candidate, the termination processing circuit 43 generates data 403 in which bit number 03 is supplemented with a virtual changed pixel candidate.

In other words, bit number 08 is added as a changed pixel candidate to bit numbers 05-07 that have already been detected as changed pixel candidates. On the other hand, as shown in FIG. 7(C), the termination point is at bit number 03, and data 402
If bit number 03 has already been detected as a changed pixel candidate, the termination processing circuit 43 outputs the data 402 as is. Further, if there is no termination point, as shown in FIG. 7(D). Mask data 207
Since all bits (00-07) are "■", the termination processing circuit 43 outputs the data 402 as is without compensating for the virtual change pixel candidate. In this way, the termination processing circuit 43 supplements virtual change pixel candidates only when processing the final 8 bits of one line.

Data 408 obtained through the changed pixel candidate detection circuit 42 and the termination processing circuit 43 is sent to the changed pixel detection circuit 44. As shown in FIG. 10(A), the changed pixel detection circuit 4
4 is aO from among the changed pixel candidates shown in the data 403.
Detect the change pixel candidates (81 points) closest to the point, and
The bit number of one point is converted into 3-bit data 210 (AIDT
This is a priority encoder that outputs as OO-02). Data 21 corresponding to each bit number 00-07
0 (A107 port 0-02) is shown in FIG. 8(C). As shown in FIG. 1O (B), in the data 403, aO
The change pixel candidate closest to the point is bit number 03, and "Oll" corresponding to this bit number 03 is set as data 21.
Output as 0 (AIDTOO-02).

As described above, 81 points are detected, and the detection results are sent to the selector 35 and the selector 38 to proceed with the compression process.

Hereinafter, the b1 point detection circuit 24 will be described with reference to the block diagram showing the configuration of the b1 point detection circuit 24 shown in FIG. 11 and the detailed circuit diagrams of each block shown in FIGS. 12 to 15.
I will explain in detail. In FIG. 11, 51 is 18-bit parallel data 20 sent from the reference line register 26.
2 (RREP-4-11> to control signal 5 from control unit 1
This is an inverting circuit that inverts by 04 (FBLKC).

The control unit 1 controls the direction of pixel color change from point aO to point b1 (
Control signal 504 (F
BLKC) is sent to the inversion circuit 51. In this embodiment, the aq point is white ("0") and the b1 point is black ("l"), and the direction of color change is unified from white to black. Control signal 504 (PBLKC)
When the ao point is black, it is "1" and when it is white, it is "0". As shown in FIG. 12(A), the inverting circuit 51 performs the exclusive OR of each bit of the image pattern 202 (RREP-4-11) and the control signal 504 (PBLKC).
It consists of an LLISIVIE OR gate circuit. Examples of human output data are shown in FIGS. 12(B) and 12(C).

In FIG. 12(B), when the ao point is black ("l"), the direction of color change of the pixel is black-white, so the control unit 1 sets the control signal 504 (PBLKC) to "■". Therefore, the image pattern 202 is inverted by the inversion four-way 51 and output as data 501. On the other hand, as shown in FIG. 12(C), when the aO point is white ("0"), the direction of color change of the pixel is from white to black, so the control unit 1 sends the control signal 504 (PBLKC) " o”. Therefore, the image pattern 202 is not inverted and the data 5
Output as 01.

Data 501 in which the direction of color change of the pixels is unified by the inversion circuit 51 is sent to the changed pixel candidate detection circuit 52. The changed pixel candidate detection circuit 52 inputs the mask data 205 (AOLS-3-07) from the mask pattern generation circuit 29, and based on this, detects candidates for changed pixels (point b1) located on the processing direction side from point aO. do. As shown in FIG. 13(A), -3-11 out of data 501 (-4-11)
-4 out of each bit and data 501 (-4-11)
NAND gate circuit that inverts the shift data (-3-11) obtained by inverting each bit of -10 and shifting it one bit at a time to the upper bit number and the mask data 205 (AOLS-3-07) and then inverting it. It consists of

An example of input/output data is shown in FIG. 13(B). Inversion circuit 51
Data 501 from bit number 05. as shown in the figure.
06.09, lO is white (“0”) and the rest are black (°1”
). Also, since the 81st point is bit number 03, in mask data 205 (AOLS-3-07), the bits on the processing direction side from bit number 03 are "1", and the other bits are "0".
Furthermore, each bit of data 501 (-4-1o) is inverted and shifted one bit at a time to the upper bit number, resulting in data with bit numbers 06.07.10.
11 is black (“°1”) and the rest are white (“0”).

When these three data are ANDed and then inverted, bit number 07.11 is detected as a changed pixel candidate, as shown in data 502. In this way, the changed pixel candidate detection circuit 52 detects a changing point in the data 501 that is located on the processing direction side from point aO and changes from white ("0") to black ("1"), and identifies this as a changed pixel candidate. do.

Data 502 indicating changed pixel candidates is sent to the termination processing circuit 53. Here, 0 out of data 502 (-3-11)
If a termination point is included in 〇-07, termination processing is performed. The termination processing circuit 53 compensates for virtual changed pixels based on the mask data 207 (ENDPTOO-07) from the decoder 30. As shown in FIG. 14(A), the termination processing circuit 53 outputs data 502 (-
AN that takes the AND of each bit 00-07 of 3-11) and mask data 207 (ENDPTOO-07)
It consists of D gates. The first example of input/output data is
This is shown in Figure 4 (B).

If the termination point is at bit number 03 and bit number 03 of data 502 is not detected as a changed pixel candidate, the termination processing circuit 53 generates data 503 in which bit number 03 is supplemented with a virtual changed pixel candidate.

Note that 0 of the data 502 (-3-11) being processed
If the end point is not included in 0-07, the decoder 30 outputs data 205 (ENDP
TOO-07), the termination processing circuit 53 does not compensate for virtual changed pixel candidates, and the data 502 is output as is as data 503.

Data 503 obtained via the changed pixel candidate detection circuit 52 and the termination processing circuit 43 is sent to the changed pixel detection circuit 54. As shown in FIG. 15(A), the changed pixel detection circuit 5
4 is a from among the changed pixel candidates shown in the data 503.
Detect the changed pixel candidate (point b1) closest to the point, and
The bit number of one point is converted into 4-bit data 211 (BID[
This is a priority encoder that outputs as ETOO-03). Data 211 (13LDETOO-03) corresponding to each bit number -3-11 is shown in FIG. 8(D). As shown in FIG. 15(B), in the data 503, the change pixel candidate closest to point aO is bit number 07.
10-1" corresponding to this bit number 07 is output as data 211 (BIDETOO-03).

Point b1 is detected as described above, and the detection result is sent to the subtracter 32 and selector 37 to proceed with the compression process.

Hereinafter, with reference to the flowchart shown in FIG.
The operations of point detection and b1 point detection will be explained.

Here, each block surrounded by a dotted line indicates a range in which the a1 point detection circuit 23 and the b1 point detection circuit 24 operate in one step of the microprogram according to instructions from the control section 1 based on the microprogram. Each block surrounded by a solid line represents a group of processing. Processing timing order relationships are established between blocks indicated by dotted lines by a microprogram. On the other hand, within the dotted line blocks are the solid line blocks connected in series [■ The order of processing between tiles is realized by hardware.

First, an 8-bit image pattern is taken into the a1 point detection circuit 23, and a 16-bit image pattern is taken into the b1 point detection circuit 24 (GOI). Then, each circuit detects 81 points and b1 point (Ei02). In this example, the first starting change pixel (point a O) is white (“O”).
), so FBLKC and PBLK
Set P to °°0゛° and do not invert the image pattern. a
As a result of point and b1 point detection, if both are not detected (
803), reset the position of point a to 1nax (ao-8゜〇-4), and set register 2B (RREF
), set the image pattern of register 25 (RDTI) to 8
Shift bit by bit (604) and return to 601. On the other hand, if at least one of point 81 and point b1 is detected (803), the position of the detected point and the positional relationship between point 81 and point b1 are detected (BO2). Based on the result of step 805, the subsequent processing differs as follows.

(1) Point a and point b1 are detected together, and -3≦a l
b When 1≦3: Processed as vertical mode. As a result, the generation unit 5 is instructed to generate a vertical mode code (eoe).

Next, the position of point a is reset to the position of the detected 81 points, and the FBLKC and FBup signals are inverted (set to "0" for °°1" and "1" for °0"). ) (807). Here, if the ao point is located to the right of the end of the line (the position of the virtual change pixel) (608)
, performs line end processing (EOL processing). On the other hand, if the ao point is not at the position of the virtual changed pixel, the process returns to 801 and the next a point and b1 point are detected.

(2) b1 point not detected, a point detected, or 81 points, b
If points are detected together and al-bl≦-4; treated as horizontal mode. As a result, the generation unit 5 is instructed to generate a horizontal mode code (618).

Next, the position of point a is reset to the position of the detected 81 points, and the PBLKC and FBLKP signals are inverted (if "1" is set to "0", if "o" is set to "1")
゛゛〉 (619). Here, if point aO is located to the right of the end of the line (the position of the virtual change pixel) (
620), line end processing (EOL processing) is performed. On the other hand, if the ao point is not at the position of the virtual change pixel, the a1 point detection circuit 23 has an 8-pixel image pattern b1
Each 16-bit image pattern is taken into the point detection circuit 24 (821). 82-bit image patterns are then detected (822). Here (hardware), b
Two-point detection is also performed, but since only 32 points are required, the detection result of point b2 is ignored. Therefore 82
Until a point is detected (623), change the position of point a to m
At the same time, the image patterns of register 2B (RREP) and register 25 (RDTI) are shifted by 8 bits (024). Then, the next image pattern is loaded into the a1 point detection circuit 23 and the b1 point detection circuit 24, respectively ((i21)
, 622 to continue detecting 82 points. When the 82 points are detected (823), the generator 5 is instructed to generate a vertical mode code ((i25). This completes the horizontal mode processing, and the position of the aO point is reset to the position of the detected 32 points. At the same time, the PBLKC and FBLKP signals are inverted (if they are "1", they are set to "0", and if they are "0°," they are set to "1").
) (62B). Then, the process returns to 801 and detects the next 81 points, b1 point.

(3) When point a is not detected and point b1 is detected (b1 detection pending ■ signal - "0"), or when point a and point b1 are both detected and a1bt≧4: Enter pass mode test. Here, b11 detection hold ■ is a signal generated by a b1 detection hold gate (not shown). The processing performed by this b1 detection hold gate is performed in parallel with b1 detection. b The detection hold gate is the image pattern (RREP-4-11
) 16 bits, RREP-3-07 (especially RREP
05-07), it is determined whether or not point b1 exists in RREP-3-04, and whether only point b exists in RREP05-07 (point b2 does not exist). Depending on the result of the determination, the subsequent processing differs as follows.

b The detection pending gate is RREF-3-O with 81 points not detected.
If b1 point does not exist in 4, or RREPO5-0
Point b exists in 7, but point b2 exists in RREFO6-07. If not, enable b11 detection hold■ ("■
”). This b11 detection pending ■ is transmitted to the control unit 1.The 81st point and the b1 point are determined to be undetected, and the 80
Return to step 4 and continue processing. Therefore, RREI'Q5-0
If point b and point b2 exist in 7, there is a possibility that it can be processed as a vertical mode. If 81 points are not detected and b1 and b2 points do not exist in RItEPO5-07, b11 detection suspension ■ is enabled (°0''). This b11 detection suspension ■ is transmitted to the control unit 1. ,6
The process advances to 09 and is processed as a bus mode test.

When entering the pass mode test, the position of point aO is reset to the position of detected point b1, and the signals of FBl, KC are inverted (°°1"-"0", "0"-"1 ”
) (609). Next, the a1 point detection circuit 23 receives an 8-picture image pattern, and the b1 point detection circuit 24 receives a 1-pitch image pattern.
Each 6-bit image pattern is captured (GIO). Then, two points a and b are detected (611). If both points a and b are not detected (612), the position of point aO is set to max(a
o 8, -4) and register 26
(RREI) and shifts the image pattern of register 25 (RDTI) by 8 bits (613). Then, the process returns to 610, and the next image pattern is loaded into the a point detection circuit 23 and the b1 point detection circuit 24, respectively (610).
10). Then, point a and two points b are detected (611
). On the other hand, if at least one of point a and point b2 is detected (Ei12), the position of the detected point and the positional relationship between point 81 and point b2 are detected (614)
. Based on the result of step 814, the process proceeds as follows.

(i) Point a not detected and point b detected, or 81 points,
If points b are detected together and a 1 > b 2:
Treated as bus mode. As a result, the generation unit 5 is instructed to generate a bus mode code (615).

Then, the position of point a is reset to the position of detected point b2, and the FBI and KC signals are inverted ("l
”-”Oo”, “O” →”1”) (61B)
, where a. If the point is located to the right of the end of the line (the position of the virtual changed pixel) (817), line end processing (EOL processing) is performed. On the other hand, if the aO point is not at the position of the virtual changed pixel, the process returns to 601.

(If) If point b is not detected and point a is detected, or if both 81 points and point b are detected and a1≦b2, it is processed as horizontal mode. As a result, the generation unit 5 is instructed to generate a horizontal mode code (827), and the process proceeds to 819.

(4) Point a is not detected and point b is detected (b, detection pending signal -
In the case of "■"): As mentioned above, there is a possibility that it can be processed in the vertical mode, so both points a and b1 are not detected and the process returns to ■604.

As described above, point a detection and point b1 detection are performed in parallel, and the compression process is proceeded based on the results.

As described above, in this embodiment, the image pattern is processed in parallel byte by byte, so that the pixel tlt
Compared to the previous serial processing, the speed has been significantly increased. In addition, the vertical mode code processing has become easier by expanding the target range for b1 point detection by more than 3 bits forward and backward compared to the target range for 31 point detection (8 pins). Also,
By providing an inverting circuit in each of the 81 point and b1 point detection circuits, the same circuit can be used regardless of the direction of color change of the pixel, simplifying the circuit. Also, b
By providing a detection hold gate, when a1 is not detected and b is detected, the position of point b1 can be known in advance, and the compression efficiency can be improved. Furthermore, by providing an end processing circuit in the normal change point detection circuit, a virtual change pixel candidate can be supplemented to the right of the end point of the line, making encoding easier.

[Effects of the Invention] As described above, in the present invention, image patterns are processed in parallel, thereby speeding up compression processing and simplifying the circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of a binary data compression processing device that is an embodiment of the present invention, FIG. 2 is a diagram showing the detailed configuration of the detection unit 2 shown in FIG. 1, and FIG. A) and (B) are diagrams showing in detail the configurations of the register 26 and register 25 shown in FIG. 2, respectively. FIG. 4 is a diagram showing the detailed configuration of the a1 point detection circuit 23 shown in FIG. 5 is a circuit diagram showing an example of the inversion circuit 41 shown in FIG. 4 and an example of input/output data, and FIG. 6 is a diagram showing an example of input/output data of the inversion circuit 41 shown in FIG.
A circuit diagram showing an example of 2 and a diagram showing an example of human output data, 7th
The figure shows a circuit diagram showing an example of the termination processing circuit 43 shown in FIG. 4, and a diagram showing an example of input/output data. FIGS. A diagram showing circuit connections of the pattern generation circuit 29 and an example of input/output data; FIGS. 8(C) and (D) are diagrams showing an example of bit numbers corresponding to data indicating bit positions; FIG. 10 is a diagram showing the circuit connection of the decoder 30 shown in FIG. 2 and an example of input/output data, and FIG. 10 is a diagram showing the circuit connection of the changed pixel detection circuit 44 shown in FIG. 4, and the input/output data example. A diagram showing an example of data, Figure 11 is b1 shown in Figure 2.
FIG. 12 is a diagram showing the configuration of the point detection circuit 24 in detail.
FIG. 13 is a circuit diagram showing an example of the inversion circuit 51 shown in FIG. 1 and an example of input/output data, and FIG. 13 is a circuit diagram showing an example of the changed pixel candidate detection circuit 52 shown in FIG. 11 and an example of human output data. 14 is a circuit diagram showing an example of the termination processing circuit 53 shown in FIG. 11 and an example of human output data, and FIG. 15 is a circuit diagram of the changed pixel detection circuit 54 shown in FIG. 11. A diagram showing connections, a diagram showing an example of input/output data, and FIG. 16 are a flowchart showing an example of the operation of the compression process of this embodiment. 1... Control unit 21... Stop register 22... Start register 25... Encoding line register 2B... Reference line register 27... Register 28... Decoder 41... Inverting circuit ( a 1 point) 42... Changed pixel candidate detection circuit (a 1 point) 43...
- Termination processing circuit (a 1 point) 44... Change pixel detection circuit (a r point) 51... Inversion circuit (b 1 point)

Claims (11)

[Claims] (1) Start change pixel in encoded scanning line (a_0 point)
A first register in which position information is set, and a second register in which the image pattern of the encoded scanning line is held in units of multiple bits.
a register, a signal indicating whether or not to invert the image pattern obtained via the second register, and an inversion circuit that inverts the image pattern obtained via the second register based on the signal; a_1 point candidate for detecting a change pixel (a_1 point) candidate on the processing direction side from the start change pixel of the image pattern obtained via the inversion circuit based on the position information of the start change pixel set in the first register; a detection circuit, a third register in which position information of a pixel (terminal point) located one bit in the processing direction side from the terminal pixel in the scanning line is set;
If the image pattern obtained through the register includes a termination point, the termination point of the image pattern obtained through the second register is determined based on the position information of the termination point set in the third register. A termination processing circuit that supplements a virtual change pixel candidate at the point position, and a change closest to the start change pixel among the change pixel candidates detected by the a_1 point candidate detection circuit and the change pixel candidates supplemented by the termination processing circuit. Detect pixel candidates a_
A binary data compression processing device comprising a one-point detection circuit. (2) The a_1 point candidate detection circuit detects an image pattern on the processing direction side from the start change pixel in the image pattern obtained via the inversion circuit, based on the position information of the start change pixel set in the first register. A circuit that generates a mask pattern for masking the image pattern, and an image that is logically ANDed between this mask pattern and the image pattern obtained through the inversion circuit, and then inverted, indicating a change pixel candidate on the processing direction side from the start change pixel. 2. The binary data compression processing device according to claim 1, further comprising a NAND circuit that generates a pattern. (3) When the image pattern obtained via the second register includes a termination point, the termination processing circuit determines the termination point based on the position information of the termination point set in the third register. generate a mask pattern that masks the image pattern other than the terminal point in the image pattern obtained through the register of 2;
Further, if the image pattern does not include a terminal point, a circuit that generates a mask pattern that masks all the image patterns obtained via the second register, and a circuit that generates a mask pattern and the a_1 point candidate detection circuit. and a circuit for generating an image pattern in which the terminal point position is supplemented with a virtual change pixel candidate by performing a logical product with an image pattern obtained through Data compression processing device. (4) The inverting circuit is comprised of an EXOR circuit that takes an exclusive OR of each bit of the image pattern obtained via the second register and the signal. The binary data compression processing device described above. (5) The binary data compression processing device according to claim 1, wherein the second register holds the image pattern of the encoded scanning line in 1-byte units. (6) Start change pixel in encoded scanning line (a_0 point)
a first register in which position information is set; a fourth register that holds an image pattern of a reference search line in units of multiple bits; and whether or not the image pattern obtained through the fourth register is to be inverted. a second inversion circuit that inverts the image pattern obtained via the fourth register based on the second signal; and a start change pixel set in the first register. a b_1 point candidate detection circuit that detects a change pixel (b_1 point) candidate on the processing direction side from the position of the start change pixel of the image pattern obtained via the second inversion circuit based on position information; If the image pattern obtained through the third register and the fourth register includes position information of a pixel (terminal point) located one bit on the processing direction side from the pixel, the terminal point is included in the image pattern. a second termination processing circuit that supplements a virtual change pixel candidate at the position of the termination point set in the third register;
and a b_1 point detection circuit that detects a changed pixel candidate closest to the start changed pixel among the changed pixel candidates detected by the b_1 point candidate detection circuit and the changed pixels supplemented by the second termination processing circuit. A binary data compression processing device characterized by: (7) The b_1 point candidate detection circuit processes the position of the start change pixel in the image pattern obtained via the second inversion circuit, based on the position information of the start change pixel set in the first register. a circuit that generates a mask pattern for masking the image pattern on the processing direction side; a circuit that generates shift data that inverts the image pattern obtained through the second inversion circuit and shifts it by one bit in the processing direction side; The mask pattern, the shift data, and the image pattern obtained through the second inversion circuit are logically ANDed and then inverted to create an image pattern indicating change pixel candidates on the processing direction side from the position of the start change pixel. 7. The binary data compression processing device according to claim 6, comprising a NAND circuit for generating. (8) When the image pattern obtained via the fourth register includes a termination point, the second termination processing circuit performs the following operations based on the position of the termination point set in the third register: Generate a mask pattern that masks image patterns other than the terminal point in the image pattern obtained via the fourth register, and if the image pattern does not include the terminal point, A circuit that generates a mask pattern that masks all the image patterns obtained through 7. The binary data compression processing apparatus according to claim 6, further comprising a circuit for generating an image pattern with supplemented information. (9) A patent characterized in that the second inversion circuit is comprised of an EXOR circuit that takes an exclusive OR of each bit of the image pattern obtained via the fourth register and the second signal. A binary data compression processing device according to claim 6. (10) The fourth register stores an image of the reference scanning line in bit units expanded by at least 3 bits in the processing direction and in the opposite processing direction of the image pattern of the encoded scanning line set in the second register. 7. The binary data compression processing device according to claim 6, wherein a pattern is retained. (11) A patent characterized in that, after detecting point b_1, the second signal is inverted when detecting the next changed pixel (point b_2) located on the reference scanning line and located on the processing direction side from point b_1. A binary data compression processing device according to claim 6.