JPH06303146A - Encoder and decoder - Google Patents

Abstract

PURPOSE:To execute encoding processing from digital data into a code word and composite processing from code word into the digital data simultaneously. CONSTITUTION:A control circuit 10 controls the arithmetic operation for decoding and encoding by an arithmetic operation circuit 12 according to an operation program fed a ROM 11 and controls the input output of a code word of data buyffers 13,14. The arithmetic operation circuit 12 executes alternately the arithmetic operation of the encoding processing and the arithemetic operation of the decoding procerssing and two registers 13,14 are operated alternately corresponding to the respective arithmetic operation processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding / decoding device for compressing and expanding digital data.

[0002]

2. Description of the Related Art In the transmission of digital data such as a facsimile, the transmitting side encodes the digital data in accordance with a predetermined rule, and the obtained codeword is sent to the receiving side. On the receiving side, the transmitted codeword is decoded by the procedure reverse to that of the encoding process, and the first digital data is reproduced. As a result, the amount of information to be transmitted is greatly reduced, and the transmission time is shortened.

FIG. 3 is a block diagram of an image data (digital data) encoding / decoding device in a facsimile. The control circuit 1 executes the arithmetic processing of the arithmetic circuit 3 according to the operation program supplied from the ROM 2,
Further, it controls input / output of digital data and codewords to / from the arithmetic circuit 3. Internal circuits such as an image reading unit and a reproducing unit are connected to the control circuit 1, and digital data is input from the image reading unit and digital data is output to the image reproducing unit. The data buffer 4 accumulates the code word by a certain number of bits, sends the code word taken in from the control circuit 1 to the transmission line through the modem, and at the same time, takes the code word taken in from the transmission line in a certain bit unit. Supply to.

In the digital data input from the image reading section, the information of white and black for each scanning line read by scanning the original is associated with the data of 0 and 1, and the information of each scanning line is respectively. It is represented by an array of data.
The continuous length of the white information and the black information on the scanning line corresponds to the number of bits (run length) in which the same data continues, and the run length is proved as a terminating code or a make-up code by the arithmetic processing in the arithmetic circuit 3. Is converted into a codeword. The run length of the terminating code is set for each 1 bit from 0 bit to 63 bits, and 8 bits at maximum for white data and 12 bits at maximum for black data are added. The makeup code is set every 64 bits, and the termination code is combined and added to the data having a run length of 64 bits or more. This make-up code has a maximum of 9 bits for white data and a maximum of 1 for black data.
3 bits are added. Therefore, if the run length is less than 64 bits, it is encoded into a code word of 12 bits or less, and even if the run length is 64 bits or more, it is encoded to a code word of 25 bits or less.

On the other hand, codewords (terminating code and make-up code) that are taken into the data buffer 4 from the transmission line and input to the arithmetic circuit 3 are arithmetically processed in codeword units, and the run represented by the codeword is represented. It is decoded into white data or black data having a length. Therefore, white data and black data in which 0 or 1 continues for a predetermined number of bits are continuously obtained, and these data are output from the control circuit 1 to the image reproducing unit.

FIG. 4 is a diagram for explaining the operation of the data buffer 4 in the encoding process, and FIG. 5 is a diagram for explaining the operation of the data buffer 4 in the decoding process. The data buffer 4 is configured with the number of bits (for example, 13 bits) capable of storing the longest codeword, but here,
For simplification, the description will be made with an 8-bit configuration in which the code word is assumed to have a maximum of 8 bits.

First, a case will be described in which 4-bit, 6-bit, and 3-bit code words obtained by the encoding process of the arithmetic circuit 3 are sequentially transmitted. In step 1, when all bits of the data buffer 4 are empty, 4 bits d
When the code words 1 to d4 are output from the control circuit 1, they are fetched from the first bit to the fourth bit of the data buffer 4. In step 2, when the code word of 6 bits d5 to d10 is output, the 4 bits d5 to d8 are temporarily taken from the 5th bit to the 8th bit of the data buffer 4, and the 8 bits d1 to d8 in the data buffer 4 are fetched. Is sent to the transmission line and all the bits are vacant, then the remaining 2 bits d9 and d10 are taken into the first bit and the second bit of the data buffer 4. Here, the data buffer 4
Is configured to send out the code to the transmission line in 8-bit units when the code is fetched in all bits, and when all the bits are satisfied by fetching 4 bits d5 to d8 in step 2, The code of 8 bits d1 to d8 is transmitted to make all bits empty. Therefore, the 2 bits d9 and d10 that could not be captured can be captured in the first bit and the second bit. And step 3
When the code words of 3 bits d11 to d13 are output at, since the data buffer 4 has 3 or more empty bits, they are fetched from the third bit to the fifth bit. As described above, if the number of bits of the input codeword is smaller than the number of empty bits of the data buffer 4, the codeword is taken into the empty bits as it is, and if the number of bits of the codeword is larger, empty first. Only the bits are fetched, the code word of the data buffer 4 is sent out, and all the bits are vacant. Then, the remaining code words are fetched in order from the first bit of the data buffer 4.

Secondly, the code sent from the transmission line is fetched in units of 8 bits, 4 bits, 6 bits and 3 bits.
A case where bit code words are sequentially extracted will be described. First, the code word of 8 bits D1 to D8 is loaded into the data buffer 4, and in step 1, the 4 bits D1 to D8 of them are fetched.
D4 is taken out as the first code word and supplied to the control circuit 1. By the way, regarding the number of bits of each codeword,
It is determined during the arithmetic processing in the arithmetic circuit 3, and the code word is extracted from the data buffer 4 based on this determination. In step 2, the 4 bits D5 to D8 left in the data buffer 4 are first taken out, and all the bits in the data buffer 4 are in an empty state. The data buffer 4 is configured to newly fetch the code after all the bits of the code have been fetched. When the remaining 4 bits D5 to D8 are fetched, the next 8 bits D9 to D1 are fetched.
The code of 6 is newly taken into the data buffer 4 from the transmission line. Therefore, the newly captured 8-bit D
Of the codes 9 to D16, 2 bits D9 and D10 are extracted, and 6 bits D5 to D10 combined with the previously extracted 4 bits D5 to D8 are used as the second code word as the control circuit 1
Is supplied to. Then, in step 3, the data buffer 4
3 bits of the 6-bit code left in D11 to D1
3 is taken out as the third codeword. As mentioned above,
If the number of bits of the code word to be taken out is smaller than the number of bits of the code left in the data buffer 4, the code in the data buffer 4 is taken out as it is, and if the number of bits of the code word to be taken out is first left in the data buffer 4. The code is taken out, and then a part of the code newly taken in is combined to obtain the code word.

[0009]

In the above encoding and decoding apparatus, code words may remain in the data buffer 4 even after the completion of each step, and it is necessary to continuously operate at least in scanning line units. Becomes In that case, the same apparatus cannot perform simultaneous encoding and decoding, and, for example, in a facsimile, an operation of reading a transmission original while receiving image information becomes impossible.

Therefore, an object of the present invention is to provide an encoding / decoding device that enables simultaneous encoding and decoding.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that continuous digital data is encoded and bits corresponding to the data contents are obtained. An arithmetic circuit that obtains a number of codewords and sequentially decodes the codewords for each unit to obtain continuous digital data, and the coded codewords are sequentially fetched from the arithmetic circuit to obtain a fixed number of bits. And a second buffer for sequentially fetching codes successively input from an external circuit, accumulating a certain number of bits, and supplying the same to the arithmetic circuit in units of one codeword, and the above arithmetic operation. A control circuit that determines the number of bits of the codeword and controls the input and output of the codewords of the first and second buffers according to the arithmetic processing operation of the circuit.

[0012]

According to the present invention, by providing the first buffer for encoding processing and the second buffer for decoding processing, even if a code word is left in one buffer, the other buffer is provided in the other buffer. The arithmetic circuit can execute the encoding and decoding processes on the codeword that is captured. Therefore, simultaneous encoding and decoding can be performed using the same device.

[0013]

1 is a block diagram of an encoding and decoding apparatus according to the present invention. The control circuit 10 receives the operation program stored in the ROM 11, executes the arithmetic processing of the arithmetic circuit 12 according to the instruction, and controls the input / output of the code word and the image data (digital data). Similar to the arithmetic circuit 3 shown in FIG. 3, the arithmetic circuit 12 performs arithmetic processing for encoding to obtain a terminating code and makeup code from digital data and for decoding to obtain digital data from those code words. I do. Control circuit 10
, A data buffer 13 for encoding and a data buffer 14 for decoding are connected in parallel. When the encoding process is performed, the control circuit 10 fetches a code word into the data buffer 13, and when decoding, Is configured to capture the codeword from the transmission line into the data buffer 14. In addition, registers 15 and 1 for storing data indicating the number of bits of the code word
6 is connected to the control circuit 10 so as to correspond to the respective data buffers 13 and 14, and these registers 15 and 1
According to the data stored in 6, the sending of the codeword from the data buffer 13 to the transmission line and the fetching of the codeword from the data buffer 14 to the control circuit 10 are controlled.

In this encoding / decoding device, when only one of encoding and decoding is performed, only one of the data buffer 13 for encoding and the data buffer 14 for decoding operates. That is, during the encoding process, the data buffer 13 for the encoding process is used.
Performs the same operation as the step shown in FIG. 4, and during the decoding processing, the data buffer 14 for the decoding processing performs the same operation as the step shown in FIG. Therefore, the control circuit 10 and the arithmetic circuit 12 are respectively subjected to the encoding and decoding processes.
Will repeat the same calculation as in the conventional calculation circuit 1.

FIG. 2 is a diagram for explaining the operation of each of the data buffers 13 and 14 when the encoding process and the decoding process are simultaneously performed. In this case, when the code words sent from the transmission line are fetched to sequentially fetch the 4-bit and 6-bit code words, and at the same time, the 3-bit and 7-bit code words obtained by the encoding process are sent to the transmission line. Will be explained. Each data buffer 13 and 14 has an 8-bit configuration.

First, from the transmission line to the data buffer 1
The code of 8 bits D1 to D8 is fetched into 4, and in step 1, 4 bits D1 to D4 of them are fetched as the first code word and supplied to the control circuit 10. At this time, the control circuit 10 determines how many bits of the 8 bits D1 to D8 fetched in the data buffer 14 constitute the first code word, and gives the number of bits to the register 16.
As a result, the data buffer 14 stops outputting at the time when the code word of that number of bits (4 bits in step 1) is given to the control circuit 10. In step 2, when the code word of 3 bits d1 to d3 is obtained by the arithmetic processing in the arithmetic circuit 12, the code word is fetched from the first bit to the third bit of the data buffer 13. Here, in the register 15,
Data indicating the number of bits of the code word obtained by the arithmetic processing of the arithmetic circuit 12 is input from the control circuit 10, and the bit of the data buffer 13 is instructed to fetch the code word. In step 3, the four bits D5 to D8 left in the data buffer 14 are taken out to obtain the data buffer 1
When all the bits of 4 become empty, the control circuit 10 sends an enable signal for permitting the transmission of the code to the transmitting side, and the code of the next 8 bits D9 to D16 is newly added to the data buffer 14 from the transmission line. It is captured. Then, the 8-bit D9-
2 bits D9 and D10 are extracted from the code of D16,
The 6 bits D5 to D10 combined with the previously fetched 4 bits D5 to D8 are supplied to the control circuit 10 as the second code word. In step 4, 7 bits d from the arithmetic circuit 12
When the code words 4 to d10 are output, first, 5 bits d4 to d8 are fetched from the fourth bit to the eighth bit of the data buffer 13 in the empty state. This 5 bits d4
When .about.d8 is fetched and all the bits of the data buffer 13 are filled, the data buffer 13 sends the fetched code to the transmission line to leave all the bits empty. Then, the remaining 2 bits d9 and d10 are captured in the first bit and the second bit of the data buffer 13. These 2 bits d9 and d10 will be sent to the transmission line together with the code when the remaining 3rd to 8th bits of the data buffer 13 are filled in the subsequent step.

As described above, the encoding process and the decoding process are alternately executed at each step, and in the encoding process, the code output from the control circuit 10 to the empty bit of the data buffer 13 is executed. Words are sequentially fetched, and in the compounding process, the codes fetched from the transmission line into the data buffer 14 are sequentially fetched one by one, and the control circuit 10
Entered in. In these processes, the codeword fetch position in the data buffer 13 and the data buffer 14
The data indicating the extraction position of the code word from is stored in the register 1 provided corresponding to each of the data buffers 13 and 14.
5 and 16 are stored respectively. Therefore, even if different processing is performed in the next step, after two steps, the code word is fetched into the data buffer 13 and the data buffer 14 according to the data in the registers 15 and 16.
It is possible to accurately extract the codeword from.

[0018]

According to the present invention, since the data buffer for the encoding process and the data buffer for the decoding process are separately provided, the encoding process and the decoding process are alternately executed at each step. It Therefore, it becomes possible to simultaneously process the encoding of digital data into a code word and the decoding of a code word into digital data while using a single arithmetic circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an encoding and decoding device according to the present invention.

FIG. 2 is a diagram illustrating an operation of a data buffer at the time of simultaneous encoding and decoding processing.

FIG. 3 is a block diagram showing a configuration of a conventional encoding and decoding device.

FIG. 4 is a diagram illustrating an operation of a data buffer at the time of encoding processing.

FIG. 5 is a diagram illustrating an operation of a data buffer during a decoding process.

[Explanation of symbols]

 1, 10 Control circuit 2, 11 ROM 3, 12 Arithmetic circuit 4, 13, 14 Data buffer 15, 16 register

Claims (2)

[Claims] 1. An arithmetic circuit for encoding continuous digital data to obtain a code word having a bit number corresponding to data content, and for sequentially decoding the code word for each unit to obtain continuous digital data. And a first buffer that sequentially fetches the coded code words from the arithmetic circuit and outputs them at a constant number of bits, and sequentially captures codes that are continuously input from an external circuit and accumulates them at a constant number of bits. Then
The second buffer supplied to the arithmetic circuit in units of one code word and the number of bits of the code word are determined according to the arithmetic processing operation of the arithmetic circuit to input the code words of the first and second buffers. An encoding and decoding device comprising: a control circuit that controls an output. 2. The encoding and decoding apparatus according to claim 1, wherein encoding from digital data to a code word and decoding from code word to digital data are alternately executed step by step.