JPH088645B2 - Image signal encoding / decoding large-scale integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal encoding / decoding large-scale integrated circuit used in a facsimile apparatus or the like, and particularly to MH, MR and M
The present invention relates to a large-scale integrated circuit for picture signal coding / decoding that performs coding and decoding by the MR coding method.

Conventional technology Currently, CC is the encoding method for facsimile.
According to Recommendation T.4 of the ITT (International Telegraph and Telephone Consultative Committee), the MH coding system for the one-dimensional coding system and the MR coding system for the two-dimensional coding system are internationally standardized.

Here, the MH coding method is a method in which a change point of a coded line image signal is detected and an MH code corresponding to the run length and the black and white of the run is used. As shown in FIG. 5 (a), the termination code corresponding to the run length of 0 to 63 and the makeup code for the run length of every 64 runs from 64 to 2560 are shown in FIG. 5 (b). is there. That is, 64 or more runs are encoded by a combination of the makeup code and the subsequent terminating code. The MR coding method detects a change point of a coded line image signal and a change point of a reference line (the line immediately before the coded line) image signal, and sequentially codes the coded lines from their relative positions. It is a method to convert. In this MR coding method, the change points of the coding line and the reference line are defined as follows.

a ₀ : Change point that is the starting point of the coding line At the beginning of the coding line, a ₀ is placed on the virtual white change point immediately before the first pixel of the line. During coding of the code line, the position of a ₀ is defined by the immediately preceding code mode.

a ₁ : The first change point to the right of a ₀ on the coding line a ₂ : The first change point to the right of a ₁ on the coding line b ₁ : The change pixel on the reference line to the right of a ₀ First change point having color opposite to a ₀ b ₂ : First change point to the right of b ₁ on the reference line FIG. 6 shows an example of the positional relationship of the above change points. Also,
FIG. 7 shows the reference numerals corresponding to the mode division according to the relative position of the change points.

 The procedure for determining the mode will be described with reference to FIG.

Procedure 1 (a) When b ₂ exists on the left side of a ₁ , it is detected as a pass mode and is encoded using this mode code word '0001'. After this, the pixel directly below b ₂ becomes the new starting pixel a ₀ .

(A) If the pass mode is not detected, proceed to step 2.

Step 2 (a) Determine the absolute value of the relative distance a ₁ b ₁ .

(A) If | a ₁ b ₁ | ≦ 3, it is detected as a vertical mode and the distance of a ₁ b ₁ is encoded as shown in FIG. After that, the pixel a ₁ becomes the new starting pixel a ₀ . a ₁ b ₁ > 0 indicates that a ₁ is on the right side of b ₁ and is represented by V _R , and a ₁ b ₁ > 0 indicates that a ₁ is on the left side of b ₁ and is represented by V _L.

(C) If | a ₁ b ₂ |> 3, it is detected as horizontal mode,
As shown in FIG. 7, the code '001' is followed by a ₀ a ₁ and
Each one-dimensional encoding of a ₁ a ₂ is performed by M (a ₀ a ₁ ) and M (a ₁ a ₂ ). After this, the pixel a ₂ becomes the new starting pixel a ₀ .

Also, regarding the MMR coding method, the coding algorithm is the same as the MR coding method.

For a conventional MH / MR / MMR encoding / decoding circuit in a facsimile apparatus, a large-scale integrated dedicated hardware circuit (hereinafter referred to as CODEC / LSI) is usually used.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, there is a possibility that an error in circuit design or an error in manufacturing may occur at the time of starting the manufacturing of such a CODEC / LSI, and it is necessary to perform a chip test.

For this reason, a fixed image signal is actually input to the CODEC / LSI.
MH, MR, MMR encoding method A method of extracting each code code and comparing it with a predetermined code code, and vice versa.
MH, MR, MMR encoding method It is possible to input a predetermined code code for each and compare the restored image signal with a predetermined image signal.In this case, the CODEC / LSI chip is good as a whole. ， I had a problem that I could only identify the defect.

The present invention has been made in view of the above problems, and an image signal capable of not only discriminating whether a chip is good or bad during a chip test but also confirming the operation of a predetermined one block of an internal circuit. An object is to provide a large-scale encoding / decoding integrated circuit.

Means for Solving the Problems The problems described above include a system bus interface circuit for inputting and outputting coded data, and an image bus for inputting and outputting a coded line image signal and a reference line image signal at the time of two-dimensional encoding and a restored image signal. An interface circuit, at the time of two-dimensional encoding, inputs the encoded line image signal and the reference line image signal, detects respective change points, and outputs an encoding mode and a change point address of the encoded line image signal,
At the time of one-dimensional encoding, the change point address and color information of the encoded line image signal is output, and at the time of two-dimensional decoding, the address information of the decoding mode and the decoding run length and the reference line image signal are input, and the one-dimensional decoding is performed. Sometimes, a mode determination image restoration circuit that restores an image by inputting color information and decoding run length address information, and the one-dimensional code by inputting the encoding mode and the code run length of the encoding line during two-dimensional encoding At the time of encoding, the color information and the encoding run length of the encoding line are input, the respective code data are output to the system bus interface circuit, the code data is input from the system bus interface circuit, and the mode is set at the time of two-dimensional decoding. The decoding run length is output together with the decoding mode to the judgment image restoration circuit, and the color information is output during one-dimensional decoding. And a table search circuit for outputting a decoding run length, a data memory and an arithmetic unit, and inputs a change point address of the encoded line signal at the time of one-dimensional and two-dimensional encoding to calculate a code run length of the encoded line. And outputs to the table search circuit, inputs the decoding run length at the time of one-dimensional and two-dimensional decoding, calculates the address information of the decoding run length, and outputs the address information to the mode determination image restoration circuit. A sequencer circuit for controlling the sequencer circuit, and by the control of the sequencer circuit, the encoding mode and the code run length are input from the system bus interface circuit to the table search circuit via the data memory to transmit the code data to the system bus interface. Output to the circuit, and the code data is output to the system bus interface. It is achieved by an image signal coding and decoding a large scale integrated circuit and outputs the input from Eisu circuit to the table search circuit and the decoding mode to decode the run length to said system bus interface circuit via said data memory. In addition, the mode determination image decoding circuit inputs the change point address of the coding line and the change point address of the reference line at the time of two-dimensional coding, determines the coding mode, and outputs the table to the table search circuit to perform two-dimensional coding. At the time of decoding, the decoding mode is input from the table search circuit, the address information of the decoding run length is input from the sequencer circuit, a change point address of a reference line is input, and image restoration data is output,
At the time of one-dimensional decoding, the color information is input from the table search circuit, the address information of the decoding run length is input from the sequencer circuit, and image restoration data is output, and the image restoration data is input. An image restoration circuit that restores an image by inputting a coded line image signal and a reference line image signal at the time of two-dimensional coding, and inputs the change point address of the coded line and the change point address of the reference line to the mode determination circuit. At the same time as outputting, the change point address of the coded line is output to the sequencer circuit, the color information and the change point address are output by inputting the coded line image signal at the time of one-dimensional coding, and the time of two-dimensional decoding is referred to. A change point detection circuit that inputs a line image signal and outputs a change point address of the reference line to the mode determination circuit, and a control circuit for the sequencer circuit. The image signal conversion / decoding large size which inputs the image data from the image bus interface circuit to the change point detection circuit and outputs the change point address information of the image data to the system bus interface circuit via the data memory. It may be a large scale integrated circuit. Further, under the control of the sequencer circuit, pattern data is input from the system bus interface circuit to the change point detection circuit via the data memory and change point address information is input from the system bus interface circuit via the data memory. It may be a large-scale integrated circuit for outputting / decoding image signals. Further, there is provided a first-in first-out memory capable of inputting data from the system bus interface circuit and the image bus interface circuit and outputting the data to the change point detection circuit.
Under the control of the sequencer circuit, pattern data is input from the system bus interface circuit to the change point detection circuit via the first-in first-out memory and change point address information is output from the system bus interface circuit via the data memory. It may be an image signal / decoding large-scale integrated circuit.

Operation 1) A coded line image signal and a reference line image signal are input from the outside to the image bus interface circuit during encoding and output to the mode determination image restoration circuit during two-dimensional encoding. In the mode determination image restoration circuit, at the time of two-dimensional encoding, the encoded line image signal and the reference line image signal are input, each change point is detected, the encoding mode is output to the table search circuit, and the encoded line image signal changes. The point address is output to the sequencer circuit, the coded line image signal is input at the time of one-dimensional encoding, the change point address and color information of the coded line image signal are generated, and the change point address is output to the sequencer circuit. The information is output to the table search circuit. The sequencer circuit controls each circuit, inputs the change point address, calculates the code run length of the coding line by the calculator, and outputs the code run length to the table search circuit. The table retrieval circuit inputs the coding mode from the mode determination image restoration circuit and the code run length from the sequencer circuit at the time of two-dimensional encoding, and the color information from the mode determination image restoration circuit to the code run length at the time of one-dimensional encoding. Is input from the sequencer circuit and the code data is output to the system bus interface circuit. The system bus interface circuit outputs this code data to the outside.

2) At the time of decoding Code data is input to the system bus interface circuit from the outside and output to the table search circuit. Based on this code data, the table search circuit searches the decoding mode and the decoding run length at the time of two-dimensional decoding, outputs the decoding mode to the mode determination image restoration circuit, and outputs the decoding run length to the sequencer circuit. At the time of one-dimensional decoding, the color information and the decoded run length are searched, the color information is output to the mode determination image restoration circuit, and the decoded run length is output to the sequencer circuit. The sequencer circuit controls each circuit, inputs the decoding run length, calculates the address information by the calculator, and outputs the address information to the mode determination image restoration circuit. The mode determination image restoration circuit restores an image by inputting a decoding mode and address information and a reference image signal from the image bus interface circuit during two-dimensional decoding, and restores an image based on color information and address information during one-dimensional decoding. It is restored and output to the image bus interface circuit.
The image bus interface circuit outputs the restored image signal to the outside.

3) During table search circuit test Under control of the sequencer circuit, the coding mode and code run length are once input to the data memory of the sequencer circuit from the system bus interface circuit and output to the table search circuit. The table search circuit searches code data based on the coding mode and the code run length and outputs the code data to the system bus interface circuit. In addition, after inputting coded data from the system bus interface circuit to the table search circuit to search for the decoding mode and decoding run length and input to the data memory of the sequencer circuit,
Output to system bus interface circuit. In this way, the table search circuit can be tested.

4) Change point detection circuit test-1 Mode decision image restoration circuit is composed of a mode decision circuit, an image restoration circuit and a change point detection circuit, and a) At the time of coding, the change point detection circuit is coded by the image bus interface circuit Image signal and reference line image signal at the time of two-dimensional encoding, each change point address is output to the mode determination circuit, and the change point address of the encoded line is output to the sequencer circuit. A line image signal is input to generate color information and a change point address, the color information is output to a table search circuit, and the change point address is output to a sequencer circuit. The mode determination circuit inputs the change point address of the coding line and the change point address of the reference line at the time of two-dimensional coding, determines the coding mode, and outputs it to the table search circuit.

(B) The decoding mode determination circuit inputs the decoding mode from the table search circuit, the decoding run length address information from the sequencer circuit, and the change point of the reference line image signal from the change point detection circuit during two-dimensional decoding. Enter the address, and input the color information from the table search circuit during one-dimensional decoding,
Decoding run length address information is input from the sequencer circuit and image restoration data is output to the image restoration circuit. The image restoration circuit inputs the image restoration data and outputs the restored image signal to the image bus interface circuit. The change point detection circuit inputs the reference line image signal from the image bus interface circuit at the time of two-dimensional decoding and outputs the change point address of the reference line to the mode determination circuit.

C) During change point detection circuit test Under the control of the sequencer circuit, the image data is input to the change point detection circuit from the image bus interface circuit and the change point address information of the image data is input to the data memory of the sequencer circuit. Then, the function of the change point detection circuit is tested by outputting the change point address information from the data memory to the system bus interface circuit.

5) Change point detection circuit test-2 Change point detection circuit after inputting pattern data from the system bus interface circuit to the data memory of the sequencer circuit under the control of the sequencer circuit using the circuit configuration of the change point detection circuit test-1. Then, the function of the change point detection circuit is tested by outputting the change point address information to the change point address information, inputting the change point address information into the data memory again, and then outputting it through the system bus interface circuit.

6) Change point detection circuit test-3 In addition to the circuit configuration of change point detection circuit test-1, data can be input from the system bus interface circuit and image bus interface circuit, and a first-in first-out memory that outputs this data to the change point detection circuit is provided. By providing the pattern data, the pattern data is once stored in the first-in first-out memory from the system bus interface circuit and then input to the change point detection circuit under the control of the sequencer circuit. The change point detection circuit outputs change point address information to the data memory of the sequencer circuit based on this pattern data.
The change point detection circuit test function is tested by outputting the change point address information from the data memory through the system bus interface circuit.

Embodiments Hereinafter, first to fourth embodiments of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 shows a schematic structure of a CODEC / LSI according to the first embodiment of the present invention. The configuration is a system bus interface circuit 1 which is connected to an external microcomputer and is capable of inputting / outputting coded data to / from this bus and having a control register, and a coding table from a coding mode and its run length during two-dimensional coding. To output the code data, output the code data from the color information and run length at the time of one-dimensional encoding, search the decoding table from the code data at the time of decoding, and perform the composite mode and its run length at the time of two-dimensional decoding. Is a circuit 2 for outputting color information and run length at the time of one-dimensional decoding. For details thereof, the two-dimensional encoding mode and the run length are input, and at the time of one-dimensional encoding, the color information and the run length are input. To generate a coded address and generate a coded address generation circuit 2a and a coded table ROM based on this coded address. The code table ROM 2b for searching and outputting code data, the coding packing circuit 2c for aligning the number of digits of this code data, the first-in first-out memory 2d for inputting / outputting code data, and the code data from the first-in first-out memory 2d for decoding are input. Parallel
Decoding packing circuit 2e for serial conversion and parallel / serial conversion data input to generate decoding address Decoding address generation circuit 2f and decoding ROM is searched based on the decoding address and decoding is performed at the time of two-dimensional decoding Decoding table RO that outputs the coding mode and decoding run length, and outputs color information and decoding run length during one-dimensional decoding.
A table search circuit 2 including an M2g and a table control circuit 2h for controlling each circuit 2a to 2g, and a CODE having an arithmetic function.
A microprogram type circuit 3 for controlling the entire C-LSI, the details of which are a sequencer address control circuit 3a for determining an address of a sequencer, a microprogram ROM 3b in which an instruction code is stored, and an instruction code of an internal clock 1 A sequencer circuit 3 including an instruction register 3c for holding during a cycle, a RAM 3d connected to the internal data bus 7, an arithmetic unit 3e for performing an operation specified by an instruction code, a reference line image signal and a code at the time of two-dimensional encoding The change point is detected from the encoded line image signal and the mode of MR encoding and MMR encoding method is detected.When the one-dimensional encoding is performed, the color information and the change point are detected from the encoded line image signal and the two-dimensional decoding is performed. Restores the image using the decoding mode and its run-length address information, and the color information and run-length address information when performing one-dimensional decoding. Mode determination image restoration circuit 4, connected to an external memory circuit, and a reference line image signal,
The image bus interface circuit 5 inputs and outputs the encoded line image signal and the restored image signal. The operation of the image signal encoding / decoding large-scale integrated circuit configured as described above will be described below. In the sequencer circuit 3, the instruction code stored in the microprogram ROM 3b is sequentially output by the address indicated by the sequencer address control circuit 3a and held in the instruction register 3c for one cycle of the internal clock. In the sequencer address control circuit 3a, the address is normally incremented every cycle of the internal clock, but an instruction code is input from the instruction register 3c to perform an unconditional jump or a conditional jump. The jump address in this case is also specified by the instruction code. In addition, the sequencer address control circuit 3a
If an address stack memory is provided inside, a subroutine or loop operation can be performed. The arithmetic unit 3e performs an arithmetic operation according to the instruction code and transfers the result to the RAM 3d and each circuit through the internal data bus 7. The RAM 3d is also controlled by the instruction code and inputs / outputs data on the internal data bus 7. The instruction code from the instruction register 3c is output to each circuit through the internal control signal bus 6, and the status signal and the response signal from each circuit are sent through the internal control signal bus 6 to the sequencer circuit 3
Input from and control the whole. Next, the operation of the entire circuit will be described.

At the time of encoding, first, a control register in the system bus interface circuit 1 is set by an external CPU. As a result, the sequencer circuit 3 operates the encoding program and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (only the encoded line image signal in the case of the MH encoding method). The input image signal is transferred to the mode determination image restoration circuit 4, where a change point is detected, the encoding mode is determined at the time of two-dimensional encoding, color information is detected at the time of one-dimensional encoding, and the table is searched. Output to circuit 2. The change point address is output to the sequencer circuit 3, and the sequencer circuit 3 subtracts the change point address by the arithmetic unit 3e to obtain its run length and outputs it to the table search circuit 2. In the table search circuit 2, the coded address generation circuit 2a generates the address. The code data output from the encoding table ROM2b has the same number of bits in the encoding packing circuit 2c and is output from the system bus interface circuit 1 to the outside through the FIFO2d.

At the time of decoding, a control register in the system bus interface circuit 1 is also set from an external CPU, so that the decoding program operates in the sequencer circuit 3.
The code data is input to the FIFO 2d of the table search circuit 2 through the system bus interface circuit 1. This code data is parallel / serial converted by the decoding packing circuit 2e, and the decoding table is generated by the decoding address generation circuit 2f.
Generate an address to search ROM2g. Decryption table R
The OM2g searches the decoding table from the address to determine the decoding mode and its run length at the time of two-dimensional decoding, and the color information and run length at the time of one-dimensional decoding. The decoding mode or color information is output to the mode determination image decoding circuit 4, and the run length is added by the calculator 3e of the sequencer circuit 3, that is, the calculation result image is transferred to the mode determination image restoration circuit 4 as address information. To be done. The mode determination image restoration circuit 4 restores an image from the decoding mode, address information, and reference line image signal at the time of two-dimensional decoding, and color information and address information at the time of one-dimensional decoding. Output to.

When the chip test is performed here, it is naturally possible to actually input the data and compare the encoded and decoded data with the reference data. Further, through the system bus interface circuit 1, the sequencer circuit 3
The intermediate code which is the information of the encoding mode and the run length is input to the RAM 3d therein. In this case, as the control of the sequencer circuit 3, the operations of the image bus interface circuit 5 and the mode determination image restoration circuit 4 are stopped, and the coded address generation circuit 2a in the table search circuit 2 has a RAM 3d in which an intermediate code is input in advance. Enter the data of. After that, the table search circuit 2 performs a normal encoding operation, and the code data is output from the system bus interface circuit 1 to the outside. Further, the code data input from the system bus interface circuit 1 is set to the decoding mode and run length in the table search circuit 2, is output from the decoding table ROM2g, and the sequencer circuit 3 is operated to input this into the RAM3d. Then, the data in the RAM 3d is output to the outside through the system bus interface circuit 1. This allows a functional test of the table search circuit 2.

FIG. 2 shows a schematic structure of a CODEC / LSI according to a second embodiment of the present invention, and the same symbols as those in FIG. 1 indicate the same contents.
Differences from FIG. 1 will be described. In Figure 2 the first
The mode determination image restoration circuit 4 shown in the figure includes a mode determination circuit 4a for detecting a mode of an encoding method, an image restoration circuit 4b for generating a restored image, and a coded run length picture signal and a reference line picture signal at the time of two-dimensional coding. A change point detection circuit 4c that detects the change point and detects the change point and color information from the encoded line image signal at the time of one-dimensional encoding.

 Next, the operation will be described.

At the time of encoding, first, a control register in the system bus interface circuit 1 is set by an external CPU. As a result, the encoding program operates in the sequencer circuit 3 and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (only the encoded line image signal in the case of the MH encoding method). To do. The input image signal is transferred to the change point detection circuit 4c, where the change point is detected and color information is also detected at the time of one-dimensional encoding, and the change point address is used for the mode determination circuit 4a and the sequencer circuit 3
And the color information is output to the table search circuit 2. The mode determination circuit 4a determines the encoding mode and outputs it to the table search circuit 2. In the sequencer circuit 3, the change point address is subtracted by the arithmetic unit 3e to obtain the run length, and the run length is output to the table search circuit 2. The table search circuit 2 searches the coding table from the coding mode and run length information at the time of two-dimensional coding and from the color information and run length information at the time of one-dimensional coding, aligns the bits of the code data, and executes the system bus interface. Output to circuit 1. The code data is output from here.

At the time of decoding, a control register in the system bus interface circuit 1 is also set from an external CPU, so that the decoding program operates in the sequencer circuit 3. Code data is the system bus interface circuit 1
To the table search circuit 2. The table search circuit 2 searches the decoding table from the code data,
The decoding mode and its run length are determined during two-dimensional decoding, and the color information and run length are determined during one-dimensional decoding. The decoding mode and the color information are the mode determination circuit 4a.
And the run length information is output to the sequencer circuit 3. In the sequencer circuit 3, this run length is added by the arithmetic unit 3c, and the address information as the result of this arithmetic is transferred to the mode determination circuit 4a. At the time of two-dimensional decoding, the reference line image signal is input from the image bus interface circuit 5, transferred to the change point detection circuit 4c, the change point of the reference line is detected, and the change point address is obtained. Output to the mode determination circuit 4a. Mode decision circuit
In 4a, the color (black or white) of the restored image signal, the restoration start address and the end address are output from these to the image restoration circuit 4b, and the image restoration circuit 4b sequentially restores the image in accordance with this instruction. The restored image signal is output to the outside through the image bus interface circuit 5.

When the chip test is performed here, naturally, a method of actually inputting data and checking the coded and decoded data output by the CODEC / LSI can be implemented. Further, the image signal input from the image bus interface circuit 5 is sequentially transferred to the change point detection circuit 4c. Here, as the operation of the sequencer circuit 3, the change point information output from the change point detection circuit 4c is stored in the RAM 3d in the sequencer circuit 3. When a certain amount of change point information is stored, this data is transferred from RAM3d to the system bus interface circuit 1
To output to the outside. This allows the function of the change point detection circuit to be tested.

FIG. 3 shows a schematic structure of a CODEC / LSI according to a third embodiment of the present invention, and the same reference numerals as those in FIGS. 1 and 2 indicate the same contents.

The difference between FIG. 2 and FIG. 3 is that the change point detection circuit 4c from the system bus interface 1 via the sequencer circuit 3
The point is that the pattern data can be transferred to.

The operation at the time of encoding and decoding is the same as in the case of FIG. 2, and the test method of the change point detection circuit 4c is different, so this test method will be described.

The pattern data is input to the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1. In order to control the sequencer circuit 3 in this case, instead of inputting the reference line image signal and the encoded line image signal of the image bus interface circuit 5, the data stored in the RAM 3d is input to the change point detection circuit 4c. The change point detection circuit 4c detects a change point of the input image signal and stores the change point information in the RAM 3d in the sequencer circuit 3.
When the change point detection operation for the pattern data previously input to the RAM 3d is completed, the change point information data stored in the RAM 3d is output to the outside through the system bus interface circuit 1. As a result, the function of the change point detection circuit 4c can be tested only from the system bus interface circuit.

FIG. 4 shows a schematic structure of a CODEC / LSI according to a fourth embodiment of the present invention, and the same reference numerals as those in FIGS. 1 to 3 indicate the same contents.

The difference between FIG. 3 and FIG. 4 is that a first-in first-out memory is provided which can input data from the system bus interface circuit 1 and the image bus interface circuit 5 and outputs this data to the change point detection circuit. ,
The operation at the time of decoding is the image bus interface circuit 5
Since only the data is transferred to the change point detection circuit, which is the same as the case of FIG. 3, the description of the operation of the entire circuit is omitted.

When performing a chip test, naturally, a method of actually inputting data and checking the encoded and decoded data output by the CODEC / LSI can be implemented. Further, the pattern data is input to the FIFO memory 4d through the system bus interface circuit 1. In this case, the sequencer circuit 3 is controlled so that the reference line image signal and the encoded line image signal input to the image bus interface circuit 5 are stopped and the image signal is not input from the image bus interface circuit 5 to the FIFO memory 4d. To do. FIFO memory 4d
The pattern data stored in is sequentially input to the change point detection circuit 4c, where the change point of this pattern data is detected,
This change point information is stored in the RAM 3d in the sequencer circuit 3. When the change point detection operation of the pattern data input to the FIFO memory 4d in advance is completed, the change point information data stored in the RAM 3d is output to the outside through the system bus interface circuit 1. If the capacity of the FIFO memory 4d is small, the above operation can be repeated several times. Further, when the pattern data is input to the FIFO memory 4d, it is possible to store the pattern data in the RAM 3d once and then transfer the pattern data to the FIFO memory 4d. As a result, the function of the change point detection circuit 4c can be tested.

According to the present invention, in the image signal coding / decoding large-scale integrated circuit including the system bus interface circuit, the image bus interface circuit, the table search circuit, the mode determination image restoration circuit, and the sequencer circuit, the entire chip is tested. Not only is it possible to perform a single function test of the table search circuit, and it is also possible to perform a single function test of the change point detection circuit that constitutes the mode determination image restoration circuit, which makes it easy to determine the quality of these single functions. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 4 is a block diagram showing a second embodiment of the present invention, FIG. 3 is a block diagram showing a third embodiment of the present invention, FIG. 4 is a block diagram showing a fourth embodiment of the present invention, and FIG. a) shows the terminating code, FIG. 5 (b) shows the make-up code, FIG. 6 shows the positional relationship of the change points in the MR and MMR coding systems, and FIG. 7 shows the two-dimensional code. It is a figure showing. 1 ... System bus interface circuit, 2 ... Table search circuit, 3 ... Sequencer circuit, 3a ... Sequencer address control circuit, 3b ... Micro program ROM, 3
c …… instruction register, 3d …… RAM, 3e …… operation unit, 4 ……
Mode decision image restoration circuit, 4a ... Mode decision circuit, 4b ...
... Image restoration circuit, 4c ... Change point detection circuit, 4d ... FIFO memory, 5 ... Image bus interface circuit, 6 ...
… Internal control signal bus, 7 …… Internal data bus.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hideyuki Shirai, Inventor Hideyuki Shimeguro 2-3-8, Meguro-ku, Tokyo Matsushita Densen Co., Ltd. (72) Inventor Toshiko Nishida 2-3-8 Shimeguro, Meguro-ku, Tokyo Matsushita Electric Transmission Co., Ltd.

Claims (4)

[Claims] 1. A system bus interface circuit for inputting / outputting code data, an image bus interface circuit for inputting / outputting a coded line image signal and a reference line image signal at the time of two-dimensional encoding, and a restored image signal, and a two-dimensional At the time of encoding, the encoded line image signal and the reference line image signal are input, the respective change points are detected, the encoding mode and the change point address of the encoded line image signal are output, and at the time of one-dimensional encoding, the The change point address and color information of the encoded line image signal are output, the address information of the decoding mode and decoding run length and the reference line image signal are input during two-dimensional decoding, and the color information and decoding run are input during one-dimensional decoding. A mode determination image restoration circuit that restores an image by inputting address information of length, and a coding mode and a coding line of the coding mode at the time of two-dimensional coding. No. run length is input, the color information and the coding run length of the coding line are input at the time of one-dimensional coding, and code data is output to the system bus interface circuit, and the code data is output from the system bus interface circuit. A table search circuit that outputs the decoding mode and the decoding run length to the mode determination image restoration circuit at the time of two-dimensional decoding, and outputs color information and decoding run length at the time of one-dimensional decoding, and It has a memory and a computing unit, inputs a change point address of the coded line signal at the time of one-dimensional and two-dimensional coding, calculates a code run length of the coded line, and outputs it to the table search circuit. At the time of two-dimensional decoding, the decoding run length is input and the address information of the decoding run length is calculated. A sequencer circuit for controlling each circuit by outputting the encoded mode and the code run length from the system bus interface circuit via the data memory. Input to the table search circuit to output code data to the system bus interface circuit, and input code data from the system bus interface circuit to the table search circuit to input a decoding mode and a decoding run length to the data memory. A large-scale integrated circuit for image signal encoding / decoding, which is output to the system bus interface circuit via the. 2. The mode decision image restoration circuit inputs a change point address of a coding line and a change point address of a reference line at the time of two-dimensional coding, judges a coding mode and outputs it to the table search circuit. During the two-dimensional decoding, the decoding mode is input from the table search circuit, the address information of the decoding run length is input from the sequencer circuit, the change point address of the reference line is input, and the image restoration data is output. Then, at the time of one-dimensional decoding, the color information is input from the table search circuit, the address information of the decoding run length is input from the sequencer circuit, and image restoration data is output, and the image restoration data is output. An image restoration circuit for inputting and restoring an image, and for inputting a coded line image signal and a reference line image signal during two-dimensional coding The change point address of the input line and the change point address of the reference line are output to the mode determination circuit, and the change point address of the encoded line is output to the sequencer circuit to generate the one-dimensional encoding / encoded line image signal. A change point detection circuit for inputting color information and a change point address, inputting a reference line image signal at the time of two-dimensional decoding, and outputting the change point address of the reference line to the mode determination circuit; Image data is input from the image bus interface circuit to the change point detection circuit under the control of a sequencer circuit, and change point address information of the image data is output to the system bus interface circuit via the data memory. The image signal conversion / decoding large-scale integrated circuit according to claim 1. 3. Under the control of the sequencer circuit, pattern data is input from the system bus interface circuit to the change point detection circuit via the data memory, and change point address information is sent to the system bus via the data memory. The large-scale integrated circuit for image signal decoding / decoding according to claim 2, wherein the large-scale integrated circuit is output from an interface circuit. 4. The system bus interface circuit,
A first-in first-out memory that can input data from the image bus interface circuit and outputs the data to the change point detection circuit is provided, and the pattern data is changed from the system bus interface circuit through the first-in first-out memory under the control of the sequencer circuit. The image signal conversion according to claim 2, wherein the change point address information is input to the point detection circuit and is output from the system bus interface circuit via the data memory.
Decoding large scale integrated circuit.