JPH088646B2 - Image signal encoding / decoding large-scale integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal encoding / decoding large-scale integrated circuit used in a facsimile apparatus or the like, and particularly to MH, MR and M
The present invention relates to a large-scale integrated circuit for picture signal coding / decoding that performs coding and decoding by the MR coding method.

Conventional technology Currently, CC is the encoding method for facsimile.
According to Recommendation T.4 of the ITT (International Telegraph and Telephone Consultative Committee), the MH coding system for the one-dimensional coding system and the MR coding system for the two-dimensional coding system are internationally standardized.

Here, the MH coding method is a method in which a change point of a coded line image signal is detected and an MH code corresponding to the run length and the black and white of the run is used. As shown in FIG. 7 (a), the terminating code corresponding to the run length of 0 to 63 and the makeup code for the run length of every 64 runs from 64 to 2560 are shown in FIG. 7 (b). is there. That is, 64 or more runs are encoded by a combination of the makeup code and the subsequent terminating code. The MR coding method detects a change point of a coded line image signal and a change point of a reference line (the line immediately before the coded line) image signal, and sequentially codes the coded lines from their relative positions. It is a method to convert. In this MR coding method, the change points of the coding line and the reference line are defined as follows.

a ₀ : Change point that is the starting point of the coding line At the beginning of the coding line, a ₀ is placed on the virtual white change point immediately before the first pixel of the line. During coding of the code line, the position of a ₀ is defined by the immediately preceding code mode.

a ₁ : The first change point to the right of a ₀ on the coding line a ₂ : The first change point to the right of a ₁ on the coding line b ₁ : The change pixel on the reference line to the right of a ₀ First change point having color opposite to a ₀ b ₂ : First change point to the right of b ₁ on the reference line FIG. 8 shows an example of the positional relationship of the above change points. Also,
FIG. 9 shows the reference numerals corresponding to the mode division according to the relative position of the change points.

The procedure for determining the mode will be described with reference to FIG.

Procedure 1 (a) When b ₂ exists on the left side of a ₁ , it is detected as a pass mode and is encoded using this mode code word '0001'. After this, the pixel directly below b ₂ becomes the new starting pixel a ₀ .

(A) If the pass mode is not detected, proceed to step 2.

Step 2 (a) Determine the absolute value of the relative distance a ₁ b ₁ .

(A) If | a ₁ b ₁ | ≦ 3, it is detected as a vertical mode and the distance of a ₁ b ₁ is encoded as shown in FIG. After that, the pixel a ₁ becomes the new starting pixel a ₀ . a ₁ b ₁ > 0 indicates that a ₁ is on the right side of b ₁ and is represented by V _R , and a ₁ b ₁ <0 indicates that a ₁ is on the left side of b ₁ and is represented by V _L.

(C) If | a ₁ b ₂ |> 3, it is detected as horizontal mode,
As shown in FIG. 9, the code '001' is followed by a ₀ a ₁ and
Each one-dimensional encoding of a ₁ a ₂ is performed by M (a ₀ a ₁ ) and M (a ₁ a ₂ ). After this, the pixel a ₂ becomes the new starting pixel a ₀ .

Also, regarding the MMR coding method, the coding algorithm is the same as the MR coding method.

For a conventional MH / MR / MMR encoding / decoding circuit in a facsimile apparatus, a large-scale integrated dedicated hardware circuit (hereinafter referred to as CODEC / LSI) is usually used.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, there is a possibility that an error in circuit design or an error in manufacturing may occur at the time of starting the manufacturing of such a CODEC / LSI, and it is necessary to perform a chip test.

For this reason, a fixed image signal is actually input to the CODEC / LSI.
MH, MR, MMR encoding method A method of extracting each code code and comparing it with a predetermined code code, and vice versa.
MH, MR, MMR encoding method It is possible to input a predetermined code code for each and compare the restored image signal with a predetermined image signal.In this case, the CODEC / LSI chip is good as a whole. However, there was a problem of only being able to identify defects.

The present invention has been made in view of the above problems, and an image signal code capable of not only discriminating whether the entire chip is good or defective at the time of a chip test but also confirming the operation of a predetermined block of an internal circuit. An object is to provide a large-scale integrated circuit for decoding and decoding.

Means for Solving the Problems The problems described above include a system bus interface circuit for inputting and outputting code data, an image for inputting and outputting a coded line image signal, a reference line image signal at the time of two-dimensional encoding, and a restored image signal. The bus interface circuit and the change point address of the coded line and the change point address of the reference line during the two-dimensional coding are input and the coding mode is determined and output. During the two-dimensional decoding, the decoding mode and the decoding run are performed. A mode determination circuit for inputting the address information of the length, the change point address of the reference line, the color information and the address information of the decoding run length at the time of one-dimensional decoding, and outputting the image restoration data, and the image. An image restoration circuit for inputting restoration data to restore an image, and a code for inputting a coded line image signal and a reference line image signal during two-dimensional encoding The change point address of the encoded line and the change point address of the reference line are output to the mode determination circuit, the change point address of the encoded line is output, and the encoded line image signal is input during one-dimensional encoding. A change point detection circuit that outputs color information and a change point address, inputs a reference line image signal at the time of two-dimensional decoding, and outputs a change point address of the reference line to the mode determination circuit, and a change point detection circuit at the time of two-dimensional encoding. The encoding mode and the code run length of the encoding line are input, and at the time of one-dimensional encoding, the color information and the code run length of the encoding line are input to output the respective code data to the system bus interface circuit, Input code data from the system bus interface circuit,
A table search circuit that outputs the decoding mode and the decoding run length to the mode determining circuit during two-dimensional decoding and outputs color information and decoding run length during one-dimensional decoding, a data memory, and an arithmetic unit. Having the change point address of the coded line signal at the time of one-dimensional and two-dimensional coding, calculating the code run length of the coded line and outputting it to the table search circuit, and at the time of one-dimensional and two-dimensional decoding A sequencer circuit that inputs a decoding run length, calculates the address information of the decoding run length and outputs the same to the mode determination circuit, and controls each circuit, and by the control of the sequencer circuit,
Pattern data is input from the system bus interface circuit to the change point detection circuit through the data memory, change point address data is output to the mode determination circuit, and coding mode data is output from the mode determination circuit to the data memory. This is achieved by a large-scale integrated circuit for image signal encoding / decoding which outputs to the system bus interface circuit via the. In addition, a first-in first-out memory that can input data from the system bus interface circuit and the image bus interface circuit and outputs the data to the change point detection circuit is provided, and pattern data can be transferred from the system bus interface circuit under the control of the sequencer circuit. Input to the change point detection circuit through the first-in first-out memory to output change point address information to the mode determination circuit, and encoding mode information from the mode determination circuit from the system bus interface circuit via the data memory. Output image signal
It may be a large-scale decoding integrated circuit. Further, under the control of the sequencer circuit, image restoration data information is input from the system bus interface circuit to the image restoration circuit via the data memory and restored image data is restored to the system bus interface circuit via the data memory. It may be a large-scale integrated circuit for image signal encoding / decoding that outputs more. Further, under the control of the sequencer circuit, image signal code for inputting image restoration data information from the system bus interface circuit to the image restoration circuit via the data memory and outputting restored image data from the image bus interface circuit. It may be a large-scale integrated circuit for decoding / decoding. Further, under the control of the sequencer circuit, change point address data is input from the system bus interface circuit to the mode determination circuit via the data memory, and an encoding mode is input from the system bus interface circuit via the data memory. Further, the decoding mode information and the change point address data are input from the system bus interface circuit to the mode determination circuit via the data memory and the restored image data is restored to the system bus interface via the data memory. A large-scale integrated circuit for encoding / decoding image signals output from the circuit may be used. Further, under the control of the sequencer circuit, the change point address data and the decoding mode information are input from the system bus interface circuit to the mode determination circuit via the data memory and the image restoration data is output to the image restoration circuit. The image signal encoding / decoding large-scale integrated circuit may be such that the image restored by the image restoring circuit is output from the system bus interface circuit via the data memory.

Action 1) A coded line image signal and a reference line image signal are externally input to the image bus interface circuit at the time of encoding and output to the change point detection circuit at the time of two-dimensional encoding. The change point detection circuit inputs the coded line image signal from the image bus interface circuit and the reference line image signal at the time of two-dimensional encoding, outputs each change point address to the mode determination circuit, and changes the code line change point address. Is output to the sequencer circuit, and the coded line image signal is input during one-dimensional encoding to generate color information and a change point address, the color information is output to the table search circuit, and the change point address is output to the sequencer circuit. The mode determination circuit inputs the change point address of the coding line and the change point address of the reference line at the time of two-dimensional coding, determines the coding mode, and outputs it to the table search circuit. The sequencer circuit controls each circuit, inputs the change point address, calculates the code run length of the coding line by the calculator, and outputs the code run length to the table search circuit. The table search circuit inputs the coding mode from the mode determination circuit and the code run length from the sequencer circuit at the time of two-dimensional coding, and the color information from the change point detection circuit to the code run length at the sequencer circuit at the time of one-dimensional coding. Input, and code data is output to the system bus interface circuit. The system bus interface circuit outputs this code data to the outside.

2) At the time of decoding Code data is input to the system bus interface circuit from the outside and output to the table search circuit. The table search circuit searches the decoding mode and the decoding run length at the time of two-dimensional decoding based on this code data, outputs the decoding mode to the mode determination circuit, outputs the decoding run length to the sequencer circuit, and performs one-dimensional decoding. At the time of conversion, the color information and the decoded run length are searched, the color information is output to the mode determination circuit, and the decoded run length is output to the sequencer circuit. The sequencer circuit controls each circuit, inputs the decoding run length, calculates the address information by the arithmetic unit, and outputs the address information to the mode determination circuit. The mode determination circuit inputs the decoding mode from the table search circuit during two-dimensional decoding, the decoding run length address information from the sequencer circuit, and the change point address of the reference line image signal from the change point detection circuit. During one-dimensional decoding, color information is input from the table search circuit, decoding run length address information is input from the sequencer circuit, and image restoration data is output to the image restoration circuit. The image restoration circuit inputs the image restoration data and outputs the restored image signal to the image bus interface circuit. The change point detection circuit inputs the reference line image signal from the image bus interface circuit at the time of two-dimensional decoding and outputs the change point address of the reference line to the mode determination circuit. The image bus interface circuit outputs the restored image signal to the outside.

3) Mode judgment circuit, change point detection circuit test-1 Under the control of the sequencer circuit, the pattern data is once input from the system bus interface circuit to the data memory of the sequencer circuit and output to the change point detection circuit.
The change point detection circuit detects the change point and outputs the change point address data to the mode determination circuit. The mode determination circuit determines the coding mode, inputs it to the data memory, and then outputs it to the system bus interface circuit. In this way, the function test of the mode determination circuit and the change point detection circuit can be performed.

4) Mode judgment circuit, change point detection circuit test-2 In addition to the circuit configuration of mode judgment circuit, change point detection circuit test-1, data can be input from the system bus interface circuit and image bus interface circuit, and this data is checked for changes. Since the first-in first-out memory for outputting to the output circuit is provided, the pattern data is once stored in the first-in first-out memory by the control of the sequencer circuit and then input to the change point detection circuit. The change point detection circuit outputs change point address information to the mode determination circuit based on this pattern data, and the mode determination circuit outputs the coding mode to the data memory of the sequencer circuit. The functions of the mode determination circuit and the change point detection circuit are tested by outputting the encoding mode information from the data memory via the system bus interface circuit.

5) Image restoration circuit test-1 Using the circuit configurations of the mode judgment circuit and change point detection circuit test-1, the image restoration data is input from the system bus interface circuit to the data memory of the sequencer circuit and then output to the image restoration circuit. Image data restored by
The function of the image restoration circuit is tested by inputting the restored image data into the data memory again and then outputting it from the system bus interface circuit.

6) Image restoration circuit test-2 Using the circuit configurations of the mode determination circuit and change point detection circuit test-1, the image restoration data is input from the system bus interface circuit to the data memory of the sequencer circuit and then output to the image restoration circuit. Image data restored by
The function of the image restoration circuit is tested by outputting the restored image data from the image bus interface circuit.

7) Mode decision circuit test Using the circuit configuration of the mode decision circuit and change point detection circuit test-1, the change point address data is input from the system bus interface circuit to the data memory of the sequencer circuit and then output to the mode decision circuit. Then, the coding mode is set, and the coding mode is input again to the data memory and then output from the system bus interface circuit. Also, after inputting decoding mode information and change point address data from the system bus interface circuit to the data memory of the sequencer circuit, it is input to the mode determination circuit to generate restored image data, and this image restoration data is stored in the data memory. After inputting again, output from the system bus interface circuit. This tests the function of the mode determination circuit.

8) Input the change point address data and the decoding mode information from the system bus interface circuit to the data memory of the sequencer circuit using the circuit configuration of the mode decision circuit, the image restoration circuit test mode decision circuit, and the change point detection circuit test-1. After that, input to the mode determination circuit to generate image restoration data and output to the image restoration circuit,
The image restored by the image restoration circuit is input again to the data memory and then output from the system bus interface circuit. This tests the functions of the mode determination circuit and the image restoration circuit.

Embodiments Hereinafter, first to sixth embodiments of the present invention will be described with reference to FIGS.

FIG. 1 shows a schematic structure of a CODEC / LSI according to the first embodiment of the present invention. The configuration is a system bus interface circuit 1 which is connected to an external microcomputer and is capable of inputting / outputting coded data to / from this bus and having a control register, and a coding table from a coding mode and its run length during two-dimensional coding. To output the coded data, output the coded data from the color information and run length at the time of one-dimensional encoding, search the decoding table from the coded data at the time of decoding, and decode the decoding mode and its run length at the time of two-dimensional decoding. , And a table search circuit 2 for outputting color information and run length at the time of one-dimensional decoding, and a microprogram circuit 3 for controlling the entire CODEC / LSI having an arithmetic function, the details of which are the address of the sequencer. Sequencer address control circuit 3a that determines the 3b, an instruction register 3c that holds an instruction code for one cycle of the internal clock, a RAM 3d connected to the internal data bus 7, a sequencer circuit 3 including an arithmetic unit 3e that performs an operation instructed by the instruction code, an encoding A mode determination circuit 4a that detects the method, an image restoration circuit 4b that generates a restored image, a change point is detected from the coded line image signal and the reference line image signal, and a change point from the coded line image signal during one-dimensional encoding. Change point detection circuit 4c for detecting color information, connected to an external memory circuit, reference line image signal, encoded line image signal,
It comprises an image bus interface circuit 5 for inputting and outputting the restored image signal. The operation of the image signal encoding / decoding large-scale integrated circuit configured as described above will be described below. In the sequencer circuit 3, the instruction code stored in the microprogram ROM 3b is sequentially output by the address indicated by the sequencer address control circuit 3a and held in the instruction register 3c for one cycle of the internal clock. In the sequencer address control circuit 3a, the address is normally incremented every cycle of the internal clock, but the instruction code is input from the instruction register 3c,
As a result, an unconditional jump or a conditional jump is performed. The jump address in this case is also specified by the instruction code. Further, if a stack memory of addresses is provided in the sequencer address control circuit 3a, a subroutine or a loop operation can be performed. The arithmetic unit 3e performs an arithmetic operation according to the instruction code and transfers the result to the RAM 3d and each circuit through the internal data bus 7. The RAM 3d is also controlled by the instruction code and inputs / outputs data on the internal data bus 7. The instruction code from the instruction register 3c is output to each circuit through the internal control signal bus 6, and the status signal and the response signal from each circuit are input through the internal control signal bus 6 from the sequencer circuit 3 to control the entire circuit. To do. Next, the operation of the entire circuit will be described.

At the time of encoding, first, a control register in the system bus interface circuit 1 is set by an external CPU. As a result, the encoding program operates in the sequencer circuit 3 and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (only the encoded line image signal in the case of the MH encoding method). To do. The input image signal is transferred to the change point detection circuit 4c, where the change point is detected, color information is also detected at the time of one-dimensional encoding, and the change point address is output to the mode determination circuit 4a and the sequencer circuit 3. The mode determination circuit 4a determines the encoding mode and outputs it to the table search circuit 2. In the sequencer circuit 3, the change point address is subtracted by the arithmetic unit 3e to obtain the run length, and the run length is output to the table search circuit 2. The table search circuit 2 searches the coding table from the coding mode and run length information at the time of two-dimensional coding, and the color information and run length information at the time of one-dimensional coding to obtain code data, and performs bit alignment of this code data. And outputs it to the system bus interface circuit 1. The code data is output from here.

At the time of decoding, a control register in the system bus interface circuit 1 is also set from an external CPU, so that the decoding program operates in the sequencer circuit 3. Code data is the system bus interface circuit 1
To the table search circuit 2. The table search circuit 2 searches the decoding table from the code data,
The decoding mode and its run length are determined during two-dimensional encoding, and the color information and run length are determined during one-dimensional decoding. The decoding mode and the color information are the mode determination circuit 4a.
And the run length information is output to the sequencer circuit 3. In the sequencer circuit 3, this run length is added by the arithmetic unit 3c, and the address information as the result of this arithmetic is transferred to the mode determination circuit 4a. At the time of two-dimensional decoding, the reference line image signal is input from the image bus interface circuit 5, transferred to the change point detection circuit 4c, the change point of the reference line is detected, and the change point address is obtained. Output to the mode determination circuit 4a. Mode decision circuit
At 4a, the color (black or white) of the restored image signal, the restoration start address and the end address are output from these to the image restoration circuit 4b, and the image restoration circuit 4b sequentially restores the image according to this instruction. The restored image signal is output to the outside through the image bus interface circuit 5.

When the chip test is performed here, naturally, a method of actually inputting data and checking the coded and decoded data output by the CODEC / LSI can be implemented. Further, the pattern data is input to the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1. In order to control the sequencer circuit 3 in this case, instead of inputting the reference line image signal and the encoded line image signal of the image bus interface circuit 5, the data stored in the RAM 3d is input to the change point detection circuit 4c. The change point detection circuit 4c detects the change point of the input image signal, and the mode determination circuit
Outputs the change point address data to 4a. Mode decision circuit
In 4a, the coding mode is determined by this, and this coding mode data is stored in the RAM 3d in the sequencer circuit 3. When the operation from the change point detection to the coding mode determination for the pattern data input to the RAM 3d in advance is completed, the coding mode information data stored in the RAM 3d is output to the outside through the system bus interface circuit 1. As a result, the mode determination circuit 4a and the change point detection circuit 4c
Function test can be performed from the system bus interface circuit 1.

FIG. 2 shows a schematic structure of a CODEC / LSI according to a second embodiment of the present invention, and the same symbols as those in FIG. 1 indicate the same contents.

The difference between FIG. 1 and FIG. 2 is that a first-in first-out memory for inputting data from the system bus interface circuit 1 and the image bus interface circuit 5 and outputting this data to the change point detection circuit is provided. ,
The operation at the time of decoding is the image bus interface circuit 5
Just transfer the data to the change point detection circuit 4c,
Since this is the same as the case of FIG. 1, the explanation of the operation of the entire circuit is omitted.

When performing a chip test, naturally, a method of actually inputting data and checking the encoded and decoded data output by the CODEC / LSI can be implemented. Further, the pattern data is input to the FIFO memory 4d through the system bus interface circuit 1. In this case, the sequencer circuit 3 is controlled so that the reference line image signal and the encoded line image signal input to the image bus interface circuit 5 are stopped and the image signal is not input from the image bus interface circuit 5 to the FIFO memory 4d. To do. FIFO memory 4d
The pattern data stored in is sequentially input to the change point detection circuit 4c, where the change point of the pattern data is detected and the change point address is output to the mode determination circuit 4a.
The mode determination circuit 4a determines the encoding mode from this,
This data is stored in the RAM 3d in the sequencer circuit 3. When the coding mode determination of the pattern data input to the FIFO memory 4d in advance is completed, the coding mode information data stored in the RAM 3d is output to the outside through the system bus interface circuit 1.

If the capacity of the FIFO memory 4d is small, the above operation can be repeated several times. Further, when the pattern data is input to the FIFO memory 4d, it is possible to store the pattern data in the RAM 3d once and then transfer the pattern data to the FIFO memory 4d. Thereby, the function test of the mode determination circuit 4a and the change point detection circuit 4c can be performed.

FIG. 3 shows a schematic configuration diagram of a CODEC / LSI according to a third embodiment of the present invention, and the same reference numerals as those in FIG. 1 indicate the same contents. The difference between FIG. 1 and FIG. 3 is that data can be input to and output from the internal data bus 7 to the image restoration circuit 4b.

The operation at the time of encoding and decoding is the same as that of FIG. 1 and the test method is different, so the test method will be described. When the chip test is performed here, a method of actually inputting the data and checking the encoded and decoded data output by the LSI can be implemented. Further, through the system bus interface circuit 1, the sequencer circuit 3
The image restoration data information is stored in the RAM 3d therein. In this case, under the control of the sequencer circuit 3, the image restoration data information stored in the RAM 3d instead of the image restoration data information from the mode determination circuit 4a, that is, the start address, the end address and the color information of the restored image are transferred to the image restoration circuit 4b. To enter. The image restoration circuit 4b restores the image according to this instruction, and the restored image data is stored in the RA in the sequencer circuit 3.
Store it in M3d. When the image restoration for the image restoration data information previously input to the RAM 3d is completed, the restored image data stored in the RAM 3d is output to the outside through the system bus interface circuit 1. Thereby, the function of the image restoration circuit 4b can be tested.

FIG. 4 shows a schematic structure of a CODEC / LSI according to a fourth embodiment of the present invention, and the same symbols as those in FIG. 1 indicate the same contents.

The difference between FIG. 1 and FIG. 4 is that data can be input to the image restoration circuit 4b from the internal data bus 7.

The operation at the time of encoding and decoding is the same as the case of FIG. 1, but the test method of the image restoration circuit 4b is different, so this test method will be described.

Here, when a chip test is performed, it is naturally possible to implement a method of actually inputting data and checking the encoded and decoded data output by the LSI. further,
Image restoration data information is stored in the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1.
In this case, under the control of the sequencer circuit 3, instead of the image restoration data information from the mode determination circuit 4a, the image restoration data information stored in the RAM 3d, that is, the start address, end address and color information of the restored image are sent to the image restoration circuit 4b. input. The image restoration circuit 4b restores the image according to this instruction, and outputs the restored image data to the outside through the image bus interface circuit 1. Thereby, the function of the image restoration circuit 4b can be tested.

FIG. 5 shows a schematic structure of a CODEC / LSI according to a fifth embodiment of the present invention, and the same reference numerals as those in FIG. 1 indicate the same contents.

The difference from FIG. 1 is that the internal data bus 7 can input / output data to / from the mode determination circuit 4b, and an example of the detailed configuration of the mode determination circuit 4a at the time of two-dimensional encoding and decoding is shown. Is.

The mode determination circuit 4a at the time of two-dimensional encoding and decoding is an arithmetic unit 4a1 that performs an operation on the reference line image signal change point address and the encoded line image signal change point address, and determines the encoding mode from this operation result. Mode output circuit 4a2
An arithmetic unit 4a3 for obtaining the address of the restored image from the decoding mode and the reference line image signal change point address, and a multiplexer 4a4 for selecting the output of the arithmetic unit 4a3 as the address of the restored image or the output from the sequencer circuit 3. A mode determination control circuit 4a5 for controlling the mode determination circuit 4a in accordance with an instruction from the sequencer circuit 3.

 Next, the operation will be described.

As for the operation during encoding, first, a control register in the system bus interface circuit 1 is set from an external CPU.
As a result, the encoding program operates in the sequencer circuit 3 and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (only the encoded line image signal in the case of the MH encoding method). To do.
The input image signal is transferred to the change point detection circuit 4c, the change point is detected here at the time of two-dimensional encoding, and the change point address is output to the mode determination circuit 4a and the sequencer circuit 3. At the time of one-dimensional encoding, the change point and the color information are detected, and the change point address is output to the sequencer circuit 3 and the color information is output to the table search circuit 2. In the mode decision circuit 4a, the calculator 4a1
The change point addresses of the reference line image signal and the encoded line image signal are input to and the two-dimensional encoding modes (pass mode, vertical mode, horizontal mode) are compared by the mode output circuit 4a2 to the table search circuit 2 Output to. In the sequencer circuit 3, the change point address of the encoded line image signal is subtracted by the arithmetic unit 3e to obtain its run length, which is output to the table search circuit 2. The table search circuit 2 searches the coding table from the coding mode or color information and run length information, obtains the coded data, aligns the bits of the coded data, and outputs the coded data to the system bus interface circuit 1. The code data is output from here.

Similarly, the operation at the time of decoding sets the control register in the system bus interface circuit 1 from the external CPU,
As a result, the decryption program operates in the sequencer circuit 3. The code data is input to the table search circuit 2 through the system bus interface circuit 1. The table search circuit 2 searches the decoding table from the coded data, determines the decoding mode and run length at the time of two-dimensional decoding, and determines the color information and run length at the time of one-dimensional decoding. The decoding mode or color information is output to the mode determination circuit 4a, and the run length information is output to the sequencer circuit 3. In the sequencer circuit 3, this run length is added by the arithmetic unit 3e, and the address information as the result of this arithmetic is transferred to the mode determination circuit 4a. In the two-dimensional decoding mode, the reference line image signal is input from the image bus interface circuit 5, transferred to the change point detection circuit 4c, and the change point of the reference line image signal is detected here. The change point address is output to the arithmetic unit 4a3 in the mode determination circuit 4a. The arithmetic unit 4a3 generates the address of the restored image from the decoding mode and the change point address of the reference line image signal. The multiplexer 4a4 selects the restored image address output from the sequencer circuit 3 in the one-dimensional decoding mode, and selects the restored image address output from the computing unit 4a3 in the two-dimensional decoding mode, and sends it to the image restoration circuit 4b. Output. The image restoration circuit 4b sequentially restores images according to this instruction. The restored image signal is output to the outside through the image bus interface circuit 5.

When the chip test is performed here, naturally, a method of actually inputting data and checking the coded and decoded data output by the CODEC / LSI can be implemented. Further, through the system bus interface circuit 1, change point information data is input to the RAM 3d in the sequencer circuit 3. In this case, under the control of the sequencer circuit 3, the data stored in the RAM 3d is input to the mode determination circuit 4a instead of the output from the change point detection circuit 4c. The mode determination circuit 4a determines the encoding mode from this and stores it in the RAM 3d in the sequencer circuit 3. When the coding mode determination is completed for the change point address data input to the RAM 3d in advance, the coding mode data stored in the RAM 3d is output to the outside through the system bus interface circuit 1. Further, the decoding mode information and the change point address data are input to the RAM 3d in the sequencer circuit through the system bus interface circuit 1. In this case, under the control of the sequencer circuit 3, instead of the decoding mode output from the table search circuit 2, the decoding mode information stored in the RAM 3d is input to the mode determination circuit 4a, and the reference line output from the change point detection circuit 4c. Instead of the picture signal change point address
The change point address stored in the RAM 3d is input to the mode determination unit 4a. The mode determination circuit 4a thereby generates the address of the restored image and stores it in the RAM 3d in the sequencer circuit 3. Thereafter, this data is similarly output to the outside. Thereby, the function of the mode determination circuit 4a can be tested.

FIG. 6 shows a schematic structure of a CODEC / LSI according to a sixth embodiment of the present invention, and the same reference numerals as those in FIGS. 1 and 5 indicate the same contents. The difference from FIG. 5 is that data can be output from the image restoration circuit 4b to the internal data bus 7. Since the operation at the time of encoding and decoding is the same as that of FIG. 5, this explanation is omitted.

When carrying out a chip test, a method of actually inputting data and checking the coded and decoded data output by the CODEC / LSI can be implemented. Further, the change point address data and the decoding mode information are input to the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1. In this case, under the control of the sequencer circuit 3, instead of outputting the reference line image signal change point address from the change point circuit 6, the change point address data stored in the RAM 3d is input to the mode determination circuit 4a, and the table search circuit 2
The decoding mode information stored in the RAM 3d is input to the mode determination circuit 4a instead of the decoding mode output from the. The mode determination circuit 4a thereby generates an address of the restored image and outputs it to the image restoration circuit 4b. The image restoration circuit 4b generates a restored image from this information and stores it in the sequencer circuit 3.
Store in RAM3d. RAM3d when a certain operation is completed
The restored image data stored in is output to the outside through the system bus interface circuit 1. Thereby, the function test of the mode determination circuit 4a and the image restoration circuit 4b can be performed.

According to the present invention, the image signal encoding / decoding large-scale integration including the system bus interface circuit, the image bus interface circuit, the table search circuit, the mode determination circuit, the image restoration circuit, the change point detection circuit, and the sequencer circuit. In the circuit, not only the test of the entire chip, but also the mode judgment circuit, the image restoration circuit, and the change point detection circuit can be tested individually or in combination, and the excellent effect that the quality of the individual or composite function can be easily judged. is there.

[Brief description of drawings]

1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram showing a third embodiment of the present invention. FIG. 7 is a block diagram showing a fourth embodiment of the present invention, FIG. 5 is a block diagram showing a fifth embodiment of the present invention, FIG. 6 is a block diagram showing a sixth embodiment of the present invention, and FIG. a) shows the terminating code, FIG. 7 (b) shows the make-up code, FIG. 8 shows the positional relationship of the change points in the MR and MMR coding systems, and FIG. 9 shows the two-dimensional code. It is a figure showing. 1 ... System bus interface circuit, 2 ... Table search circuit, 3 ... Sequencer circuit, 3a ... Sequencer address control circuit, 3b ... Micro program ROM, 3
c …… instruction register, 3d …… RAM, 3e …… operation unit, 4a ……
Mode judgment circuit, 4a1, 4a3 ...... Calculator, 4a2 ...... Mode output circuit, 4a4 ...... MPX, 4a5 ...... Mode judgment control circuit, 4b
...... Image restoration circuit, 4c ...... Change point detection circuit, 4d ...... FIFO
Memory, 5 ... Image bus interface circuit, 6
...... Internal control signal bus, 7 ... Internal data bus.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hideyuki Shirai, Inventor Hideyuki Shimeguro 2-3-8, Meguro-ku, Tokyo Matsushita Densen Co., Ltd. (72) Inventor Toshiko Nishida 2-3-8 Shimeguro, Meguro-ku, Tokyo Matsushita Electric Transmission Co., Ltd.

Claims (6)

[Claims] 1. A system bus interface circuit for inputting / outputting code data, an image bus interface circuit for inputting / outputting a coded line image signal, a reference line image signal at the time of two-dimensional encoding, and a restored image signal. Inputs the change point address of the coding line and the change point address of the reference line during dimensional coding, determines the coding mode and outputs it, and inputs the decoding mode and decoding run length address information during two-dimensional decoding. Then, the change point address of the reference line is input, the color information and the address information of the decoding run length are input during the one-dimensional decoding, the mode determination circuit that outputs the image restoration data, and the image restoration data are input. An image restoration circuit for restoring an image, and a change point address of the encoded line by inputting a coded line image signal and a reference line image signal at the time of two-dimensional encoding The change point address of the reference line is output to the mode determination circuit, the change point address of the encoded line is output, and the coded line image signal is input during the one-dimensional encoding to obtain the color information and the change point address. A change point detection circuit that outputs a reference line image signal during two-dimensional decoding and outputs a change point address of the reference line to the mode determination circuit; and the encoding mode and encoding line during two-dimensional encoding. Of the code run length, the color information and the code run length of the coding line are input at the time of one-dimensional coding, and the code data is output to the system bus interface circuit, and the code data is output from the system bus interface circuit. Enter
A table search circuit that outputs the decoding mode and the decoding run length to the mode determining circuit during two-dimensional decoding and outputs color information and decoding run length during one-dimensional decoding, a data memory, and an arithmetic unit. Having the change point address of the coded line signal at the time of one-dimensional and two-dimensional coding, calculating the code run length of the coded line and outputting it to the table search circuit, and at the time of one-dimensional and two-dimensional decoding A sequencer circuit that inputs a decoding run length, calculates the address information of the decoding run length and outputs the same to the mode determination circuit, and controls each circuit, and by the control of the sequencer circuit,
Pattern data is input from the system bus interface circuit to the change point detection circuit through the data memory, change point address data is output to the mode determination circuit, and coding mode data is output from the mode determination circuit to the data memory. A large-scale integrated circuit for image signal encoding / decoding, which is output to the system bus interface circuit via the. 2. The system bus interface circuit,
A first-in first-out memory that can input data from the image bus interface circuit and outputs the data to the change point detection circuit is provided, and the pattern data is changed from the system bus interface circuit through the first-in first-out memory under the control of the sequencer circuit. The point detection circuit is input to output change point address information to the mode determination circuit, and the mode determination circuit outputs encoding mode information from the system bus interface circuit via the data memory. Item 1
Large-scale integrated circuit for image / decoding described. 3. The system controller controls the sequencer circuit to input image restoration data information from the system bus interface circuit to the image restoration circuit via the data memory and restore image data to the system via the data memory. The large-scale integrated circuit for image signal encoding / decoding according to claim 1, wherein the large-scale integrated circuit outputs the signal from a bus interface circuit. 4. Under the control of the sequencer circuit, image restoration data information is input from the system bus interface circuit to the image restoration circuit via the data memory and restored image data is output from the image bus interface circuit. A large-scale integrated circuit for encoding / decoding image signals according to claim 1. 5. Under the control of the sequencer circuit, the change point address data is input from the system bus interface circuit to the mode determination circuit via the data memory, and the encoding mode is set to the system bus via the data memory. Output from the interface circuit,
Decoding mode information and change point address data are input from the system bus interface circuit to the mode determination circuit via the data memory, and restored image data is output from the system bus interface circuit via the data memory. The image signal encoding / decoding large-scale integrated circuit according to claim 1. 6. Under the control of the sequencer circuit, the change point address data and the decoding mode information are input from the system bus interface circuit to the mode determination circuit via the data memory to store the image restoration data in the image restoration circuit. The image signal encoding / decoding large-scale integrated circuit according to claim 1, wherein the image output / output to the image restoring circuit is output from the system bus interface circuit via the data memory.