JPH0244966A - Large scale integrated circuit for coding and decoding picture signal - Google Patents

Abstract

PURPOSE:To prevent generation of mistake on the circuit design and on manufacture at the start of manufacturing by not only discriminating defective chips at chip test but also confirming the operation as to a prescribed block of an internal circuit. CONSTITUTION:The circuit consists of a system path interface circuit 1, an image path interface circuit 5, a table retrieval circuit 2, a mode discrimination picture decoding circuit 4 and a sequencer circuit 3. Then not only the test of the entire chip but also a single function test of the table retrieval circuit 2 is conducted and a single function test for a change point detection circuit 4c forming the mode discrimination picture decoding circuit 4 is executed. Thus, the propriety of the single function is facilitated to strengthen the chip test.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a large-scale integrated circuit for encoding and decoding image signals used in facsimile machines, etc., and particularly for encoding and decoding using MH, MR, and MMR encoding systems. This invention relates to large-scale integrated circuits for image signal encoding and decoding.

Conventional technology Currently, the encoding method for facsimile is CC.
According to Recommendations T and 4 of the International Telegraph and Telephone Consultative Committee (ITT), the MH encoding method for one-dimensional encoding and the MR encoding method for two-dimensional encoding have been internationally standardized.

Here, the MH encoding method is a method that detects a change point in an encoded line image signal and uses a Mu code corresponding to the run length and whether the run is black or white. Terminating codes corresponding to run lengths from 0 to 63 as shown in FIG. 5(a) and FIG. 5(b)
As shown in , there are make-up codes for run lengths every 64 runs from 64 to 2560. That is,
Runs of 64 or more are encoded by a combination of a make-amp code followed by a terminating code. In addition, the MR encoding method is based on the change point of the encoded line image signal and the reference line (the line immediately before the encoded line) 7.
This is a method in which the change points of the \-2 image signal are detected and the coding lines are sequentially coded from the relative positions. In this MR encoding method, the changing points of the encoded line and the reference line are defined as follows.

ao: Change point that is the starting point of the encoded line At the beginning of the encoded line, ao is placed on the virtual white change point immediately before the first pixel of the line. a during encoding of the code line.

The position of is defined by the previous code mode.

al: a on the encoded line. First change point to the right C2: First change point to the right of al on the encoding line b+: Among change pixels on the reference line, a to the right of aQ. The first change point b2 with the opposite color is on the reference line, and the first change point to the right of Figure 6 shows an example of the positional relationship of the above-mentioned change points.

Moreover, FIG. 7 shows the mode classification according to the relative position of the change point and the corresponding code.

The procedure for determining the mode will be explained using FIG.

Step 1 (7) When b2 exists on the left side of al, it is detected as a pass mode, and encoded using this mode code word '0001'. After this, the pixel directly below b2 becomes the new starting pixel a. becomes.

(b) If the pass mode is not detected, proceed to step 2.

Step 2 (7) Determine the absolute values of relative distances a and b.

(b) If la, b, l≦3, it is detected as a vertical mode and the distances of a, b are encoded as shown in FIG. After that, pixel a1 becomes the new starting pixel a. becomes.

at b, > O indicates that al is on the right side of , and is represented by VR, and a, bl < O indicates that al is on the left side of , and ■. Expressed as

(1) 1a, b2 If 1>3, it is detected as a horizontal mode, and as shown in FIG. 7, the code '001' is followed by a. A, and a, C2 are each subjected to one-dimensional encoding M (aQ al ) + M (al C2). This rear surface 9 ・＼−・ element a2 is the new starting pixel a. Totoru.

Further, regarding the MMR encoding method, the encoding algorithm is the same as the MR encoding method.

A large-scale integrated dedicated hardware circuit (hereinafter referred to as CODEC-LSI) is usually used in the MH-MR/MMR encoding/decoding circuit in a conventional facsimile machine.

Problems to be Solved by the Invention However, when starting up production of such a CODEC-LSI, there is a possibility that errors in circuit design or manufacturing may occur, and it is necessary to perform a chip test.

For this reason, there is a method of actually inputting a constant image signal to CODEC-LSI, extracting the code codes of each of the MH, MR, and MMR encoding systems, and comparing them with a predetermined code, or conversely, CODEC-LSIKMH.

A possible method is to input a predetermined code for each of the MR and MMR encoding systems and compare the restored image signal with the predetermined image signal, but in this case, the C0DEC-LSI
There was a problem in that it was only possible to distinguish between good and bad chips as a whole.

10... The present invention was made in view of the above-mentioned problems, and it is possible not only to distinguish between good and bad chips as a whole during chip testing, but also to check the operation of a predetermined block of internal circuitry. The purpose of this invention is to provide a large-scale integrated circuit that can encode and decode image signals.

Means for Solving the Problem The above problem involves a system path interface circuit that inputs and outputs encoded data, and an image path that inputs and outputs an encoded line image signal, a reference line image signal during two-dimensional encoding, and a restored image signal. an interface circuit, at the time of two-dimensional encoding, inputs the encoded line image signal and the reference line image signal, detects respective change points, and outputs an encoding mode and a change point address of the encoded line image signal; During dimensional encoding, the change point address and color information of the encoded line image signal are output, during two-dimensional decoding, address information of the decoding mode and decoding run length, and reference line image signal are input, and during one-dimensional decoding, A mode determination image restoration circuit inputs address information of color information and decoding run length to restore an image, and inputs the encoding mode and code run length of the encoding line during two-dimensional encoding, At the time of encoding, the color information and the encoded run length of the encoded line are input, and the code data is outputted to the system bus interface circuit, the code data is input from the system bus interface circuit, and the code data is inputted at the time of two-dimensional decoding. It includes a table search circuit that outputs the decoding mode and decoded run length to the mode judgment image restoration circuit, and outputs color information and decoded run length during one-dimensional decoding, a data memory, and an arithmetic unit. During two-dimensional encoding, the change point address of the encoded line signal is input, the code run length of the encoded line is calculated and output to the table search circuit, and the decoded run length is input during one-dimensional and two-dimensional decoding. The address information of the decoded run length is calculated and outputted to the mode determination image restoration circuit, and the system bus is The encoding mode and code run length are input from the interface circuit to the table search circuit via the data memory, and the code cheater is output to the system bus interface circuit, and the code data is input from the system bus interface circuit to the table search circuit. This is accomplished by a large-scale integrated circuit for image signal encoding and decoding, which inputs the decoding mode and decoding run length to the system bus interface circuit through the data memory. The mode determination image restoration circuit inputs the change point address of the encoded line and the change point address of the reference line during two-dimensional encoding, determines the encoding mode, outputs it to the table search circuit, and At the time of decoding, the deunification mode is inputted from the table search circuit, the address information of the decoded run length is inputted from the sequencer circuit, and the changing point address of the reference line is inputted to output image restoration data. , a mode determination circuit that inputs the color information manually from the table search circuit during one-dimensional decoding, inputs the address information of the 13-decoding run length from the 7-kenza circuit, and outputs image restoration data; An image restoration circuit inputs restoration data to restore an image, and inputs an encoded line image signal and a reference line image signal during two-dimensional encoding, and calculates a change point address of the encoded line and a change point address of the reference line. At the same time as outputting to the mode determination circuit, the changing point address of the encoded line is outputted to the sequencer circuit, inputting the encoded line image signal during one-dimensional encoding, outputting color information and changing point address, and outputting the changing point address of the encoded line. On a change point detection circuit which inputs a reference line image signal during dimension decoding and outputs a change point address of the reference line to the mode determination circuit, an image is output from the image bus interface circuit under the control of the sequencer circuit. The image signal conversion/decoding large-scale integrated circuit may input data to the change point detection circuit and output change point address information of the image data to the system bus interface circuit via the data memory. Further, under the control of the sequencer circuit, pattern data is input from the system bus interface circuit to the change point detection circuit via the data memory, and change point address information is sent to the system bus interface circuit via the data memory. It is also possible to use a large-scale integrated circuit for converting and decoding image signals into output signals.

Further, a first-in, first-out memory is provided that inputs data from the system bus interface circuit and the image bus interface circuit and outputs the data to the change point detection circuit, and under the control of the sequencer circuit, pattern data is input from the system bus interface circuit. It may be a dual signal conversion/decoding large-scale integrated circuit that inputs change point address information to the change point detection circuit via the first-in first-out memory and outputs change point address information from the system bus interface circuit via the data memory.

Effect 1) During encoding, an encoded line image signal is externally input to the image bus interface circuit, and during two-dimensional encoding, a reference line image signal is inputted to the image bus interface circuit and output to the mode determination image restoration circuit. During two-dimensional encoding, the mode determination image restoration circuit inputs the encoded line image signal and the reference line image signal, detects the change points of each, and outputs the encoding mode to the table search circuit, as well as changes in the encoded line image signal. Output the point address to the sequencer circuit, input the encoded line image signal during one-dimensional encoding, generate the change point address and color information of the encoded line image signal, output the change point address to the sequencer circuit, and input the encoded line image signal to generate the change point address and color information. Outputs information to the table search circuit. The sequencer circuit controls each circuit, inputs the change point address, calculates the code run length of the coded line using the arithmetic unit, and outputs the result to the table search circuit. During two-dimensional encoding, the table search circuit inputs the encoding mode from the mode judgment image restoration circuit and the code run length from the sequencer circuit, and during one-dimensional coding, inputs the color information from the mode judgment image restoration circuit and inputs the code run length. is input from the sequencer circuit, and each encoded data is output to the system bus interface circuit. The system bus interface circuit outputs this code data to the outside.

2) During decoding, code data is externally input to the system bus interface circuit and output to the table search circuit. Based on this code data, the table search circuit searches for the decoding mode and decoding run length during two-dimensional decoding, outputs the decoding mode to the mode judgment image restoration circuit, outputs the decoding run length to the sequencer circuit, During one-dimensional decoding, color information and decoded run length are searched, and the color information is output to a mode determination image restoration circuit, and the decoded run length is output to a sequencer circuit. The sequencer circuit controls each circuit, inputs the decoded run length, calculates address information using an arithmetic unit, and outputs the address information to the mode determination image restoration circuit. The mode determination image restoration circuit restores an image by inputting the decoding mode, address information, and reference image signal from the image bus interface circuit during two-dimensional decoding, and restores the image from color information and address color information during one-dimensional decoding. 17
...-7 is restored and output to the image bus interface circuit. The image bus interface circuit outputs the restored image signal to the outside.

3) When testing the table search circuit Under the control of the sequencer circuit, the encoding mode and code run length are input from the system bus interface circuit into the data memory of the sequencer circuit, and then output to the table search circuit. The full search circuit searches for code data based on the coding mode and code run length and outputs it to the system bus interface circuit. Also, after inputting the code data to the system bus interface circuit and the pf-full search circuit to search for the decoding mode and decoding run length and inputting it to the data memory of the sequencer circuit,
Output to system bus interface circuit. In this way, the table search circuit can be tested.

4) Change point detection circuit test-1 The mode judgment image restoration circuit is composed of a mode judgment circuit, an image restoration circuit, and a change point detection circuit. When performing in-picture signal and two-dimensional encoding, a reference line image signal is input, and each change point address is output to the mode determination circuit, and the change point address of the encoded line is output to the sequencer circuit, and during one-dimensional encoding, the code The color information and change point address are generated by inputting the converted line image signal, the color information is output to the table search circuit, and the change point address is output to the sequencer circuit. During two-dimensional encoding, the mode determination circuit inputs the change point address of the encoded line and the change point address of the reference line, determines the encoding mode, and outputs the result to the table search circuit.

(7) During two-dimensional decoding, the decoding mode determination circuit inputs the decoding mode from the table search circuit, inputs the decoding run length address information from the sequencer circuit, and detects changes in the reference line image signal from the change point detection circuit. Point addresses are input, color information is input from the pull search circuit during one-dimensional decoding, address information of the decoding run length is input from the sequencer circuit, and image restoration data is output to the image restoration circuit.

The image restoration circuit inputs the image restoration data and outputs the restored image signal to the image bus interface circuit. During two-dimensional decoding, the change point detection circuit inputs the reference line image signal from the image bus interface circuit and outputs the change point address of the reference line to the mode determination circuit.

c) When testing the changing point detection circuit Under the control of the sequencer circuit, image data is input from the image bus interface circuit to the changing point detecting circuit, and changing point address information of the image data is input to the data memory of the sequencer circuit.

The function of the change point detection circuit is tested by outputting this change point address information from the data memory to the system bus interface circuit.

5) Change point detection circuit test-2 Using the circuit configuration of change point detection circuit test-1, check the change after inputting pattern data from the system bus interface circuit to the data memory of the 7-controller circuit under the control of the sequencer circuit. The function of the change point detection circuit is tested by outputting it to the output circuit as changing point address information, putting this changing point address information back into the data memory, and outputting it via the system bus interface circuit.

6) Change point detection circuit test-3 In addition to the circuit configuration of change point detection circuit test-1, a first-in, first-out memory that can input data from the system bus interface circuit and image bus interface circuit and outputs this data to the change point detection circuit is used. With this provision, pattern data is once input from the system bus interface circuit into the first-in first-out memory and then input to the change point detection circuit under the control of the sequencer circuit. The change point detection circuit outputs change point address information to the data memory of the sequencer circuit based on this pattern data. The function of the change point detection circuit is tested by outputting change point address information from the data memory via the system bus interface circuit.

EXAMPLES Below, the first to fourth examples of the present invention are shown in FIGS. 1 to 4! 7 Explain.

FIG. 1 shows a CODEC LSI according to the first embodiment of the present invention.
This figure shows the schematic configuration of the . Its configuration consists of a system bus interface circuit (1) connected to an external microcomputer, capable of inputting/outputting code data to/from this bus, and equipped with a control register; When performing one-dimensional encoding, the code data is output based on color information and run length. During decoding, the decoding table is searched from the code data, and when two-dimensional decoding is performed, the decoding mode and its run length are output. The circuit 2 outputs color information and run length during one-dimensional decoding, and its details include inputting the encoding mode and run length during two-dimensional encoding, and inputting color information and run length during one-dimensional encoding. An encoded address generation circuit 2a that inputs a length and generates an encoded address, an encoded table ROM 2b that searches the encoded table ROM based on this encoded address and outputs encoded data, and aligns the number of digits of this encoded data. A first-in, first-out memory 2d inputs and outputs encoded data to and from the encoding banking circuit 2c, and a decoding banking circuit 2e inputs encoded data from the decoding dead first-in first-out memory 2d and converts it from parallel to serial, and inputs the parallel-to-serial converted data. The decoding address generation circuit 2f generates a decoding address, searches the decoding ROM based on the decoding address, and outputs the decoding mode and decoding run length during two-dimensional decoding, and color information and color information during one-dimensional decoding. A table search circuit 2 consisting of a decoding table ROM 2g that outputs a decoding run length and a table control circuit 2h that controls each circuit 2a to 2g, and a C0DE having an arithmetic function.
This is a microprogram type circuit 3 that controls the entire C-LSI, and its details include a sequencer address control circuit 3as instruction code that determines the address of the sequencer.
-7 microprogram ROM 3b1 storing the instruction code for one cycle of the internal clock, an instruction register 3c, and a RAM 3 connected to the internal data bus 7;
d, arithmetic unit 3 that performs the operation specified by the instruction code;
A sequencer circuit 3 consisting of e detects a change point from a reference line image signal and an encoded line image signal during two-dimensional encoding, detects the mode of MR encoding and MMR encoding method, and detects the mode of MR encoding and MMR encoding method during one-dimensional encoding. Color information and change points are detected from the encoded line image signal, and the image is processed using the decoding mode and its run length address information during two-dimensional decoding, and color information and run length address information during one-dimensional decoding. A mode determination image restoration circuit 4 is connected to an external memory circuit, and receives a reference line image signal, an encoded line image signal,
It consists of an image bus interface circuit 5 that inputs and outputs restored image signals. The operation of the image signal encoding/decoding large-scale integrated circuit configured as described above will be described below. In the sequencer circuit 3, the instruction code stored in the microprogram ROMab is sequentially output according to the address indicated by the sequencer address control circuit 3a, and is held in the instruction register 3c for one cycle of the internal clock. Sequencer address control circuit 3a
Normally, the address is incremented every cycle of the internal clock, but an instruction code is input from the instruction register 3C, thereby performing an unconditional jump or a conditional jump. The jump address in this case is also specified by the instruction code. Furthermore, if an address stack memory is provided in the controller address control circuit 3a, subroutines and loop operations can be performed. The arithmetic unit 3e performs arithmetic operations based on the instruction code, and sends the results via the internal data bus 7 to R.
Transfer to AM3d and each circuit. The RAM 3d is also controlled by instruction codes and inputs and outputs data on the internal data bus 7.

The instruction code from the instruction register 3C is output to each circuit through the internal control signal bus 6, and the status signal and response signal from each circuit are input from the sequencer circuit 3 through the internal control signal bus 6 to control the entire system. conduct. Next, the operation of the entire circuit will be explained 5.

At the time of encoding, first, the control register in the system bus interface circuit 1 is set from the external CPU. As a result, the encoding program operates in the controller circuit 3, and the reference line image signal is sent to the image bus interface circuit 5.
A request is made to input the encoded line image signal (in the case of the MH encoding method, only the encoded line image signal). The input image signal is transferred to the mode determination image restoration circuit 4, where it detects changing points, determines the encoding mode during two-dimensional encoding, and detects color information during one-dimensional encoding and searches this in a table. Output to circuit 2. Further, the change point address is output to the sequencer circuit 3, and in the sequencer circuit 3, the change point address is subtracted by the arithmetic unit 3e to obtain its run length and output to the table search circuit 2. In the table search circuit 2, the encoded address generation circuit 2a generates the address. The coded data outputted from the coding table ROM 2b is aligned in the number of pits by the coding banking circuit 2C and outputted to the outside from the system bus interface circuit 1 through the FIFO 2d.

At the time of decoding, the control register in the system bus interface circuit 1 is also set from the external CPU, and the decoding program is operated in the controller circuit 3 from this. The code data passes through the system bus interface circuit 1 and is input to the FIFOs 2 and d of the table search circuit 2. This encoded data is processed in parallel by the decoding banking circuit 2e.
The data is serially converted, and the decoded address generation circuit 2f generates an address for searching the decoded table ROM 2g.

The decoding table ROM 2g searches the decoding table from the address to determine the decoding mode and its run length during two-dimensional decoding, and determines the color information and run length during one-dimensional decoding. The decoding mode or color information is output to the mode determination image restoration circuit 4, and the run length is added by the arithmetic unit 3e of the sequencer circuit 3. In other words, this operation result image becomes address information and is transferred to the mode determination image restoration circuit 4. be done. Mode judgment image restoration episode 27 ・
.

In path 4, an image is restored from the decoding mode, address information, and reference line image signal during two-dimensional decoding, and from color information and address information during one-dimensional decoding, and is output to the outside through the image bus interface circuit 5.

When performing a chip test here, it is of course possible to actually input data and compare the encoded and decoded data with reference data.

Sarani, through the system bus interface circuit 1,
An intermediate code, which is information on the encoding mode and run length, is input to the RAM 3d in the sequencer circuit 3. In this case, as a control of the sequencer circuit 3, the operations of the image bus interface circuit 5 and the moto judgment image restoration circuit 4 are stopped, and the coded address generation circuit 2a in the table search circuit 2 is stored in the RAM 3 to which an intermediate code has been input in advance. Input the data of d. Thereafter, the table search circuit 2 performs a normal encoding operation and outputs the encoded data from the system bus interface circuit 1 to the outside. Further, the code data input from the system bus interface circuit 1 is decoded into a run length by the table search circuit 2, outputted from the decoding table ROM 2g, and the sequencer circuit 3 is operated so as to input it to the RAM 3d. and,
The data in the RAM 3d is output to the outside through the system bus interface circuit 1. This allows a functional test of the table search circuit 20.

FIG. 2 shows a COD E C L according to a second embodiment of the present invention.
The schematic structure of SI is shown, and the same reference numerals as in FIG. 1 indicate the same contents. The differences from FIG. 1 will be explained. Second
In the figure, the mode determination image restoration circuit 4 of FIG. Detects changing points from the image signal,
During one-dimensional encoding, it is composed of a change point detection circuit 4c that detects change points and color information from the encoded line image signal.

Next, the operation will be explained.

When encoding, first the system bus 29 is sent from the external CPU.
\-Set the control registers in the interface circuit 1.

As a result, the encoding program operates in the sequencer circuit 3, and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (in the case of the MH encoding method, only the encoded line image signal). do. The input image signal is transferred to the change point detection circuit 4C, which detects the change point and also detects color information during one-dimensional encoding.The change point address is output to the mode determination circuit 4a and the sequencer circuit 3, and the color information is output to the mode determination circuit 4a and sequencer circuit 3. The information is output to the table search circuit 2. The mode determination circuit 4a determines the encoding mode and outputs it to the table search circuit 2. In the sequencer circuit 3, the change point address is subtracted by the arithmetic unit 3e to obtain the run length, and this is output to the table search circuit 2. The table search circuit 2 searches the encoding table from the encoding mode and run length information during two-dimensional encoding, and from the color information and run length information during one-dimensional encoding, and performs bit alignment of the encoded data. Output to circuit 1. Code data is output from here to the outside.

At the time of decoding, the control register in the system bus interface circuit 1 is also set from the external CPU, and the decoding program is thereby operated in the sequencer circuit 3. The code data is input to the table search circuit 2 through the system bus interface circuit 1. The table search circuit 2 searches a decoding table based on code data, determines the decoding mode and its run length during two-dimensional decoding, and determines color information and run length during one-dimensional decoding. The decoding mode and color information are determined by the mode determination circuit 4a.
The run length information is output to the sequencer circuit 3. In the sequencer circuit 3, the run lengths are added by the arithmetic unit 3C, and address information, which is the result of this arithmetic operation, is transferred to the mode determination circuit 4a. Also, during two-dimensional decoding, a reference line image signal is input from the image bus interface circuit 5, and this is transferred to the change point detection circuit 4C, where the change point of the reference line is detected and the change point address is It is output to the mode determination circuit 4a. The mode determination circuit 4a outputs the color of the restored image signal (white instead of black), restoration start address, and end address to the image restoration circuit 4b, and the image restoration circuit 4b sequentially restores images according to these instructions. The restored image signal is output to the outside through the image bus interface circuit 5.

When performing a chip test here, it is naturally possible to implement a method of actually inputting data and checking the encoded and decoded data output by the CODEC-LSI. Furthermore, the image signal inputted from the image bus interface circuit 5 is sequentially transferred to the change point detection circuit 4c. Here, as the operation of the sequencer circuit 3, the change point detection circuit 4
The change point information output from c is sent to the RA in the sequencer circuit 3.
Store it in M3d. Once a certain amount of change point information has been stored, this data is output from the RAM 3d to the outside through the system bus interface circuit 1. This allows the function of the change point detection circuit to be tested.

FIG. 3 shows a CODEC LSI according to a third embodiment of the present invention.
The same reference numerals as in FIGS. 1 and 2 indicate the same contents.

The difference between FIG. 2 and FIG. 3 is that pattern data can be transferred from the system bus interface 1 to the change point detection circuit 4c via the sequencer circuit 3.

The operations during encoding and decoding are the same as in the case of FIG. 2, but the test method for the change point detection circuit 4c is different, so this test method will be explained.

The pattern data is input to the RAM 3d in the sequencer circuit 3 through the system bus interface I[1.

In this case, the sequencer circuit 3 is controlled by inputting data stored in the RAM 3a to the change point detection circuit 4c instead of inputting the reference line image signal and encoded line image signal to the image bus interface circuit 5. The changing point detection circuit 4c detects changing points of the input image signal, and stores this changing point information in the RAM 3d in the sequencer circuit 3. When the change point detection operation for pattern 33/turn data input in advance to RAM3d is completed,
The change point information data stored in the RAM 3d is output to the outside through the system bus interface M]. Thereby, the function of the change point detection circuit 4c can be tested only from the stem bus interface circuit.

FIG. 4 shows a C0DEC LSI according to the fourth embodiment of the present invention.
The same reference numerals as in FIGS. 1 to 3 indicate the same contents.

The difference between FIG. 3 and FIG. 4 is that a first-in, first-out memory is provided that can input data from the system bus interface circuit and the image bus interface circuit 5 and output this data to the change point detection circuit. , the operation at the time of decoding is simply to transfer the data from the image bus interface circuit 5 to the change point detection circuit.
Since this is the same as the case shown in the figure, a description of the operation of the entire circuit will be omitted.

When performing a timing test, it is natural to implement a method of actually inputting data and checking the encoded and decoded data output by the CODEC-LSI. Furthermore, through the system bus interface circuit 1, the FIF
Input pattern data into O memory 4d. In this case, the control of the sequencer circuit 3 is to stop inputting the reference line image signal and encoded line image signal to the image bus interface circuit 5, and to prevent input of image signals from the image bus interface circuit 5 to the FIFO memory 4d. do. The pattern data stored in the FIFO memory 4d is sequentially input to the change point detection circuit 4c, where the change points of this pattern data are detected, and this change point information is stored in the RAM 3d in the sequencer circuit 3. FIF in advance
When the change point detection operation of the pattern data input to the O memo 'J4d is completed, the change point information data stored in the RAM 3d is outputted to the outside through the system bus interface circuit 1. If the capacity of the FIFO memory 4d is small, it is possible to repeat the above operation several times. Further, when inputting pattern data to the FIFO memory 4d, it is also possible to store the pattern data in the RAM 3d for -1 time and then transfer it to the FIFO memory 4d. This makes it possible to test the function of the change point detection circuit 4c.

Effects of the Invention According to the present invention, a system bus interface circuit,
In a large-scale integrated circuit for image signal encoding/decoding consisting of an image bus interface circuit, a table search circuit, a mode determination image restoration circuit, and a sequencer circuit, it is possible to test not only the entire chip but also the individual function test of the table search circuit. Further, it is possible to carry out an independent function test of the change point detection circuit constituting the mode determination image restoration circuit, and there is an excellent effect that it is possible to easily judge whether the independent function is good or bad.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the first embodiment of the present invention;
FIG. 3 is a block diagram showing a second embodiment of the invention, FIG. 3 is a block diagram showing a third embodiment of the invention, FIG. 4 is a block diagram showing a fourth embodiment of the invention, and FIG. a) shows a terminating code, FIG. 5(b) shows a make-up code, FIG. 6 shows the positional relationship of changing points in MR and MMR encoding systems, and FIG. 7 shows a two-dimensional code. FIG. ■...System bus interface L2...
・Table search circuit, 3...Sequencer circuit, 3a...
Sequencer address control circuit, 3b...microphrogram ROM, 3c...instruction register, 3d...RAM
, 3e... Arithmetic unit, 4... Mode determination image restoration circuit,
4a...Mode determination circuit, 4b - Image restoration circuit, 4
c... Change point detection circuit, 4d... FIFO memory, 5.
...Image bus interface circuit, 6. Internal control signal bus, 7. Internal data bus.

Claims (1)

[Claims] 1. A system bus interface circuit that inputs and outputs encoded data, and an image bus interface circuit that inputs and outputs encoded line image signals, reference line image signals during two-dimensional encoding, and restored image signals. During two-dimensional encoding, the encoded line image signal and the reference line image signal are input, the respective change points are detected, the encoding mode and the change point address of the encoded line image signal are outputted, and the one-dimensional code is When decoding, the change point address and color information of the encoded line image signal are output, when two-dimensional decoding, address information of the decoding mode and decoding run length, and reference line image signal are input, and when one-dimensional decoding, color information is output. and a mode determination image restoration circuit that restores an image by inputting the address information of the decoding run length and the decoding run length, and inputting the encoding mode and the code run length of the encoding line during two-dimensional encoding, and The color information and the encoded run length of the encoded line are input, and each code data is output to the system bus interface circuit, and the code data is input from the system bus interface circuit, and the mode determination image is restored during two-dimensional decoding. It has a table search circuit that outputs the decoding mode and the decoded run length to the circuit, and outputs the color information and the decoded run length during one-dimensional decoding, a data memory, and an arithmetic unit, and is capable of one-dimensional and two-dimensional encoding. When inputting the change point address of the encoded line signal, the code run length of the encoded line is calculated and outputted to the table search circuit, and during one-dimensional and two-dimensional decoding, the decoded run length is inputted and the code run length of the encoded line is calculated. a sequencer circuit that calculates and outputs the address information to the mode determination image restoration circuit and controls each of the circuits; and under the control of the sequencer circuit, the encoding mode and code run are determined from the system bus interface circuit. The length is input to the table search circuit via the data memory and the code data is output to the system bus interface circuit, and the code data is input from the system bus interface circuit to the table search circuit to enter the decoding mode. A large-scale integrated circuit for encoding and decoding image signals, characterized in that a decoded run length is output to the system bus interface circuit via the data memory. 2. The mode determination image restoration circuit inputs the change point address of the encoded line and the change point address of the reference line during two-dimensional encoding, determines the encoding mode, and outputs it to the table search circuit, At the time of decoding, the decoding mode is input from the table search circuit, the address information of the decoding run length is input from the sequencer circuit, the changing point address of the reference line is input, and image restoration data is output. a mode determination circuit that inputs the color information from the table search circuit during original decoding, inputs the address information of the decoded run length from the sequencer circuit, and outputs image restoration data; An image restoration circuit that restores an image, inputs an encoded line image signal and a reference line image signal during two-dimensional encoding, and outputs a change point address of the encoded line and a change point address of the reference line to the mode determination circuit. At the same time,
It outputs the change point address of the encoded line to the sequencer circuit, inputs the encoded line image signal during one-dimensional encoding, outputs the color information and the change point address, and outputs the reference line image signal during two-dimensional decoding. a change point detection circuit that inputs and outputs a change point address of the reference line to the mode determination circuit;
Under the control of the sequencer circuit, image data is input from the image bus interface circuit to the change point detection circuit, and change point address information of the image data is output to the system bus interface circuit via the data memory. 2. The image signal conversion/decoding large-scale integrated circuit according to claim 1. 3. Under the control of the sequencer circuit, pattern data is input from the system bus interface circuit to the change point detection circuit via the data memory, and change point address information is input from the system bus interface circuit via the data memory. 3. The large-scale image signal conversion/decoding integrated circuit according to claim 2, wherein the image signal conversion/decoding large-scale integrated circuit outputs an image signal. 4. A first-in, first-out memory is provided that inputs data from the system bus interface circuit and the image bus interface circuit and outputs the data to the change point detection circuit, and receives pattern data from the system bus interface circuit under control of the sequencer circuit. 3. Image signal conversion/decoding according to claim 2, wherein the change point address information is input to the change point detection circuit via the first-in first-out memory and output from the system bus interface circuit via the data memory. Large scale integrated circuits.