JP2002311104A - Testing circuit of integrated circuit device and method for testing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable non-defective/defective decision of each functional block to be easily executed by a little number of test/data inputting and a little number of output data bits in a short time in an integrated circuit device having a plurality of functional blocks. SOLUTION: The integrated circuit device 2 comprises a test data storage unit 3, a bus switching controller 4 for reading in parallel test data from the storage unit and imparting the read data to a plurality of functional blocks FB(1) to FB(n), each digit output data compressing unit 5 for processing to compress the outputs of the blocks at each digit, an overall digit output compressing unit 9 for further compressing the digit compressed outputs, an external output interface unit 10 for outputting the outputs of the overall digit output compressing unit to an external terminal, and a test command controller 8 receiving the test command from the tester to control the command. Thus, the tester side inputs a test command, compares the output data of the external output terminal with an expected value, and executes the non-defective/defective decision of the integrated circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit device having a plurality of functional block circuits as constituent elements, and
The present invention relates to a test circuit and a test method for a semiconductor integrated circuit device such as an ASIC (Application Specific Integrated Circuit) configured by combining blocks.

[0002]

2. Description of the Related Art As a first conventional example in this technical field, a "semiconductor integrated circuit" described in Japanese Patent Application Laid-Open No. 04-355383 is known. This conventional "semiconductor integrated circuit"
Is an input control circuit that supplies the same input data (test pattern data) to a plurality of function blocks in parallel, an output of any one of the plurality of function blocks and another function block And a switching circuit for comparing each output with the output of the functional block. As a result, it is possible to reduce the test time and the test pattern of the functional block in a semiconductor integrated circuit having a plurality of functional blocks having the same function.

As a second conventional example, Japanese Patent Application Laid-Open No.
Japanese Patent Application Laid-Open No. 101855 discloses “Test Circuit and Test Method for Semiconductor Integrated Circuit and Semiconductor Device”. In the second conventional example, output data output from a signal processing circuit to be tested is temporarily held by a flip-flop circuit, and arithmetic processing such as exclusive OR is performed with the next output data by a logic circuit. And a data compression circuit for compressing and outputting the data to a number smaller than the number of output data, and outputting the compressed output data as device output data via a switch circuit.
Then, an operation test of the semiconductor integrated circuit is performed by comparing the output data with an expected value prepared in advance.

As a third conventional example, Japanese Patent Application Laid-Open No.
JP-A-003424 discloses an “integrated circuit device and a test data generation circuit incorporated in the integrated circuit device”.
In the third conventional example, a data generator for generating test data corresponding to each of a plurality of functional blocks;
A data generator is specified as a source of test data, an instruction register for storing instruction information for specifying a transfer destination of the test data, a decoder for decoding the stored instruction information, and a signal decoded by the decoder. In response, a test function including an input register for providing test data to the functional block and an external interface unit for outputting output data of the functional block or output data compressed by the compression means to the outside is provided in the integrated circuit device. The test function is controlled by embedded and ordinary instruction information. This makes it possible to reduce the amount of hardware required for realizing the test function.

[0005]

In the above-mentioned first conventional example, the input test pattern data is reduced, but the test target is limited to a plurality of functional blocks having the same function. There is a problem that a plurality of functional blocks having different functions are not effective.

In the second conventional example, it is necessary to give input test pattern data to a signal processing circuit to be tested for each output data in order to obtain each output data. There is a problem in reducing the number and shortening the test time.

In the third conventional example, it is necessary to provide instruction information for each functional block, and there is a problem in that the test time is shortened.

According to the present invention, the number of test pattern data and the test time can be reduced for a plurality of functional blocks having different functions, and the bit width of output data can be reduced. The present invention provides a test circuit and a test method that can perform the test.

[0009]

In order to solve the above-mentioned problems, a test circuit for an integrated circuit device according to the present invention relates to a built-in test circuit for an integrated circuit device having a plurality of functional blocks. A test data storage unit for holding test data to be input to each functional block,
A bus switching control unit that controls the plurality of functional blocks to input the same test data read from the test data storage unit in parallel;
For output data of each functional block with respect to data input, a logical operation is performed for each digit of each bit of the output data,
An output data compression unit for compressing and outputting one bit of output data for each digit, an external output interface unit for outputting the output data of the output data compression unit to an external terminal of the integrated circuit device, and an external test A test command control unit for interpreting and controlling the execution of the instruction in response to the control instruction.

Alternatively, for a test circuit of an integrated circuit device having a plurality of functional blocks, the test circuit
A test data storage unit for holding test data to be input to each of the functional blocks, and control to input the same test data read from the test data storage unit to the plurality of functional blocks in parallel A bus switching control unit that performs logical operation for each digit of each bit of the output data with respect to the output data of each functional block corresponding to the same test data input, and compresses the output data into one bit for each digit. An output data compression unit for compressing the output data, which has been compressed to 1-bit output data for each digit, over each digit and outputting it as 1-bit compressed output data; and outputting the output data of the output data compression unit. An external output interface for outputting to an external terminal of the integrated circuit device; and a test for interpreting and controlling the execution of the command in response to an external test control command · Characterized in that it is intended and a command control unit.

Further, the test data stored in the test data storage section is supplied from outside.

In addition, the logical operation of the output data compression unit is "1" when the value obtained by adding the bit value is odd for each digit bit of the output data of the plurality of functional blocks, and "1" when the value is even. This is a logical operation for generating an even parity bit of "0" for each digit, and outputs output data compressed for each digit bit to the external terminal.

Further, the logical operation of the output data compression unit is "0" when the value obtained by adding the bit value is odd for each digit bit of the output data of the plurality of functional blocks, and "0" when the value is even. This is a logical operation for generating an odd parity bit of "1" for each digit, and outputting output data compressed for each digit bit to the external terminal.

The logical operation of the output data compression unit is "1" when the value obtained by adding the bit value is odd for each digit bit of the output data of the plurality of functional blocks, and "1" when the value is even. A logical operation for generating an even parity bit of "0" for each digit is performed, and a logical operation for generating an even parity bit is similarly performed over each of the compressed digit bits. And outputting one bit of compressed output data obtained by compressing each digit bit to the external terminal.

Further, the logical operation of the output data compression unit determines "0" when the value obtained by adding the bit value is odd for each digit bit of the output data of the plurality of functional blocks, and "0" when the value is even. A logical operation for generating an odd parity bit of "1" for each digit, and a logical operation for similarly generating an odd parity bit over each of the compressed digit bits. The one-bit output data compressed over the respective digit bits is output from the external output terminal.

Further, the logical operation of the output data compression unit is processed by an exclusive OR operation.

In the test method for an integrated circuit device according to the present invention, an expected value of output data of each functional block is calculated in advance in accordance with the test data stored in the test data storage unit. The odd parity bit value or the even parity bit value is calculated in advance for each digit bit of the expected value of the output data, and is compared with the compressed output data output from the external terminal of the integrated circuit device. To determine the presence or absence of an error for each digit bit,
The quality of the integrated circuit device is determined.

Alternatively, an expected value of the output data of each functional block is calculated in advance according to the test data stored in the test data storage unit, and each of the expected values of the output data of each functional block is calculated. Odd
The parity bit value or the even parity bit value is calculated in advance, and the odd parity bit value or the even parity bit value for each digit calculated as described above over each digit bit is further modified. A parity bit value or an even parity bit value is calculated in advance and compared with the 1-bit compressed output data output from the external terminal of the integrated circuit device to determine the presence or absence of an error; It is characterized in that the quality of the device is determined.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram illustrating a configuration of a test circuit of an integrated circuit device according to a first embodiment of the present invention. In the drawing, the test circuit of the integrated circuit device according to the first embodiment of the present invention includes a plurality of functional blocks FB (1) to FB.
(N) is a test circuit of the integrated circuit device 2 provided with the functional block group 1, wherein the test circuit holds common test data input to each of the functional blocks FB (1) to FB (n). The same test data read from the test data storage unit 3 is stored in the test data storage unit 3 and the plurality of functional blocks FB (1) to FB (n).
A bus switching controller 4 for controlling data to be input in parallel; Perform logical operation for each digit,
An output data compression unit 5 for compressing and outputting 1-bit output data for each digit, and an external output interface unit 6 for outputting output data 51 of the output data compression unit 5 to an external terminal 61 of the integrated circuit device 2 And a test command control unit 8 that receives a test control command from the outside such as a tester 7 to interpret and control the command.

Next, a test method for performing a function test on each of the functional blocks FB (1) to FB (n) provided in the integrated circuit device using the test circuit of the integrated circuit device will be described. explain.

FIG. 3 is a flowchart for explaining an execution procedure of a test method for an integrated circuit device according to a second embodiment of the present invention. First, in a first step S1, a test mode setting instruction is given from an external tester 7 to the test command control unit of the integrated circuit device 2 to set the test mode. Next, in a second step S2, test data commonly input to the plurality of functional blocks FB (1) to FB (n) is transmitted via the test command control unit 8
The test data is stored in the test data storage unit 3. Third step S
In 3, the test command control unit 8 controls the bus switching control unit 4 by giving a test execution start command to the test command control unit 8 from the tester 7.
The test data stored in the test data storage unit 3 is read out, and the same test data read out is read in parallel to the plurality of functional blocks FB (1) to FB.
(N). In a fourth step S4, output data is output from each functional block to which the same test data has been input, according to each function. In a fifth step S5, the output data output from each of the functional blocks FB (1) to FB (n) is subjected to a compression process for each digit by each digit output data compression unit 5, and 1 bit is output for each digit. Is output as output data 51. In the sixth step S6,
The output data compressed for each digit is output to the external output terminal 61 via the external output interface unit 6. In the seventh step S7, the external tester 7
Compressed output data output to the external output terminal 61;
Comparing with expected value data, it is judged as good if they are the same and defective if they are different. Here, the expected value is calculated in advance by calculating the output data expected value of each functional block with respect to the test data input and compressing the output data expected value by each digit output data compression unit 5. The expected value data is calculated and prepared in the tester in advance. As described above, the quality of the integrated circuit device is determined by the test method for the integrated circuit device according to the second embodiment of this invention.

Next, a test circuit of an integrated circuit device according to a third embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 9 is a diagram illustrating a configuration of a test circuit of the integrated circuit device according to the third embodiment. The difference from the test circuit of the integrated circuit device according to the first embodiment shown in FIG. 1 is that the output data 51 of each digit output data compression unit 5 is further subjected to a compression process over all digits, and the all-digit output data compression unit 9 is used. Is provided.

That is, the all digit output data compression unit 9
As in the test circuit of the integrated circuit device according to the first embodiment, the output data 51 that has been subjected to the compression processing by the digit output data compression unit 5 is further data-compressed over each digit and output as 1 bit. Data 91 is obtained.

On the tester side, the output data compressed to 1 bit output from the external terminal 101 via the external output interface unit 10 and the expected value data calculated in the second embodiment are further similar. The 1-bit expected value data calculated by performing the compression process is compared, and if they are the same, it is determined to be a good product, and if they are different, it is a defective product, and the quality of the integrated circuit device is determined.

Next, a description will be given of the contents of compression processing in the above-mentioned digit output data compression section. Conventionally, an error detection method using a parity check bit has been used as a method for detecting a one-bit error in data. The compression processing contents of each digit output data compression section 5 and all-digit output data compression section 9 of the present invention are the same processing contents as the parity check bit generation processing.

FIG. 4 is a block diagram showing a configuration example of a compression processing circuit provided for each digit when the number of functional blocks is eight. Each digit output data D (f,
i) <f is a functional block number, i is a digit position number of output data> is an exclusive OR circuit 41-
An exclusive OR operation is performed at 44. Further, the exclusive OR circuits 45 and 46 perform an exclusive OR operation on each of the outputs 410, 420, 430 and 440 in the same manner for each two bits. Similarly, these exclusive OR circuits 45,
The exclusive OR circuit 47 performs an exclusive OR operation on each of the outputs 46 to output each digit output data.
The data is compressed into 1-bit digit output data (in this case, even parity bit), and each digit output data compression unit 5
Output data 51.

If the data width of each functional block is m bits, the all-digit output data compression section 9 similarly performs an exclusive OR operation on the m-bit output data, thereby obtaining a 1-bit output data. The output data 91 is obtained.

On the tester side, the same compression processing as that described above is applied to the expected value output data of each functional block for the input test data, so that the output data 51 of each digit output data compression unit 5 is processed. The expected value data or the expected value data for the output data 91 of the all-digit output data compression unit 9 is calculated in advance and prepared, so that the external output terminal 61 or 101 of the integrated circuit device 2 under test is output. The output data can be compared with the output data.

Further, by making the output data of each functional block externally readable, a more detailed error analysis becomes possible when an error is detected in the integrated circuit device.

[0031]

As described above, the test circuit of the integrated circuit device of the present invention inputs the same test data to a plurality of functional blocks in parallel and outputs the output data of each functional block for each bit digit. The data is compressed and output to an external terminal, or the compressed output data is further compressed over each digit bit and output to the external terminal as 1-bit compressed output data. A single-bit error can be easily detected, and the number of test data inputs and the output of a small number of bits, in which the pass / fail judgment of the integrated circuit device to be tested is small,
In addition, there is an effect that it can be executed in a short time.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a test circuit of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a test circuit of an integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a flowchart illustrating a procedure of an integrated circuit test method according to a third embodiment of the present invention.

FIG. 4 is a view for explaining a configuration example of compression processing contents of each digit output data compression circuit unit or all digit output data compression unit of the present invention.

[Explanation of symbols]

Reference Signs List 1 functional block group 2 integrated circuit device 3 test data storage unit 4 bus switching control unit 5 each digit output data compression unit 6 external output interface unit 7 tester 8 test command control unit 9 full digit output data compression unit 10 external output interface Unit 41, 42, 43, 44, 45, 46, 47 Exclusive OR circuit 51 Each digit output data compression output 61 External output terminal signal 91 All digit output data compression output 101 External output terminal signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H01L 27/04 TF term (Reference) 2G132 AA13 AA15 AC04 AD06 AH01 AK22 AL09 5B048 AA20 BB05 CC02 DD05 5F038 DF11 DT05 DT15 EZ20

Claims (10)

[Claims] 1. A test circuit for an integrated circuit device having a plurality of function blocks, wherein the test circuit stores a test data storage unit that stores test data to be input to each of the function blocks; A bus switching control unit for controlling the blocks so as to input the same test data read from the test data storage unit in parallel; and an output unit for the output data of each functional block corresponding to the same test data input. An output data compression unit for performing a logical operation for each digit of each bit of data and compressing and outputting 1-bit output data for each digit, and an external terminal of the integrated circuit device for outputting the output data of the output data compression unit An external output interface unit for outputting the command to a test command control unit for interpreting and executing the command in response to an external test control command A test circuit for an integrated circuit device, comprising: 2. A test circuit for an integrated circuit device having a plurality of function blocks, wherein the test circuit stores a test data storage unit for storing test data input to each of the function blocks; A bus switching control unit for controlling the block to input the same test data read from the test data storage unit in parallel, and the output data of each functional block for the same test data input A logical operation is performed for each digit of each bit of data, and the output data is compressed to 1-bit output data for each digit, and the output data compressed to 1-bit output data for each digit is compressed for each digit. An output data compression unit for outputting the output data as 1-bit compressed output data, and an output terminal for outputting the output data of the output data compression unit to an external terminal of the integrated circuit device. A test circuit for an integrated circuit device, comprising: a unit output interface unit; and a test command control unit that receives an external test control instruction, interprets and controls the instruction. 3. The test circuit according to claim 1, wherein the test data stored in the test data storage unit is externally supplied. 4. The logical operation of the output data compression unit performs a logical operation for each digit bit of output data of the plurality of functional blocks.
This is a logical operation for generating an even parity bit for each digit, which is "1" when the value obtained by adding the bit values is odd and "0" when it is even, and is an output compressed for each digit bit. 4. The test circuit for an integrated circuit device according to claim 1, wherein data is output to said external terminal. 5. The logical operation of the output data compression unit performs a logical operation for each digit bit of output data of the plurality of functional blocks.
This is a logical operation for generating, for each digit, an odd parity bit that becomes “0” when the value obtained by adding the bit values is odd and “1” when the value is even, and outputs an output compressed for each digit bit. 4. The test circuit for an integrated circuit device according to claim 1, wherein data is output to said external terminal. 6. The logical operation of the output data compression unit performs a logical operation for each digit bit of output data of the plurality of functional blocks.
A logical operation is performed to generate, for each digit, an even parity bit that becomes “1” when the value obtained by adding the bit values is odd and “0” when the value is even, and further compresses each of the compressed digit bits. A logical operation for generating an even parity bit in the same manner, and outputting 1-bit compressed output data obtained by compressing the digit bits to the external terminal. 1, 2 or 3
A test circuit for the integrated circuit device according to claim 1. 7. A logical operation of the output data compression unit is performed for each digit bit of output data of the plurality of functional blocks.
A logical operation for generating an odd parity bit for each digit, which becomes "0" when the value obtained by adding the bit values is odd and "1" when it is even, is performed, and further, the above-mentioned compressed digit bits And performing a logical operation to generate odd parity bits in the same manner, and outputting 1-bit output data compressed over the respective digit bits from the external output terminal. 4. The test circuit for an integrated circuit device according to 1, 2, or 3. 8. The integration according to claim 1, wherein the logical operation of the output data compression unit is processed by an exclusive OR operation. Test circuit for circuit equipment. 9. An expected value of output data of each functional block is calculated in advance in accordance with test data stored in the test data storage unit, and each digit bit of the expected value of output data of each functional block is calculated. 6. An odd parity bit value or an even parity bit value is calculated in advance for each digit bit and compared with compressed output data output from the external terminal of the integrated circuit device according to claim 4 or 5. A test method for the integrated circuit device, wherein the presence or absence of an error is determined to determine whether the integrated circuit device is good or bad. 10. An expected value of output data of each functional block is calculated in advance according to test data stored in the test data storage unit, and each digit bit of the expected value of output data of each functional block is calculated. An odd parity bit value or an even parity bit value is calculated in advance for each of the digit bits, and the odd parity bit value or the even parity bit value is calculated over the respective digit bits. 8. The integrated circuit according to claim 6, wherein an even parity bit value is calculated in advance and compared with 1-bit compressed output data output from the external terminal of the integrated circuit device according to claim 6 to determine whether there is an error. A test method for an integrated circuit device, wherein the quality of the device is determined.