JPS63238722A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To shorten a pull-in time and to stabilize the frequency of a pulled-in regenerative clock by using a difference value of frequency information as it is or after amplifying it in accordance with the amplitude of the difference value. CONSTITUTION:A difference device 1 finds out a difference between frequency obtained from the transmitting side and that formed on the receiving side in accordance with a regenerative clock and generates difference value information. When the amplitude of the difference value information is included within a prescribed range, the information is applied to an integrated circuit as it is, and when the value is not included in the range, the information is adjusted at its gain by a gain adjusting circuit 3 and then applied to the integrated circuit 4. An integrated value obtained from the circuit 4 is applied to an oscillator 6 through a D/A converter 5 to generate a regenerative clock. A counting circuit 7 counts the regenerative clock to form the frequency information of the regenerative clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock recovery circuit, and more particularly to a clock recovery circuit that generates a clock synchronized with sequentially received clock frequency information.

[Conventional technology]

Conventionally, this type of clock recovery circuit calculates the difference between the frequency information sent from the transmitting side and the frequency information of the recovered clock, integrates this difference value, and converts it into a voltage to determine the oscillation frequency of the voltage-controlled oscillator. Through this control, a regenerated clock synchronized with the incoming frequency information is generated.

[Problem that the invention seeks to solve]

In the conventional clock recovery circuit described above, the number of bits of frequency information on the transmitting side is set in consideration of reducing the transmission capacity.
For example, when X-bit frequency information is sent, the receiving side uses ybi to improve the stability of the recovered clock.
Calculation is performed using an integrating circuit of t (x<y). Note that the difference value X bits of the frequency information is input to the lower X bits of the integrating circuit. In this case, when the reproduced clock begins to synchronize with the transmission clock, only the lower few bits of the frequency information difference value change, and the amplitude of the difference value decreases by 9 degrees. Furthermore, when this differential amplitude is input to the integrating circuit, it becomes equivalent to multiplying by 1/2.

Therefore, although the stability of the reproduced clock is good, the gain decreases by 9 when it is input to the integrating circuit, so it has the disadvantage that it takes a considerable amount of time until the reproduced clock becomes equal to the standard.

On the other hand, in order to eliminate the gain reduction in the integrating circuit and eliminate the above-mentioned drawback, if the difference value of the frequency information is changed to be converted directly into voltage to control the oscillator, the synchronization pull-in time will be shortened, but the difference value This has the disadvantage that the value fluctuation directly affects the frequency fluctuation, resulting in poor stability of the reproduced clock.

[Means for solving problems]

The clock recovery circuit of the present invention includes a difference device that includes first frequency information indicating the frequency of an incoming clock and second frequency information indicating the frequency of the recovered clock, and a difference value within a predetermined range. gain control means for determining whether or not the difference is within the range, multiplying the difference information by a gain set in advance according to the result of the determination, and transmitting the resultant information; and clock generation means for controlling the frequency of the clock and generating the second frequency information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The subtractor 1 generates difference value information C between the frequency information a sent from the transmitting side and the frequency information generated on the receiving side using reproduced signals and f. The amplitude detection circuit 2 determines whether the amplitude of this difference value information C is within a predetermined range and outputs a determination signal d. When the determination signal d indicates that the amplitude of the difference value information C is within a predetermined range, the gain adjustment circuit 3 outputs the difference value information C as is, and when it is outside the range, the gain adjustment circuit 3 outputs the difference value information C as is. The value information is multiplied by ct-n (n is a preset number of 1 or more) and then sent, and the gain given to the difference value information C is adjusted. The integration circuit 4 integrates the output information e from the gain adjustment circuit 3. The integral value is converted into an analog voltage by a digital-to-analog converter (D/A) 5, and a voltage-controlled oscillator 6t is controlled by this analog voltage to send out a reproduced clock f. The counting circuit 7 receives the reproduced clock f
By counting the frequency information of the first regenerated clock, all the frequency information is generated and sent to the subtractor 1.

〔Effect of the invention〕

As explained above, the present invention determines whether the amplitude of the difference value of frequency information is within a predetermined range, and if it is within the range, the difference value is used, and if it is outside the range, the difference value is used. By amplifying and using the difference value, it is possible to shorten the synchronization pull-in time and to stabilize the frequency of the recovered clock after the pull-in.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. l...Differentiator, 2...Amplitude detection circuit,
3...Gain adjustment circuit, 4...Integrator circuit, 5...Digital-to-analog converter (1)/
A'), 6...oscillator, 7...counting circuit. Kaya l flash

Claims (1)

[Claims] a differentiator that takes the difference between first frequency information indicating the frequency of the incoming clock and second frequency information indicating the frequency of the recovered clock; and a subtractor that determines whether the value of the difference is within a predetermined range and that gain control means that multiplies the difference information by a preset gain according to the determination result and sends the result;
A clock regeneration circuit comprising: clock generation means for controlling the frequency of the regenerated clock and generating the second frequency information in response to information sent out from the gain control means.