JPH04192771A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To use an inexpensive D/A converter by operating the high-order bit of a level control signal during the prescribed period of time after a signal is inputted and synchronization is established, then fixing the data of the high- order bit and feedbacking a low-order bit. CONSTITUTION:A lock detector circuit 8 detects the phase of synchronization in a system with a signal of the generation of a synchronization detecting and reproducing circuit 3. Receiving the locking signal, a timer circuit 9 sets a gain for a signal level detection circuit 5 and transmits a pulse to a latch circuit 10. Thus, the high-order bit of the control signal for the input signal is defined. The timer circuit 9 holds the latch circuit 10 thereafter and outputs a signal switching the gain so as to performs the operation of the low-order bit. Thus, the size of the circuit can be reduced by using the signal level detection circuit in time division and the accurate control using the inexpensive A/D converter can be performed by dividing the control signal data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic gain control circuit for television signals.

BACKGROUND OF THE INVENTION As digital signal processing technology advances, more and more devices are using A/D converters. Analyze the signal
When performing D conversion, management of the Azukawa 1G input signal level is required in order to make effective use of the limited dynamic range.

Figure 2 is a bronch diagram showing a conventional automatic gain control circuit.
The video signal input to the variable gain amplifier 1 is amplified and
/D converter 2. Using the data output from the A/D converter 2, the synchronization detection clock regeneration circuit 3 detects the synchronization signal in the video signal, and the A/D converter 2, which is phase synchronized with the synchronization signal, generates a four-fold clock or Generates various pulses necessary for the video signal processing circuit 4. At the same time, a window signal is generated to extract amplitude information from the video signal. Upon receiving this window signal, the signal level detection circuit 5
From the output data of the D converter 2, for example, data inversely proportional to the amplification of the video signal is obtained from the horizontal synchronizing signal waveform. This data is converted into an analog signal by a D/A converter 6 and input to the control terminal of the variable gain amplifier 1 via a low-pass filter 7 to remove unnecessary high frequency components.

This constitutes a negative feedback loop including the A/D converter, and automatically controls the input level.

Problems to be Solved by the Invention In the circuit described above, if the control gain of the variable gain amplifier 1 is "1" and the number of quantization bits of the A/D is N, in order to obtain a pull-in range of 6 dB, the control gain must be D/A
The number of bins I of the converter needs to be N+1 or more.

In this way, in a control system that feedbanks the results of digital calculations, the quantum bi of the data that is fed back.

The controllable Guinamin range is limited by the number of I. Another problem was that it was difficult to obtain a high-precision D/A converter.

Means for Solving the Problems An automatic gain control circuit according to the present invention receives a signal as input,
After synchronization is established, the binary bits of the level control signal are operated for a certain period of time, and then the upper bit data is fixed and the lower bit data is fed back.

According to the present invention, by dividing the control signal data, it is possible to use an inexpensive /A converter. Furthermore, since the signal level detection circuit can be used in a time-division manner, the circuit scale can be reduced.

Embodiment FIG. 1 is a block diagram showing an automatic gain control circuit according to an embodiment of the present invention, and numerals 1 to 5 in the figure are equivalent to the conventional one. 8 is a lock detection circuit to which the output of the synchronization detection circuit 3 is input; 9 is a timer circuit to which the output of the lock detection circuit 8 is input; 10 is the signal level detection circuit 5
A latch circuit 11 receives the upper bit of the output data and holds the data by the output of the timer circuit 9;
/A converter, I2 is a low-pass filter into which the output of the D/A converter 11 is input, and 13 is a D/A into which the lower bits of the output data of the signal level detection circuit 5 are input.
converter; 14 is a low-pass filter into which the output of the D/A converter 13 is input; 15 is an adder that adds the outputs of the two low-pass filters 12 and 14 and supplies the sum to the control terminal of the variable gain amplifier 1; It is.

The operation of an embodiment of the present invention configured as described above will be described below.

The input video signal is amplified by the variable gain controller 1,
The signal is input to the A/D converter 2. The output data of the A/D converter 2 is input to a synchronization detection and reproduction circuit 3, which detects a synchronization signal in the video signal and generates various pulses whose phase is synchronized with the input signal. At the same time, a window signal is generated to extract amplified information from the video signal, and the signal level detection circuit 5
Thus, digital data for controlling the variable gain amplifier 1 is obtained.

The lock detection circuit 8 detects, from the signal generated by the synchronization detection and reproduction circuit 3, that the system is phase-locked with the input signal. Upon receiving this lock signal, the timer circuit 9 instructs the signal level detection circuit 5 to perform a calculation on the upper bits.
While setting the gain, a pulse is sent to the latch circuit 10 to pass data. This determines the upper bits of the control signal for the input signal. The timer circuit 9 holds the latch circuit 10 after the time required for determining the upper bits has elapsed, and outputs a signal to the signal level detection circuit 5 to switch the gain so as to perform calculations on the lower bits. The upper and lower data obtained in this way are transferred to the D/A converter I.
L 13 into an analog signal and low pass filter 12. ] 4 to remove unnecessary high frequency components, and the adder 15 adds the voltage to obtain the control voltage of the variable gain amplifier 1.

Effects of the Invention The automatic gain control circuit according to the present invention configured as described above uses the signal level detection circuit in a time-division manner, so that the circuit scale can be reduced. Furthermore, by dividing the control signal data, there is an effect that more accurate control can be performed using an inexpensive /A converter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an automatic gain control circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional automatic gain control circuit. 1...variable gain amplifier, 2...A, /
D converter, 3...Synchronization detection regeneration circuit, 4...
...Video signal processing circuit, 5...Signal level detection circuit, 6.11.12...D/A converter, 7
．． 12.14...Low pass filter, 8...
... Lock detection circuit, 9 ... Timer circuit,
1゜・・・Latch circuit, 15・・・Adder.

Claims (1)

[Claims] A variable gain amplifier is provided in the front stage of an A/D converter of a device that A/D converts a television signal and performs digital signal processing, and the gain of the variable gain amplifier is automatically controlled. A signal level detection circuit that detects the current signal level using a part of the output waveform of the D converter and calculates the difference from the amplification reference value, and a lock that detects that the internal clock is phase-synchronized with the input signal. a detection circuit; a timer circuit that receives a lock signal from the lock detection circuit and outputs a switching signal after a certain period of time; and a latch circuit that holds the upper bit signal of the output of the signal level detection circuit using the output of the timer circuit. , a D/A converter that converts the output of the latch circuit into an analog signal, a D/A converter that converts the lower bit output of the signal level detection circuit into an analog signal, and a D/A converter that converts the output of the two D/A converters into an analog signal. An automatic gain control circuit comprising an adder that performs addition, and the variable gain amplifier is automatically controlled by the output of the adder.