JPS63237476A - Manufacture of insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine MOS including a gate electrode in the manner of self-algnment, by forming, in an active layer, inverse conductivity type source and drain regions by impurity diffusion from a second semiconductor film, and forming a part of source and drain wiring with a first semiconductor film being in contact with the second semiconductor film. CONSTITUTION:On the exposed surface of an active region 11, a gate oxide film 80 is formed by a thermal oxidation and the like. In this thermal processing, N-type source.drain regions 12 and 13 are formed by impurity diffusion from a second semiconductor film 61 into the active region 11. After this process, a selective etching is performed using a mask process in order to left a first and a second semiconductor films 40 and 61 inside the lines 120 is figure, and a conducting film 91. Therefore, a source wiring 42 and a drain wiring 43 are formed by a first semiconductor film 40, source.drain electrodes 62 and 63 are formed by a second semiconductor film 61 at the end-portion of an aperture, and a gate electrode 91 is formed by the conducting film 91. Then, an insulating film 110 of SiO2 and the like is deposited if necessary, and contact holes 142, 143, 149, etc., are made to arrange wirings 102, 103, etc., of Al and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a self-aligned manufacturing method for insulated gate semiconductor devices, particularly MO3 integrated circuits.

[Essentials of invention]

The method for manufacturing an insulated gate semiconductor device of the present invention includes the following steps: a. exposing an active region to a field insulating film on the surface of a P-type semiconductor substrate; and b. a first oxide film, an N-type first polycrystalline film, and a second oxide film. a step of sequentially depositing a three-layer multilayer film consisting of a C6 active region, and forming an aperture in the multilayer film on the active region that is narrower than one width of the C6 active region and wider than the other, and the end of the aperture is substantially vertical or d. Depositing a second polycrystalline film containing N-type impurities; e. Anisotropically etching the second polycrystalline film to remove the active region and the second oxide. exposing the film and leaving a second polycrystalline film along the opening edges of the multilayer film; f) exposing the active region again by an anisotropic etching/notch after depositing a third oxide film; , leaving a third oxide film on the side surface of the second polycrystalline film along the edge of the opening of the multilayer film; g. providing a gate insulating film on the exposed active region surface; h. A step of depositing a crystalline film; i. Applying a resist to make the surface almost flat, performing an etch bank until the second oxide film is blown out, and depositing a third polycrystalline film in the openings of the multilayer film. a step of forming a remaining gate electrode; j. 1st. selectively removing unnecessary portions of the second and third polycrystalline films; The first polycrystalline film in contact with the film forms part of the source and drain wiring. Fine source and drain regions and gate electrodes can be formed in a self-aligned manner.

[Conventional technology]

The miniaturization of transistors is progressing year by year in response to demands for high speed and high integration. Among these, self-alignment technology is required in combination with microfabrication technology to miniaturize elements. For example, Electronics Letters, Volume 19,
283 pages (1983) or JP-A-54-82175
．． The bipolar manufacturing method described in Japanese Patent Application Laid-Open No. 15230/1983 uses self-alignment technology using so-called SST to produce 30 pse.
A delay time of c is obtained. On the other hand, the Institute of Electronics and Communication Engineers Technical Research 1 Notice SSD 84-101 (December 18, 1984)
An MO3 self-alignment method named MUSA-MO3T is described in Japan). In the above two methods, one electrode (base or source/drain) and the contact hole or gate insulating film formation region of the other electrode (emitter) are self-aligned, but the other electrode (emitter or gate electrode) is Unable to self-align.

That is, a planar overlapping portion occurs between one electrode and the other electrode, resulting in a large parasitic capacitance, which hinders speeding up.

In addition, for fine MO3, LDD (
The above method is difficult to apply to a lightly doped drain structure.

[Problem that the invention seeks to solve]

The present invention provides a manufacturing method that can form a fine MO5 including a gate electrode in a self-aligned manner, and also provides a self-aligned manufacturing method that can easily realize an LDD structure.

[Means for solving problems]

The method for manufacturing an MO3 semiconductor device of the present invention includes: a. exposing an active region on the surface of a semiconductor substrate of one conductivity type covered with a field insulating film; b) a first insulating film, a first semiconductor film of an opposite conductivity type, and a second a step of sequentially depositing at least a three-layer multilayer film consisting of two insulating films; providing an opening in the multilayer film above the active region narrower than one width of the C9 active region and wider than the other width; d. Depositing a first semiconductor film of opposite conductivity type; e. Anisotropically etching the second semiconductor film to form a second semiconductor film along the edge of the opening in the multilayer film. f. leaving the third insulating film on the side surface of the second semiconductor film along the opening edge of the multilayer film by anisotropic etching after depositing the third insulating film; d) exposing the active region; Step of providing a gate insulating film on the surface; h. Step of depositing a conductive film; the conductive film is left in the opening of the multilayer film to serve as a gate electrode; j) the step of selectively removing the first and second semiconductor films as well as the unwanted portions of the conductive film; Then, source and drain regions of opposite conductivity type are formed by diffusion of impurities from the second semiconductor film, and part of the source and drain wirings are formed by the first semiconductor film in contact with the second semiconductor film.

1. After the process, remove or thin the third insulating film and add opposite conductivity type impurities at low density to provide low density source and drain regions adjacent to the opposite conductivity type source and drain regions;
A so-called LDD structure can also be realized.

[Effect]

In the present invention, when a thin film is almost isotropically deposited on a stepped surface and this thin film is anisotropically etched, the effective thickness of the thin film is large, so the thin film remains on the stepped side surface. 2
The semiconductor film and the third insulating film are selectively left on the side surfaces of the multilayer film opening. Therefore, it is desirable that the side surfaces of the multilayer film openings be vertical or negatively sloped (overhanging).

In addition, the gate electrode is formed by etching back after flattening the surface using a resist, etc., taking advantage of the fact that this electrode part is recessed compared to other parts due to the openings in the multilayer film. . Therefore, fine source/drain regions and gate electrodes can be formed in a self-aligned manner.

〔Example〕 The present invention will be explained in detail below using the drawings.

(a) Example 1 (FIGS. 1 and 2) FIG. 1 Fal-(11 shows a process sectional view based on an embodiment of the present invention, and FIG. 2 shows a plan view for explanation.

In FIG. 1, a field oxide film 20 is formed using selective oxidation or the like, and a first insulating film 30 is formed on a P-type Si substrate 10 exposing an active region 11 where a transistor will be provided in the future.
This is a cross section in which a three-layer multilayer film consisting of a first semiconductor film 40 and a second insulating IIW 50 is sequentially deposited. Active region 11 is provided within line 11 in FIG. The first insulating film 3°, the first semiconductor film 40, and the second insulating film 50 are each CVD-3i 0
2 (0,2 μm), poly Si (0,4 μrn)
.

For example, SiO□ (0.2 μm) is used, and poly-Si contains P-type impurities. Of course, the thickness of each layer can be selected at any value determined by process design. FIG. 1 (bl is a cross-section of a multilayer film with an opening so that the active region 11 is exposed; as shown by line 1 in FIG. The other end is located on field oxide film 20.

The end portion 1 of the opening needs to be etched substantially vertically or with a negative slope, and this can be done by reactive ion etching (RIE), ion beam etching, or the like. FIG. 1 tc+ shows a cross section of a P-type cylinder 2 semiconductor film 60, for example, poly-Si, which is isotropically deposited to a thickness of, for example, 0.5 μm by residual pressure CVD or the like. Figure 1 (in d+,
The second semiconductor film 60 is anisotropically etched using RfE or the like to expose the active region 11 and the second insulating film 50, while leaving the second semiconductor film 61 along the side surface 1 of the opening.

After further depositing a third insulating film 7o such as CVD-3iOz,
The cross section in which the third insulating film 71 is left along the side surface 2 of the second semiconductor film 61 by anisotropic etching again is shown in FIG. 1+11. The width of the third insulating film 71 can be controlled depending on the thickness and etching conditions, and is, for example, 0.3 μm.

Figure 1 (fl is the active nM exposed in the step of Figure 1(e))
This is a cross section in which a gate oxide film 80 is provided on the surface of the region 11 by thermal oxidation or the like. In this heat treatment step, the active f is removed from the second semiconductor film 61.
N-type source/drain regions 12 and 13 are formed by intra-region II region 1 intra-region 1 dopant diffusion. After that, the conductive film 90, for example, N
After depositing the type poly Sk (FIG. 1fg)), a surface flattening film such as a resist is deposited on the entire surface, and a flattening film and a conductive film 90 are formed.
FIG. 1 (hl) shows a state in which the conductive film 91 is left only in the multilayer film opening by a so-called etch bank that is etched at a rate substantially equal to that of the second insulating film 50.
The first semiconductor film 40 is exposed to the extent that the first semiconductor film 40 does not disappear. Furthermore, after this step, line 120 in FIG.
The first and second semiconductor films 40.61 and the conductive film 91 inside the
Selective etching is performed in the mask process to leave a trace. the result,
The source wiring 42 . The drain wiring 43 is formed by the second semiconductor film 61 at the end of the opening, and the source/drain electrodes 62 and 63 are formed by the conductive film 91, and the gate electrode 91 is formed by the conductive film 91. Thereafter, an insulating film 110 such as Sin is deposited as necessary, and contact holes 142, 143, 149, etc. as shown in FIG.
．． 103, etc., and complete it as shown in Figure 1+11.

1st. Second. 5 as 3rd insulation 11g30,50.70
An example using ift was described, but SiN, 5iON, PS
G, BPSG, etc. can also be combined as appropriate. Also, 1st. Second semiconductor film, conductive film 30, 60.
As 90, a multi-Ns material consisting of a high melting point metal and polySI can also be used.

(b) Example 2 LDD process sectional view (FIG. 3) FIG. 1 +11 to fc) shows a process sectional view when the present invention is applied to the LDD structure MO5. Figure 3 (al is Example 1
Similarly to the process example in Figure 1 (this is a cross section taken up to hl,
This is the state before the mask process and selective etching of the first and second semiconductor films 40.61 and the conductive film 91. However, the diffusion of the N-type source/drain regions 12 and 13 is made smaller than in the first embodiment, so that the double-headed region 12.13 becomes the gate electrode 91.
It is not superimposed with In FIG. 3 [bl], the third insulating film 71 exposed on the surface is connected to the conductive film 91 and the first insulating film 71. Second semiconductor 17
A 940.61 mask is removed, and N-type impurity ions are implanted into regions defined by the similar mask and field oxide film 20 to form low density source/drain regions 14 and 15. After that, unnecessary parts of the first and second semiconductor films 40.61 and the conductive film 91 are selectively etched, an insulating film 110 is deposited, contact holes are formed, and metal wiring is formed to complete the process as shown in FIG. 3 fc). . In the step of FIG. 3 fbl, the third insulating film 71 is
It is not necessary to completely remove it, but it may be made thin enough to allow selective ion implantation of N-type impurities.

(C) Example 3 Process sectional view (Fig. 4) Fig. 4 (al~
(El shows a process sectional view of another embodiment of the present invention.

FIG. 4 (Al is a first oxide film 30, a first poly 5i 40, a second insulating film F15 on the field insulating film 20 and the active region 11.
3 layers of 0 and 1! This is a cross section in which openings are provided on the active region 11 after the film has been deposited. For example, SiN is used as the second insulating film 50.
Use. In this example, the end of the opening has a negative slope cross section. Figure 4) has a second polygon 5i61. on the side wall of the opening. Third
The cross section in which the oxide film 71 is formed (FIG. 4 fc) shows the cross section in which poly 5i90 is deposited after the gate oxide film 80 is formed. Thereafter, a surface flattening film (resist, SOG, bias sputter film, etc.) is applied and etched back. As shown in FIG.゜Second. Figure 4 t shows a state in which a metal film 190 such as W or AI is selectively deposited on the third poly Si 40.61.91.
It is e+. Thereafter, a MOS transistor can be manufactured in the same manner as in Example 1 or 2. Through the above steps, a semiconductor device with low wiring resistance can be realized.

[Effects of the Invention] As described above, according to the present invention, it is possible to directly contact wiring such as polySt to minute source/drain regions, and gate electrodes can also be formed in a self-aligned manner without overlapping other electrodes. provided. Therefore, a MOS transistor with extremely small parasitic capacitance can be realized, and a high-speed, highly integrated semiconductor device can be obtained.

In addition, since the LDD structure can be easily manufactured, fine MO3
The present invention is very effective in the production of. Although an N-channel MOS has been described as an example, the same applies to a P-channel MOS, and the present invention can be applied even if the gate insulating film is other than an oxide film.

[Brief explanation of drawings]

Fig. 1 fal to F11 are cross-sectional views in the order of the manufacturing process of a MOS transistor according to the present invention, and Fig. 2 is a sectional view of Fig. 1 + al to (ll
FIG. 3 is a plan view for explaining (al to fC1 are LD
Cross-sectional views of D-MOS in the manufacturing process according to the present invention, FIG. 4f
al to tel are step-by-step sectional views of other embodiments of the present invention. 10...P-type Si substrate 11...Active regions 12, 13...N-type source/drain regions 14.
15... N-type low density source/drain region 20.
...Field insulating film 30...First insulating film 40.42.43...First semiconductor film 50...Second insulating film 60.61, 62.63...Second semiconductor Membrane 70.7
1...Third insulating film 80...Gate insulating film 90.91...Conducting film or more 46+)ll=Y6LDD-MOS) Lower side of sidewall of the sensor 31 side

Claims (4)

[Claims] (1) A first step of exposing an active region on the surface of a semiconductor substrate of one conductivity type where a transistor will be formed in the future and covering other regions with a field insulating film; a second step of sequentially depositing at least a three-layer multilayer film consisting of two insulating films, and forming an opening in the multilayer film above the active region, narrower than one width of the active region and wider than the other width; A third step in which one opposing end is located within the active region and the other opposing end is located on the field insulating film, and the opening end is substantially vertical or overhanging; a fourth step of depositing a second semiconductor film containing conductivity-type impurities; and anisotropically etching the second semiconductor film to expose the active region and the second insulating film, and depositing the active region and the second insulating film at the ends of the openings of the multilayer film. a fifth step of leaving a second semiconductor film along the side surfaces of the second semiconductor film along the opening edges of the multilayer film, and exposing the active region by anisotropic etching after depositing a third insulating film; A sixth step in which a third insulating film is left on the surface of the active region, a seventh step in which a gate insulating film is provided on the surface of the exposed active region, an eighth step in which a conductive film is deposited, and a planarization film that makes the surface almost flat is deposited. The planarizing film and the conductive film are removed by an etching means having substantially the same etch rate for the planarizing film and the conductive film until at least the second insulating film is exposed, and the conductive film is placed in the opening of the multilayer film. The method comprises at least a ninth step of forming a remaining gate electrode, and a tenth step of selectively removing unnecessary parts of the first and second semiconductor films and the conductive film, and forming a gate electrode from the second semiconductor film in the active region. A method for manufacturing an insulated gate type semiconductor device, characterized in that source and drain regions of opposite conductivity type are formed by impurity diffusion, and part of source and drain wirings are formed by a first semiconductor film in contact with a second semiconductor film. (2) After the ninth step, removing or thinning the third insulating film and selectively adding impurities of opposite conductivity type to the active region between the conductive film and the second semiconductor film at a low density. 2. A method of manufacturing an insulated gate semiconductor device according to claim 1, wherein: (3) The insulated gate according to claim 1 or 2, wherein the conductive film is a third semiconductor film, and the etching in the ninth step is performed until the first semiconductor film is exposed. A method for manufacturing a type semiconductor device. (4) After the ninth step, a step of selectively depositing a metal film on the exposed first and third semiconductor films is performed. manufacturing method.