JPS63234627A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the chip size by devising the titled circuit such that a 2nd MOS transistor(TR) is not electrified when a 1st MOS TR is electrified and a logic circuit is electrified and the 2nd MOS TR is electrified when the 1st MOS TR is electrified and the logic circuit is not electrified. CONSTITUTION:A MOS TR 7 is electrified at a half period of a clock signal PHIand an output terminal OUT 1 goes to a high level. When any of control signals E1-E3 at a high level or all of them are at a low level at the remaining half period of the clock signal PHI, for example, when the control signal E1 is at a high level, the logic circuit 2 is electrified the output OUT1 goes to a low level because of the conduction of the MOS TR 1 and the MOS TR 7 is not electrified. When the control signals E1-E3 are all at a low level, all the logic circuits 2,4,6 are not electrified. Thus, the output terminal OUT1 goes to a high level although the MOS TRs 1,3,5 are electrified and the logic circuit 8 electrify the MOS TR 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit such as a bus driver circuit used in a microprocessor.

[Conventional technology]

Conventionally, this type of output circuit has been a circuit in which the output of a tristate buffer circuit is connected in parallel to a pass line.

To explain with reference to Fig. 4, there are three tri-state buffer circuits (1 to 5, 6 to 10, and 11 to 15 in Fig. 4).
are connected to the pass line in parallel, and only one of the three tristate outputs is output from the pass line to the output terminal.

A timing chart of the operation is shown in FIG. Control signal E
l, E2. Either one of E3 becomes high level. For example, when El is at a high level, the input data signal D1 is output to the output terminal 0UT2. Similarly, for control signal E2, input data signal D2. Input data signal D3 corresponds to control signal E3. In the case of FIG. 4, the number of transistors is 36.

[Problem that the invention attempts to solve]

The conventional output circuit described above is a tri-state buffer circuit or is complex, so the number of transistors and size (LSI
The disadvantage is that the surface area (when the surface area becomes large) is large.

[Means for solving problems]

The output circuit of the present invention has a plurality of parallel circuits in which a first MOS transistor whose gate input is a clock signal and a logic circuit which becomes conductive or non-conductive depending on the logic of the data input signal and the control signal are connected in series. one terminal is connected to the output terminal, the other terminal is connected to one terminal of the power supply, and a second MOS transistor is connected to the output terminal and the other terminal of the power supply,
The clock signal causes the second MOS transistor to conduct when the first MOS transistor is non-conductive;
When the first MOS transistor is conductive and the logic circuit is conductive, the second MOS transistor is non-conductive, and when the first MOS transistor is conductive and the logic circuit is non-conductive, the second MOS transistor is conductive. The MOS transistor is characterized in that it is configured to be conductive.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The embodiment of FIG.
Logic circuits 2 and 4 each connected in series to the S transistor
．． 6 is connected in parallel to the output terminal OUT 1 and the ground, and the MOS transistor 7 is connected to the power supply VDD and the output terminal 0UT.
It is connected to I and the gate of the MOS transistor is driven by the logic circuit 8.

Seven MOS transistors become conductive during a half cycle of the clock signal Φ, and the output terminal 0UT1 becomes high level.

In the remaining half period of the clock signal Φ, the control signals E1, E2 .
If any one of E3 is set to high level or all of them are set to low level, for example, when the control signal E1 is at high level, the logic circuit 2 becomes conductive, the MOS transistor 1 becomes conductive, the output of 0UTI becomes low level, and Mo51 to Langisthu are non-conductive. becomes. In addition, control signals El, E2 . E3
When the control signals of are all low level, logic circuits 2, 4.6
are all non-conducting. Therefore, the output terminal 0UT1 becomes high level although the MOS transistors 1 and 3.5 are conductive, and the logic circuit 8 makes the MOS transistor 7 conductive.

That is, as shown in Fig. 5, 0UT in half period of clock Φ
1 becomes high level, but in the remaining half cycle, the control signals El, E2 . Input data signal DI,
D2. D3 is output to the output terminal 0UT1.

Next, a first embodiment of the present invention will be described with reference to FIG.

Figure 2 shows the logic circuits 2 and 4.6 in Figure 1 as a series circuit of two MOS transistors (2.3 and 5, 6 and 8 in Figure 2,
9), and this is an example in which the logic circuit 8 of FIG. 1 is realized using a two-man NOR and an inverter (FIG. 2, 11 and 12). The operation is the same as in FIG. The number of transistors in FIG. 2 is 16.

Similarly, a second embodiment of the present invention will be explained with reference to FIG. Figure 3 shows the first logic circuit 2, 4.6, which is a two-man NAND
and inverter (7.10 and 8, 11 and 9.12 in Figure 3)
), and this is an example in which the logic circuit 8 in FIG. 1 is realized by a two-man NOR and an inverter (14.15 in FIG. 3). The operation is the same as in FIG. The number of transistors in FIG. 3 is 31.

〔Effect of the invention〕

As explained above, the present invention has the effect of realizing an output circuit with a small number of transistors. If the present invention is implemented in a semiconductor integrated circuit, the chip size can be reduced by reducing the circuit scale due to the small number of transistors.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams of embodiments of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a time chart for explaining the operation of FIG. 4. , 6th
The figure is a time chart showing the operation of FIG. 1. 1.3, 5.7...MOS transistor, 2°4.6
．． 8...Logic circuit, 1-10...MOS transistor, 11...2 human power N0R112...inverter.

Claims (1)

[Claims] A plurality of circuits in which a first MOS transistor whose gate input is a clock signal and a logic circuit which becomes conductive or non-conductive depending on the logic of the data input signal and the control signal are connected in series are connected in parallel, and one of the circuits is connected in parallel. and a second MOS transistor is connected to the output terminal and the other terminal of the power supply, and when the first MOS transistor is non-conductive according to the clock signal, the second MOS transistor is connected to one terminal of the power supply. second M
When the OS transistor is conductive and the first MOS transistor is conductive and the logic circuit is conductive, the second MOS transistor is conductive.
The S transistor is non-conductive, and when the first MOS transistor is conductive and the logic circuit is non-conductive, the second MMOS transistor is non-conductive.
An output circuit characterized in that an OS transistor is configured to be conductive.