JPS63232662A - Interface testing instrument - Google Patents

Abstract

PURPOSE:To test an interface in real time, by providing a control register which stores information for designating the reception of signals from a partner side and reception of testing signals to be sent and a selector which switches receiving signals between the signals from the partner side and testing signals. CONSTITUTION:When a normal test is carried out by using the information stored in a register 45, tests on the operations of an interface is performed depending upon whether or not the delay until the reception is within an allowable delay time Ta designated by a register 47 and whether or not the continuation time of receiving signals is longer than an allowable minimum continuation time designated by another register 48. when a false normal test is carried by using the information stored in the register 45, the input to one input terminal of an AND circuit 6 is changed by using the receiving polarity designating information stored in the register 42 of the next higher digit of the lowest order of a control register 4 and an abnormality responding signal is returned to the interface.

Description

[Detailed Description of the Invention] [Summary] In order to test an interface at a terminal or a terminal connected to a line network, information specifying reception of a signal from the other side and reception of a test signal sent by the interface concerned. a control register including a first register for storing the information, and a selector for switching the received signal between the signal from the other party and the test signal sent by the self based on the stored contents of the first register. A second register for storing information specifying that the polarity of the received signal is to be inverted when receiving the test signal in the control register; A selection circuit is provided to invert the polarity of the received test signal based on the test signal, thereby making it possible to test the processing ability in response to an abnormal state.

[Industrial application field]

FIG. 4 shows an example of a transmission system equipped with an interface that is the subject of the test of the present invention, in which a terminal device 100 and a terminal device 110 connected to a communication network connect interfaces 101 and 111 provided respectively. They are connected to each other by a connecting transmission line, so that the terminal device can communicate with the communication network via this termination device.

The present invention relates to a device for testing the functionality of an interface in these terminal devices and terminal devices.

[Conventional technology]

Interface 101.11 as shown in Figure 4 above
When performing the test in 2, conventionally, the output end and the input end of the interface were short-circuited, the sent signal was directly received, and the test was performed by comparing the sent signal and the received signal. Tests have been carried out by removing the input/output lines of the interface Y, etc., and connecting a dedicated tester for testing the function of the interface between the connection terminals to these lines.

[Problem that the invention seeks to solve]

In all of the conventional techniques mentioned above, real-time testing cannot be performed because the connection of the input/output terminals must be changed, and the former method results in an operating state that differs from the operating state in actual use. However, the latter method had problems such as requiring a dedicated tester.

[Means for solving problems]

FIG. 1 is a block diagram showing the principle of the present invention. In order to test the interface 111 (101) at the end or terminal connected to the line network, the other side 101 (
111) and the corresponding interface 111
(101) includes a first register 41 that stores information specifying the reception of the test signal sent by the device; A selector 5 for switching between the signal and the test signal is provided.

The control register 4 further includes a second register 42 that stores information specifying to invert the polarity of the received signal when receiving the test signal, and receives the test signal based on the information stored in this register. A polarity selection circuit 6 can be provided to invert the polarity of the test signal.

[For production]

In normal use, the first register 41 of the register 4 is set to "0" so that the selector 5 supplies the received data from the receiver 3 to the interface 101 (111).
Information for switching the side input to output is stored.

The transmission signal from this interface 101 (111) is sent from the transmission register 1 via the driver 2 to the other side interface 111 (101), and the signal received from this other side interface 111 (101) is sent to the receiver 3. The data is then transferred to the interface 101 (111) via the selector 5 in the above switching state.

According to the present invention, when performing a test, the register 4 is
Information for switching the selector 5 so that the transmission data from the transmission register 1 is input to the interface is written into the first register 41 by a microprocessor (not shown), and thereby the selector 5 is set to "1". ” side input is switched to output.

As a result, the test signal from the transmission register 1 is sent back from the selector 5 to the interface via the polarity selection circuit 6, which will be described later, and the interface 101 (111) is tested by comparing it with the sent test signal, for example.

In addition, in order to conduct a test by inverting the polarity of the test signal sent back to the interface in this way, the above-mentioned polarity inversion circuit 6 is provided, and the polarity inversion circuit 6 is stored in the second register 42 of the register 4. After inverting the polarity of the output from the transmitting register 1 according to the inversion command information, the selector 5
can be sent back to this interface via.

〔Example〕

Figure 2 shows the present invention in an R3-2320 that processes serial data.
2 is a diagram showing an embodiment applied to an interface, in which components corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1. FIG.

In a normal communication state, the bit data written in the transmission register 1 is read out by the clock supplied to the transmission register from the AND circuit 11 when the read signal and select signal from the microprocessor 10 arrive at the same time. The selector 5 sends the bits from the driver 2 to the other side interface, and the bits received from this other side interface are sent to the microprocessor IO by the selector 5.
Since the output of the receiver 3 is in a switching state in which the input on the "0" side to which the output of the receiver 3 is connected is output by the output of the register 41 of the control register 4 which stores the data of the least significant bit of the data bus 20, A receiving register (not shown) is used to write received data through a gate 32 which is made conductive by an output signal from an AND circuit 31 when the selenoid signal 5 and a read signal and a select signal from the microprocessor 10 arrive from the receiver 3 at the same time. will be forwarded to.

When testing the interface, set the lowest pin (lowest pin) output of the data bus 20 from the microprocessor 10 to “1”.
” and the register 41 of the lowest digit of the control register 4 is set to “
1" is stored, and the selector 5 supplies the input on the "0" side, that is, the transmission output of the transmission register 1, to the gate 32 via the polarity selection circuit 6.

From the register 48 of the most significant digit of the control register 4 to the register 42 excluding the register 41 of the least significant digit, the selector is switched from the microprocessor 10 on the data bus 20 as shown in FIG. The bit information sent as parallel information along with the information is allocated and
The information stored in these registers 42 to 48 will also be described below with reference to the operational waveform diagram in FIG.

The most significant digit register 48 of the control register 4 contains the reception timing Tb, which is the maximum allowable delay time until reception, and the next most significant digit register 47 contains the reception timing Ta, which is the minimum duration time of the received signal. The registers 46 and 45 in the next order store bit information specifying pseudo-normal test and normal test, respectively.

A waveform diagram when performing a normal test, that is, a normal transmission/reception test using the information stored in the register 45, is shown in FIG. 3(a), and the signal (1) sent from the transmitting register 1 is When received as signal (2),
This interface depends on whether the delay until reception is within the allowable delay time Ta specified by the register 47 and whether the duration of the received signal is greater than or equal to the allowable minimum duration time specified by the register 48. Test the operation of.

In addition, when performing a pseudo-normal test using the information stored in the register 45, that is, when testing, for example, how to deal with an abnormal response as shown by E in the received signal (2) in FIG. 3, the control register is used. The input to one input terminal of the AND circuit 6 is changed according to the above-mentioned reception polarity designation information stored in the register 42 of the upper digit next to the lowest order of 4, and the abnormal response signal shown in the above is outputted from the ink face. send it back to

Note that registers 43 and 44 of the control register 4 store data for specifying test signals, and this control register @4 is output from the AND circuit 49 when both the write signal and the select signal are present. Writing is performed using the signal as a clock, and when the test is completed, it is reset by a reset signal from the microprocessor 10.

〔Effect of the invention〕

According to the present invention, an interface test can be performed in real time without switching input/output lines.
Furthermore, not only can the temporal behavior of the interface in actual operation be confirmed through testing, but by adding a polarity selection circuit, an abnormal response signal can be generated and supplied to the interface, thereby making it possible to control software such as processing programs. It is possible to achieve special effects such as making it possible to perform operational tests including the following.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is an embodiment, FIG. 3 is a test waveform diagram, and FIG. 4 is a diagram showing an example of a transmission system to which the present invention is applied. 4... Control register, 41... First register in this control register, 42... Second register in this control register, 5... Selector, 6... Polarity selection circuit.

Claims (2)

[Claims] (1) In order to test an interface in a terminating device or terminal device connected to a line network, a first device that stores information specifying reception of a signal from the other side and reception of a test signal transmitted from the interface concerned. Register (41
), and a selector (5) that switches the received signal between the signal from the other party and the test signal based on the contents stored in the first register. Interface test equipment. (2) The control register (4) further includes a second register (42) that stores information specifying to invert the polarity of the received signal when receiving the test signal; 2. The interface testing device according to claim 1, further comprising a selection circuit (6) for inverting the polarity of the received test signal based on the information that the interface testing device receives.