JPS63231661A - Precedence controller - Google Patents

Abstract

PURPOSE:To arbitrarily change the priority level of each device by providing a memory, which outputs a permission signal based on the state of the request signal of the device and the state of the preceding permission signal, and a holding means which holds the permission signal from the memory and outputs it to the memory at the next time. CONSTITUTION:A memory 11 which outputs the permission signal based on the request state of the device and the state of the preceding permission signal and a holding means 12 which holds the output of the memory 11 and outputs it to the memory 11 at the next time are provided. Since the priority level of the device is stored in the memory 11, it is unnecessary to extend the hardware constitution in case of the increase of the number of devices, whose priority levels should be controlled, if the setting information volume of priority level is equal to or smaller than the capacity of the memory 11. If contents of the memory 11 are so set that continuous designation of the same device is inhibited, processings of devices having lower priority levels are prevented from being stagnated by monopolization of the device having a higher priority level; and in case of the change of priority levels of devices, it is sufficient if a memory having different contents is attached.

Description

[Detailed Description of the Invention] [Summary] The present invention makes it possible to prevent processing from being biased toward a specific device when generating a permission signal when request signals from multiple devices conflict, and also to prevent processing from being biased toward a specific device. In order to be able to easily assign different priorities, there is provided a memory for outputting a grant signal to the priority controller based on the state of the request signal of the device and the state of the previous grant signal, and a grant of this memory. A holding means for holding the signal and outputting it to the memory next time is provided.

(Industrial Application Field) The present invention relates to a priority control device, and particularly to a priority control device that generates a permission signal according to a predetermined priority when requests from multiple devices conflict. be.

[Conventional technology]

Conventional priority control devices include the following devices that control the priority of interrupt processing. This prioritizes each device that requests an interrupt, and when interrupt request signals from multiple devices are input at the same time, the interrupt request from the device with a higher ranking is prioritized and the interrupt permission signal is sent. is generated.

As shown in FIG. 4, such a priority control device 1 sets the priorities of, for example, four devices such that the first device is placed first, the second device is placed second, and the third device is placed first. is placed in the third place, and the fourth device is placed in the fourth place, and the request signals R1~ from these devices are
R4 is input to the decoder 4t04, which is composed of the first to third inverters 2, 3.4 and the first to third AND gates 5, 6.7, to generate permission signals P1 to P as shown in the table below.
4 is generated.

In this table, request signals R1 to R4 are "1" when a request is being generated, and "0" when a request is not being generated.
'' is displayed, and the permission signals P1 to P4 are displayed as ``1'' when interrupts are permitted, and ``0'' when interrupts are not permitted.

[Problem that the invention seeks to solve]

By the way, in the conventional priority control device as mentioned above, priority control is performed by hardware consisting of decoders, AND gates, etc., so as the number of devices whose priorities need to be controlled increases, the priority There is a problem that the structure of the ranking control device is complicated and large. In addition, when such a conventional priority control device is adopted,
- Since the priority of devices is unchanged in the system, if a request from a device with a high priority is made continuously, a request from a device with a low priority will always be denied, and the processing of such a device will be delayed. It happens.

Furthermore, in order to change the priorities of other devices with the same hardware configuration according to the purpose, the priority control device must have a different configuration than the one described above, which is complicated. It is.

(Means for solving the problem) In the present invention, as shown in FIG. permission signal P based on the priority order
The priority control device 10 that generates the above includes a memory 11 that outputs a permission signal based on the request state of the device and the state of the previous permission signal, and a holding means that holds the output of this memory 11 and outputs it to the memory 11 next time. 12.

(Operation) According to the present invention, since the device priorities are stored in the memory, even if the number of devices whose priorities should be controlled increases, as long as the amount of priority setting information is within the memory capacity,
There is no need to increase the hardware configuration. Further, according to the present invention, the memory stores the priority based on the state of the request signal of the device and the state of the previous permission signal, and the holding means holds the output of the memory and outputs it to the memory next time. By prohibiting the same device from consecutively specifying the memory contents, a device with a high priority will not be monopolized and the processing of a device with a low priority will not be delayed.
To change the priority of a device, simply install memory with different contents.

〔Example〕

Embodiments of the priority control device according to the present invention will be described below with reference to the drawings.

FIGS. 2 and 3 show an embodiment of the priority control device according to the present invention.

In this embodiment, the priority control device 10 controls the interrupt priorities of four devices in the same manner as before.
As shown in the figure, a memory 11 has eight input terminals AO to A7 and four output terminals DO to D3 that output permission signals based on the input signals, and the output of this memory is set to latch timing. It consists of a latch circuit 12 as a holding means for latching based on the data.

Of the input terminals AO to A7 of this memory 11, four input terminals AO to A3 are connected to interrupt request signals R1 to R of the four devices.
4 is input, and the previous permission signals P' 1 to P' latched by the latch circuit 12 are input to the other input terminals A4 to A7.
4 is input.

The memory 11 is provided with a table storing output signals corresponding to input signals. As shown in FIG. 3, this table is configured to output terminals corresponding to the input patterns of the request signals R1 to R3 to the input terminals AO to A7 and the previous permission signals P'1 to P'3 output by the latch circuit. Permission signals P1 to P to be output to DO to D3
It stores the contents of 4.

In this embodiment, in principle, the priority order of the devices is such that the first device is given first priority, and then the second device, third device, fourth device, etc.
device and lower its priority. In this embodiment, even a device with a high priority level is prevented from continuously interrupting, thereby preventing lower-level devices from being unable to interrupt. That is, for example, assume that the first device and the second device issue interrupt request signals at the same time. At this time, assuming that the system has just been started up, the latch circuit outputs a signal "0" to the input terminals A4 to A7 of the memory. Among the devices, the first device and the second device generate an interrupt request signal “1”, and the third and fourth devices generate a signal rOJ. Therefore, the memory input terminal AO~
r11000000J is input to A7 in order, and in response to this input signal, rlo is input to output terminals DO to D3 in order.
The oOJ signal is output (indicated by the original number a in Figure 3).
, an interrupt enable signal "1" is output to the first device, an interrupt disable signal "0" is output to the other devices, and the latch circuit 12 latches this signal. And then again. 1st
Assume that the device 1 and the second device request an interrupt. Then, the interrupt request signal "1" is input to the input terminals AO and A1 of the memory. The input terminals A4 to A7 are the permission signals P'1 to P''4 outputted by the memory last time, that is, rloooo.
J is input, and rlloo is input to input terminals AO to A7 in order.
roooJ is input, and rolooJ is output to the output terminals DO to D3 of the memory in order (as shown in FIG. 3), no interrupt permission signal is output to the first device, and the second
An interrupt permission signal "1" is output to the device.

In the table shown in FIG. 3, A4 has "1", and A5 below it has "1". A6. A7 indicates a case where "0" is input, that is, a case where interrupt permission was given to the first device last time, and in this case, the interrupt request of the first device and the interrupt request of the other device are If there is a conflict with an interrupt request, interrupt permission is given to another device, and if there is a conflict with an interrupt request, the interrupt permission is generated in accordance with the priority order. In this figure, only the case where interrupt permission was given to the first device last time is displayed, but information about the case where interrupt permission was given to other devices last time is also stored in the same way. It is.

In this way, this embodiment uses the contents of the memory 11, including the priority order and the result of the previous interrupt permission signal latched by the latch circuit 12, to determine the device that should generate the interrupt permission signal. Therefore, even if a device with a higher priority order continuously generates an interrupt request, the device with a lower priority order can also generate an interrupt permission signal, and the device with a lower priority order can receive an interrupt request. In addition to eliminating processing delays, even in systems with the same hardware configuration, the priority order of each device can be changed simply by replacing the memory with a memory that stores different table contents.

In the Naoki embodiment, there are 4 devices whose priorities are controlled.
Although it has been explained as a stand, it is of course better if there are more. Further, although the above embodiment has been described with respect to the case where priority control of interrupts is executed as a priority control device, the present invention is capable of controlling not only interrupts but all priorities. Further, in the above embodiment, the contents of the memory are configured as described above, but in the present invention, the priority order of the devices is uniformly set in ascending order of numbers.
It goes without saying that this ranking can be set arbitrarily.

〔Effect of the invention〕

As explained above, according to the present invention, the priority control device includes a memory that stores priority information based on the state of the request signal of the device and the state of the previous permission signal and outputs the permission signal; A holding means is provided to hold the permission signal and output it to the memory next time, and the device that generates the permission signal is determined from the priority order in the memory and the result of the previous permission signal held by the holding means. Therefore, even if a device with a higher priority order continuously issues interrupt requests, a permission signal can also be generated to the device with a lower priority order, and the processing of the device with a lower priority order will not be delayed. Another advantage is that even in systems having the same hardware configuration, the priority order of each device can be changed arbitrarily by simply replacing the memory with a memory that stores different table contents.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the priority control device according to the present invention, and FIG.
FIG. 4 is a block diagram showing the conventional priority control device. 10...Priority control device 11...Memory 12...Holding means (latch circuit) Patent applicant Fujitsu Limited-2 Agent Patent attorney Teiji Igeta 2.゛ゝ1...
・l ・-2, / 1 Dohon 9: B-th repulsion (! Hatake Ii1 figure f7 tatll's rush to Ii 1 Figure 2

Claims (1)

[Scope of Claims] In a priority control device (10) that generates permission signals according to predetermined priorities when request signals from multiple devices conflict, the state of the request signal of the device and the previous permission are provided. A memory (11) that outputs a permission signal based on priority based on the signal state.
), and a holding means (12) for holding the permission signal of this memory and outputting it to the memory next time.