JPS63231661A - Precedence controller - Google Patents

Precedence controller

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Publication number
JPS63231661A
JPS63231661A JP6606887A JP6606887A JPS63231661A JP S63231661 A JPS63231661 A JP S63231661A JP 6606887 A JP6606887 A JP 6606887A JP 6606887 A JP6606887 A JP 6606887A JP S63231661 A JPS63231661 A JP S63231661A
Authority
JP
Japan
Prior art keywords
memory
priority
permission signal
devices
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6606887A
Other languages
Japanese (ja)
Inventor
Makoto Nakamoto
誠 中本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6606887A priority Critical patent/JPS63231661A/en
Publication of JPS63231661A publication Critical patent/JPS63231661A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To arbitrarily change the priority level of each device by providing a memory, which outputs a permission signal based on the state of the request signal of the device and the state of the preceding permission signal, and a holding means which holds the permission signal from the memory and outputs it to the memory at the next time. CONSTITUTION:A memory 11 which outputs the permission signal based on the request state of the device and the state of the preceding permission signal and a holding means 12 which holds the output of the memory 11 and outputs it to the memory 11 at the next time are provided. Since the priority level of the device is stored in the memory 11, it is unnecessary to extend the hardware constitution in case of the increase of the number of devices, whose priority levels should be controlled, if the setting information volume of priority level is equal to or smaller than the capacity of the memory 11. If contents of the memory 11 are so set that continuous designation of the same device is inhibited, processings of devices having lower priority levels are prevented from being stagnated by monopolization of the device having a higher priority level; and in case of the change of priority levels of devices, it is sufficient if a memory having different contents is attached.

Description

【発明の詳細な説明】 〔概要〕 本発明は複数装置の要求信号が競合したとき許可信号を
発生するに際し、特定の装置に処理が偏ることを防止で
きるようにし、また同一のハードウェア構成で異った優
先順位を容易に割り付けることができるようにするため
、優先順位制御装置に装置の要求信号の状態及び前回の
許可信号の状態に基づいた許可信号を出力するメモリと
、このメモリの許可信号を保持して次回においてメモリ
に出力する保持手段とを設けるようにしたものである。
[Detailed Description of the Invention] [Summary] The present invention makes it possible to prevent processing from being biased toward a specific device when generating a permission signal when request signals from multiple devices conflict, and also to prevent processing from being biased toward a specific device. In order to be able to easily assign different priorities, there is provided a memory for outputting a grant signal to the priority controller based on the state of the request signal of the device and the state of the previous grant signal, and a grant of this memory. A holding means for holding the signal and outputting it to the memory next time is provided.

(産業上の利用分野) 本発明は、優先順位制御装置に係り、特に複数の装置か
らの要求が競合した際、予め定めておいた優先順位に従
って許可信号を発生する優先順位制御装置に関するもの
である。
(Industrial Application Field) The present invention relates to a priority control device, and particularly to a priority control device that generates a permission signal according to a predetermined priority when requests from multiple devices conflict. be.

〔従来の技術〕[Conventional technology]

従来優先順位制御装置として、割込処理の優先順位を制
御する装置として次のようなものがある。これは、割込
を要求する各装置に順位付けをして、同時に複数の装置
の割込要求信号が入力した場合には、順位が上位の装置
の割込要求を優先して割込許可信号を発生するようにし
たものである。
Conventional priority control devices include the following devices that control the priority of interrupt processing. This prioritizes each device that requests an interrupt, and when interrupt request signals from multiple devices are input at the same time, the interrupt request from the device with a higher ranking is prioritized and the interrupt permission signal is sent. is generated.

このような優先順位制御装置1は、第4図に示すように
、例えば4台の装置の優先順位を、第1の装置を第1位
、第2の装置を第2位、第3の装置を第3位、第4の装
置を第4位として、これらの装置からの要求信号R1〜
R4を第1乃至第3のインバータ2,3.4及び第1乃
至第3のアンドゲート5,6.7で構成した4t04の
デコーダに入力して下表に示すような許可信号P1〜P
4を発生するようにしたものである。
As shown in FIG. 4, such a priority control device 1 sets the priorities of, for example, four devices such that the first device is placed first, the second device is placed second, and the third device is placed first. is placed in the third place, and the fourth device is placed in the fourth place, and the request signals R1~ from these devices are
R4 is input to the decoder 4t04, which is composed of the first to third inverters 2, 3.4 and the first to third AND gates 5, 6.7, to generate permission signals P1 to P as shown in the table below.
4 is generated.

この表において、要求信号R1〜R4は要求を発生して
いる場合に「1」を、要求を発生していない場合に「0
」を表示し、また許可信号P1〜P4は割込許可の場合
「1」を、割込不許可の場合に「0」を表示している。
In this table, request signals R1 to R4 are "1" when a request is being generated, and "0" when a request is not being generated.
'' is displayed, and the permission signals P1 to P4 are displayed as ``1'' when interrupts are permitted, and ``0'' when interrupts are not permitted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上述のような従来の優先順位制御装置にあっ
ては、優先順位の制御をデコーダ、アンドゲート等から
なるハードウェアで行なっているため、優先順位を制御
すべき装置の台数が増加すると優先順位制御装置の構造
が複雑で大きなものとなるという問題がある。また、こ
のような従来の優先順位制御装置を採用した場合には、
−のシステムにおいて装置の優先順位は不変であるから
、優先順位の高い装置の要求が続けて行なわれたとする
と、優先順位の低い装置の要求は常に不許可となり、そ
のような装置の処理が滞ることとなる。
By the way, in the conventional priority control device as mentioned above, priority control is performed by hardware consisting of decoders, AND gates, etc., so as the number of devices whose priorities need to be controlled increases, the priority There is a problem that the structure of the ranking control device is complicated and large. In addition, when such a conventional priority control device is adopted,
- Since the priority of devices is unchanged in the system, if a request from a device with a high priority is made continuously, a request from a device with a low priority will always be denied, and the processing of such a device will be delayed. It happens.

更に、同一のハードウェア構成を有する他の装置におい
て装置の優先順位を目的にあわせて変更したものとする
には、優先順位制御装置を上述のものとは異った構成と
しなければならず煩雑である。
Furthermore, in order to change the priorities of other devices with the same hardware configuration according to the purpose, the priority control device must have a different configuration than the one described above, which is complicated. It is.

(問題点を解決するための手段) 本発明において、上記の問題点を解決するための手段は
、第1図に示すように、複数の装置の要求信号Rが競合
した際、予め定めておいた優先順位に基づき許可信号P
を発生する優先順位制御装置10において、装置の要求
状態及び前回の許可信号の状態に基づく許可信号を出力
するメモリ11と、このメモリ11の出力を保持して次
回においてメモリ11に出力する保持手段12とを設け
るようにしたことである。
(Means for solving the problem) In the present invention, as shown in FIG. permission signal P based on the priority order
The priority control device 10 that generates the above includes a memory 11 that outputs a permission signal based on the request state of the device and the state of the previous permission signal, and a holding means that holds the output of this memory 11 and outputs it to the memory 11 next time. 12.

(作用) 本発明によれば、装置の優先順位はメモリに格納してい
るから、優先順位を制御すべき装置が増加したとしても
、優先順位の設定情報量がメモリの容量以内であれば、
ハードウェア構成を増加する必要はない。また本発明に
よればメモリは装置の要求信号の状態及び前回の許可信
号の状態に基づいた優先順位を格納しており、また保持
手段はメモリの出力を保持して次回においてメモリに出
力するから、メモリの内容を同一装置の連続指定を禁止
するようにしておけば、優先順位の高い装置が独占して
、優先順位の低い装置の処理が滞ることはなくなる他、
装置の優先順位を変更するのには異った内容のメモリを
取り付けるだけでよい。
(Operation) According to the present invention, since the device priorities are stored in the memory, even if the number of devices whose priorities should be controlled increases, as long as the amount of priority setting information is within the memory capacity,
There is no need to increase the hardware configuration. Further, according to the present invention, the memory stores the priority based on the state of the request signal of the device and the state of the previous permission signal, and the holding means holds the output of the memory and outputs it to the memory next time. By prohibiting the same device from consecutively specifying the memory contents, a device with a high priority will not be monopolized and the processing of a device with a low priority will not be delayed.
To change the priority of a device, simply install memory with different contents.

〔実施例〕〔Example〕

以下本発明に係る優先順位制御装置の実施例を図面に基
づいて説明する。
Embodiments of the priority control device according to the present invention will be described below with reference to the drawings.

第2図及び第3図は本発明に係る優先順位制御装置の実
施例を示すものである。
FIGS. 2 and 3 show an embodiment of the priority control device according to the present invention.

本実施例において、優先順位制御装置10は、従来と同
様に4台の装置の割込優先順位を制御するもので、第2
図に示すように、8木の入力端子AO〜A7を有しこの
入力信号に基づいて許可信号を出力する4本の出力端子
DO〜D3を有するメモリ11と、このメモリの出力を
ラッチタイミングに基づきラッチする保持手段としての
ラッチ回路12とからなる。
In this embodiment, the priority control device 10 controls the interrupt priorities of four devices in the same manner as before.
As shown in the figure, a memory 11 has eight input terminals AO to A7 and four output terminals DO to D3 that output permission signals based on the input signals, and the output of this memory is set to latch timing. It consists of a latch circuit 12 as a holding means for latching based on the data.

このメモリ11の入力端子AO〜A7のうち4つの入力
端子AO−A3には4台の装置の割込要求信号R1〜R
4が入力され、他の入力端子A4〜A7にはラッチ回路
12がラッチしている前回の許可信号P’  1〜P’
 4が入力されるようにしている。
Of the input terminals AO to A7 of this memory 11, four input terminals AO to A3 are connected to interrupt request signals R1 to R of the four devices.
4 is input, and the previous permission signals P' 1 to P' latched by the latch circuit 12 are input to the other input terminals A4 to A7.
4 is input.

そして、上記のメモリ11には入力信号に対応する出力
信号を格納したテーブルを設けるようにしている。この
テーブルは第3図に示すように、入力端子AO〜A7へ
の要求信号R1〜R3及びラッチ回路が出力する前回の
許可信号P’  1〜P’ 3の入カバターンに対応し
て、出力端子DO〜D3に出力すべき許可信号P1〜P
4の内容を記憶しているものである。
The memory 11 is provided with a table storing output signals corresponding to input signals. As shown in FIG. 3, this table is configured to output terminals corresponding to the input patterns of the request signals R1 to R3 to the input terminals AO to A7 and the previous permission signals P'1 to P'3 output by the latch circuit. Permission signals P1 to P to be output to DO to D3
It stores the contents of 4.

本実施例において、装置の優先順位は原則的には第1の
装置を第1位とし、以下第2の装置、第3の装置、第4
の装置と優先順位を下げるようにしている。そして本実
施例において、優先順位が高い装置であっても、連続し
て割込を行なえないようにして、下位装置の割込が出来
なくなるのを防止している。即ち、例えば第1の装置と
第2の装置が同時に割込要求信号を出したとする。この
ときシステムを立ち上げたばかりであるとすると、ラッ
チ回路はメモリの入力端子A4〜A7に信号「0」を出
力する。そして、各装置のうち第1の装置及び第2の装
置は割込要求信号「1」を、第3及゛び第4の装置は信
号rOJを発生する。従って、メモリの入力端子AO〜
A7には順にr 11000000Jが入力され、この
入力信号に対応して出力端DO〜D3には、順にrlo
oOJの信号が出力され(第3図B生得号aで示した)
、第1の装置に割込許可信号「1」が出力され、その他
の装置には割込不許可信号「0」が出力され、ラッチ回
路12はこの信号をラッチする。そして次にまた。第1
の装置と第2の装置が割込要求をしたとする。するとメ
モリの入力端子AO及びA1には割込要求信号「1」が
入力される。そして入力端子A4〜A7には前回にメモ
リが出力した許可信号P′1〜P”4、即ちrlooo
Jが入力され、入力端子AO〜A7には順にrlloo
loooJが入力され、メモリの出力端子DO〜D3に
は順にrolooJが出力され(第3図生得号すで示し
た)、第1の装置には割込許可信号は出力されず、第2
の装置に割込許可信号「1」が出力される。
In this embodiment, in principle, the priority order of the devices is such that the first device is given first priority, and then the second device, third device, fourth device, etc.
device and lower its priority. In this embodiment, even a device with a high priority level is prevented from continuously interrupting, thereby preventing lower-level devices from being unable to interrupt. That is, for example, assume that the first device and the second device issue interrupt request signals at the same time. At this time, assuming that the system has just been started up, the latch circuit outputs a signal "0" to the input terminals A4 to A7 of the memory. Among the devices, the first device and the second device generate an interrupt request signal “1”, and the third and fourth devices generate a signal rOJ. Therefore, the memory input terminal AO~
r11000000J is input to A7 in order, and in response to this input signal, rlo is input to output terminals DO to D3 in order.
The oOJ signal is output (indicated by the original number a in Figure 3).
, an interrupt enable signal "1" is output to the first device, an interrupt disable signal "0" is output to the other devices, and the latch circuit 12 latches this signal. And then again. 1st
Assume that the device 1 and the second device request an interrupt. Then, the interrupt request signal "1" is input to the input terminals AO and A1 of the memory. The input terminals A4 to A7 are the permission signals P'1 to P''4 outputted by the memory last time, that is, rloooo.
J is input, and rlloo is input to input terminals AO to A7 in order.
roooJ is input, and rolooJ is output to the output terminals DO to D3 of the memory in order (as shown in FIG. 3), no interrupt permission signal is output to the first device, and the second
An interrupt permission signal "1" is output to the device.

第3図に示すテーブルにはA4に「1」が、それ以下の
A5.A6.A7は「0」が入力されている場合、即ち
、前回において第1の装置に割込許可を与えた場合を示
しており、この場合には第1の装置の割込要求と他の装
置の割込要求とが競合した場合には、他の装置に割込許
可を与えると共に、さらに割込要求が競合している場合
には優先順位通りに割込許可を発生するようにしている
。尚、この図においては前回に第1の装置に割込許可を
与えた場合のみ表示したが、前回に他の装置に割込許可
を与えた場合についての情輻も同様に格納しているもの
である。
In the table shown in FIG. 3, A4 has "1", and A5 below it has "1". A6. A7 indicates a case where "0" is input, that is, a case where interrupt permission was given to the first device last time, and in this case, the interrupt request of the first device and the interrupt request of the other device are If there is a conflict with an interrupt request, interrupt permission is given to another device, and if there is a conflict with an interrupt request, the interrupt permission is generated in accordance with the priority order. In this figure, only the case where interrupt permission was given to the first device last time is displayed, but information about the case where interrupt permission was given to other devices last time is also stored in the same way. It is.

このようにして本実施例は、メモリ11の内容を、優先
順位とラッチ回路12がラッチしている前回の割込許可
信号の結果をも含めて、割込許可信号を発生ずべき装置
を決定するものとしているから、優先順が上位の装置が
割込要求を続けて発生したとしても、優先順位が下位の
装置にも割込許可信号を発生することができ、優先順位
が下位の装置の処理が滞ることはなくなる他、同一のハ
ードウェア構成を有するシステムであっても格納したテ
ーブル内容が異るメモリと交換するだけで、各装置の優
先順位を換えることができるものとしている。
In this way, this embodiment uses the contents of the memory 11, including the priority order and the result of the previous interrupt permission signal latched by the latch circuit 12, to determine the device that should generate the interrupt permission signal. Therefore, even if a device with a higher priority order continuously generates an interrupt request, the device with a lower priority order can also generate an interrupt permission signal, and the device with a lower priority order can receive an interrupt request. In addition to eliminating processing delays, even in systems with the same hardware configuration, the priority order of each device can be changed simply by replacing the memory with a memory that stores different table contents.

尚木実施例においては、優先順位を制御される装置を4
台として説明したがこれはもっと多くとも少なくともよ
いのは勿論である。また、上記の実施例は優先順位制御
装置として割込の優先順位制御を実行する場合について
説明したが、本発明は割込に限らず全ての優先順位の制
御を行なう事ができる。さらに上記実施例においてはメ
モリの内容は上記のように構成したが本発明においては
装置の優先順位は番号の小さい順に一律に設定したが、
この順位については任意に設定できることは言うまでも
ない。
In the Naoki embodiment, there are 4 devices whose priorities are controlled.
Although it has been explained as a stand, it is of course better if there are more. Further, although the above embodiment has been described with respect to the case where priority control of interrupts is executed as a priority control device, the present invention is capable of controlling not only interrupts but all priorities. Further, in the above embodiment, the contents of the memory are configured as described above, but in the present invention, the priority order of the devices is uniformly set in ascending order of numbers.
It goes without saying that this ranking can be set arbitrarily.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、優先順位制御装
置に装置の要求信号の状態及び前回の許可信号の状態に
基づいた優先順位情報を格納し許可信号を出力するメモ
リと、このメモリからの許可信号を保持して次回におい
てメモリに出力する保持手段とを設け、メモリに優先順
位と保持手段が保持している前回の許可信号の結果から
許可信号を発生する装置を決定するものとしているから
、優先順が上位の装置が割込要求を続けて発生したとし
ても、優先順位が下位の装置にも許可信号を発生するこ
とができ、優先順位が下位の装置の処理が滞ることはな
くなる他、同一のハードウェア構成を有するシステムで
あっても格納したテーブル内容が異るメモリと交換する
だけで、各装置の優先順位を任意に変えることができる
という効果を奏する。
As explained above, according to the present invention, the priority control device includes a memory that stores priority information based on the state of the request signal of the device and the state of the previous permission signal and outputs the permission signal; A holding means is provided to hold the permission signal and output it to the memory next time, and the device that generates the permission signal is determined from the priority order in the memory and the result of the previous permission signal held by the holding means. Therefore, even if a device with a higher priority order continuously issues interrupt requests, a permission signal can also be generated to the device with a lower priority order, and the processing of the device with a lower priority order will not be delayed. Another advantage is that even in systems having the same hardware configuration, the priority order of each device can be changed arbitrarily by simply replacing the memory with a memory that stores different table contents.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理図、第2図は本発明にかかる優先
順位制御装置の実施例を示すブロック図、第3図は第2
図に示した優先順位制御装置のメモリに格納したテーブ
ルの内容を示す図、第4図は従来の優先順位制御装置を
示すブロック図である。 10・・・優先順位制御装置 11・・・メモリ 12・・・保持手段(ラッチ回路) 特許出願人  富士通株式会社−2 代 理 人  弁理士 井桁 貞二°゛2.゛ゝ1・・
 ・l ・−二、/ 1ど 本9:B目の斥(!畠 Ii1図 f7tatllの突洸伊1 第2図
FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the priority control device according to the present invention, and FIG.
FIG. 4 is a block diagram showing the conventional priority control device. 10...Priority control device 11...Memory 12...Holding means (latch circuit) Patent applicant Fujitsu Limited-2 Agent Patent attorney Teiji Igeta 2.゛ゝ1...
・l ・-2, / 1 Dohon 9: B-th repulsion (! Hatake Ii1 figure f7 tatll's rush to Ii 1 Figure 2

Claims (1)

【特許請求の範囲】 複数の装置からの要求信号が競合した際、予め定めてお
いた優先順位に従って許可信号を発生する優先順位制御
装置(10)において、 装置の要求信号の状態及び前回の許可信号の状態に基づ
いた優先順位に基づく許可信号を出力するメモリ(11
)と、 このメモリの許可信号を保持して次回においてメモリに
出力する保持手段(12)とを有することを特徴とする
優先順位制御装置。
[Scope of Claims] In a priority control device (10) that generates permission signals according to predetermined priorities when request signals from multiple devices conflict, the state of the request signal of the device and the previous permission are provided. A memory (11) that outputs a permission signal based on priority based on the signal state.
), and a holding means (12) for holding the permission signal of this memory and outputting it to the memory next time.
JP6606887A 1987-03-20 1987-03-20 Precedence controller Pending JPS63231661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6606887A JPS63231661A (en) 1987-03-20 1987-03-20 Precedence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6606887A JPS63231661A (en) 1987-03-20 1987-03-20 Precedence controller

Publications (1)

Publication Number Publication Date
JPS63231661A true JPS63231661A (en) 1988-09-27

Family

ID=13305164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6606887A Pending JPS63231661A (en) 1987-03-20 1987-03-20 Precedence controller

Country Status (1)

Country Link
JP (1) JPS63231661A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02219156A (en) * 1988-12-21 1990-08-31 Internatl Business Mach Corp <Ibm> Access priority determining apparatus and bus arbiter
JPH04243460A (en) * 1991-01-18 1992-08-31 Sharp Corp Data transmission device
US5247294A (en) * 1990-06-14 1993-09-21 Fujitsu Limited Signal select control circuit and signal select circuit using the same
JPH06332841A (en) * 1993-05-17 1994-12-02 American Teleph & Telegr Co <Att> System for adjusting assignment requirement and its method
US6882695B1 (en) 1997-08-28 2005-04-19 Sharp Kabushiki Kaisha Data transmission line used continuously connected in plurality of stages in asynchronous system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02219156A (en) * 1988-12-21 1990-08-31 Internatl Business Mach Corp <Ibm> Access priority determining apparatus and bus arbiter
US5247294A (en) * 1990-06-14 1993-09-21 Fujitsu Limited Signal select control circuit and signal select circuit using the same
JPH04243460A (en) * 1991-01-18 1992-08-31 Sharp Corp Data transmission device
JPH06332841A (en) * 1993-05-17 1994-12-02 American Teleph & Telegr Co <Att> System for adjusting assignment requirement and its method
US6882695B1 (en) 1997-08-28 2005-04-19 Sharp Kabushiki Kaisha Data transmission line used continuously connected in plurality of stages in asynchronous system

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