JPH0311436A - Storage access control device - Google Patents

Abstract

PURPOSE:To eliminate the memory access request processing of unbalanced load by preferentially processing the memory access request from the input/ output processing device of low speed according to the number of queuing of the memory access request. CONSTITUTION:When a write address counter 2 indicates '14' as a write address, and a read address counter 3 indicates '6' as a read address, in a preferential request indicating circuit 4, it is detected that the number of the memory access requests in waiting from the input/output processing device reaches '8' based on both these addresses. Therefore, a preferential processing indication is generated from a preferential processing indication signal 14, and in a request acceptance circuit 5, the memory access request 15 from the input/ output processing device is sent to output 18 in response to this indication. Accordingly, in a request processing circuit 6, an access request code 21 in the read address '6' in a request storage buffer 1 is decoded, and the memory access request in waiting from the input/output processing device is derived to a main storage device 7.

Description

TECHNICAL FIELD The present invention relates to a storage access control device, and more particularly to a storage access control device that receives memory access requests from a plurality of processing devices and processes them while arbitrating them.

BACKGROUND OF THE INVENTION In recent years, the demand for supercomputers for scientific and technical calculations has been increasing significantly. The field handled by this supercomputer is a field in which it is necessary to process large-scale data, and this data is often expanded on the main memory and accessed frequently.

In a vector processing device, which is a supercomputer that processes vector data, in order to access a series of vector data to the main memory, the load of these main memory access requests (referred to as memory access requests) is high. In addition, even when the load of memory access requests from low-speed input/output processing devices increases, fixed contention control is performed to process the requests from the input/output processing devices.

In such conventional methods, memory access requests from the vector processing apparatus are often processed with priority in order to improve the memory access request processing performance of the vector processing apparatus. Therefore, even if memory access requests from the input/output processing device increase, the requests from the input/output processing device are processed with low performance, resulting in a reduction in throughput.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the above-mentioned conventional methods, and its purpose is to improve memory access throughput by avoiding biased memory access request processing. iXJ storage access control device! It is about providing.

Structure of the Invention According to the present invention, there is provided a storage access control device that arbitrates each memory access request from a first and second processing device, and is capable of storing a plurality of memory access requests from the first processing device. access request storage means; address control means for generating and controlling write and read addresses to the access request storage means; The number of memory access requests of the first processing device is calculated, and if the calculation result reaches a preset value, the number of memory access requests of the first processing device is calculated in response to the memory access request of the second processing device. There is obtained a storage access control device characterized in that it includes a priority processing means for processing access requests with priority.

Embodiments Below, embodiments of the present invention will be described in detail with reference to the drawings.

The figure is a block diagram of an embodiment of the invention. In the figure,
The request storage buffer 1 is a buffer that stores a plurality of memory access requests 11 from an input/output processing device (not shown) to the main storage device 7, and the request code of the access request is stored as pending processing. It is assumed that this buffer 1 is a memory buffer that can be read and written at the same time.

The write address counter 2 generates the write address 12 of the request storage buffer and the initial ICII value “
Each time a memory access request is given from the input/output processing device via the signal line 11, the counter is
It is a 4-bit counter that is incremented by "15" and then returns to the initial value "0". This write address 12 is the address where the memory access request sent from the input/output processing device is stored. This will indicate the address that should be addressed.

The read address counter 3 generates the read address 13 of the request storage buffer 1, and is a counter that indicates the address of the memory access request stored in the request storage buffer 1 and to be processed first. The count is sequentially incremented in response to an input/output processing unit memory access request acceptance signal supplied via the signal line 19.

The priority request instruction circuit 4 calculates the number of memory access requests stored in the request storage buffer 1 and waiting to be processed based on the write address 12 and the read address 13, and when this number reaches a preset value, the priority request is given. An instruction signal 14 is generated to cause the waiting memory access request to be processed.

It also has a function of sending a memory access request signal from the input/output processing device to the request receiving circuit 5 via the signal line 15 if there is even one memory access request waiting to be processed. .

The priority request instructing circuit 4 also has a mechanism for generating a memory access request sending prohibition signal 16 when the waiting memory access request is stored in the request storage buffer 1 until its capacity is full, and sending this to the input/output processing device. It also has

If the priority processing instruction signal 14 instructs priority processing, the request receiving circuit 5 selects and outputs the memory access request 15 from the input/output processing device on the signal line 18; Accepts and outputs the supplied access request.

When a memory access request 17 from a vector processing device is accepted, a memory access request acceptance signal 20 is sent to the vector processing device, and when a memory access request 15 from an input/output processing device is accepted, a memory access request acceptance signal 20 is sent to the vector processing device. , a memory access request acceptance signal 19 is sent to the read address counter 3, and the contents of the counter 3 are counted up by "1".

The request processing circuit 6 selects the access request code according to the memory access request 17 from the vector processing device and the access request code 21 of the input/output processing device from the request buffer 1 according to the output 18 from the request reception circuit 5. This selection output 22 is decoded in the request processing circuit 6 and sent as an access request to the main storage device 7 via the signal line 22.

In this configuration, it is assumed that the request storage buffer 1 can store 16 memory access request codes as waiting, and the write address counter 2 has a value from "0" to "15".
Furthermore, when the number of memory access requests waiting to be processed in the request storage buffer 1 reaches "8" in the priority request instruction circuit 4, the priority processing instruction signal 14 is generated. .

In this case, the write address counter 2 now indicates "14" as the write address, and the read address counter 3
indicates "6" as the read address, the priority request instruction circuit 4 determines that the memory access request from the waiting input/output processing device is "8" based on these two addresses.
is detected.

Therefore, a priority processing instruction is generated from the priority processing instruction signal 14, and the request reception circuit 5 sends a memory access request 15 from the input/output processing device to the output 18 in response to this instruction. Therefore, in the request processing circuit 6, the access request code 21 at the read address "62" in the request storage buffer 1 is decoded, and the waiting memory access request from the input/output processing device is derived to the main storage device 7. It will be done.

In the above embodiment, memory access requests from an input/output processing device and a vector processing device are considered, but there are also cases where low-speed and high-speed processing devices commonly use and access main memory. It is clear that the method is widely applicable to the following.

Effects of the Invention As described above, according to the present invention, memory access requests from low-speed input/output processing devices are prioritized depending on the number of queued memory access requests, so that memory access requests with uneven loads are handled. This has the effect of eliminating processing and achieving a well-balanced memory access throughput in terms of the system.

BRIEF DESCRIPTION OF THE DRAWINGS The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 1...Request storage buffer 2...Write address counter 3...
Read address counter 4...Priority request instruction circuit 5...Request acceptance circuit 6...Request processing circuit 7...Main memory

Claims (1)

[Claims] (1) A storage access control device that arbitrates each memory access request from a first and second processing device, the access request storage means being capable of storing a plurality of memory access requests from the first processing device; , an address control means for generating and controlling write and read addresses to the access request storage means, and a memory of the first processing device waiting for processing, which is stored in the access request storage means based on the write and read addresses. Calculate the number of access requests, and if the calculation result reaches a preset value, give priority to the memory access request of the first processing device over the memory access request of the second processing device. A storage access control device comprising: priority processing means for processing.