JPS63231558A - Central processing unit - Google Patents

Abstract

PURPOSE:To shorten the bus use waiting time of a peripheral device by allowing a central processing unit (CPU) to stop its executing processing at the time of asynchronously inputting a bus use request from the peripheral device and to instantaneously permit the bus use, and after the end of the bus use request from the peripheral device, to retry the stopped processing from its initial stage. CONSTITUTION:At the time of inputting a bus use request signal (hold request signal HLDRQ) to an HLDRQ input terminal, the CPU immediately invalidates its executing processing. An address bus 12, a data bus 10 and a command bus 11 connected to the CPU are turned to high impedance and separated from the CPU and the CPU itself is turned to a holding state. The CPU outputs a hold acknowledge signal HLDAK to inform the open of these buses to the peripheral device, and the HLDRQ is disconnected, generates a retry cycle for executing the invalidated processing again. Consequently, the peripheral device can use the bus after at least one-clock waiting time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a central processing unit, and more particularly to bus control of a central processing unit connected to external peripheral devices and memory using a common bus.

(Prior Art) A conventional central processing unit has an input terminal for a hold request signal generated from a peripheral device as a means of opening a bus to a peripheral device, and a hold acknowledge signal indicating that the central processing unit has received the hold request signal. If the central processing unit is executing processing using the bus when the hold request signal is input, the peripheral device is provided with an output terminal for outputting the signal to the peripheral device until the processing cycle is completed. After the processing cycle is completed, the central processing unit enters the hold state and outputs a hold acknowledge signal to hand over the bus to the peripheral device.

(Problems to be Solved by the Invention) In the conventional central processing unit described above, a waiting time of up to one bus cycle is required from inputting a hold request signal to issuing a hold acknowledge signal, which requires peripheral devices to operate at high speed. When this is required, a waiting time of one pass cycle cannot be tolerated, and a bus control method using handshaking such as hold request and hold acknowledge cannot be used.

(Means for Solving the Problem) In order to solve this drawback, the central processing unit of the present invention has an input terminal for a bus use request signal (hold request signal), and the bus use request signal is input to this input terminal. When input, it immediately disables the processing being executed, sets the address bus, data bus, and command bus connected to the central processing unit to high impedance, disconnects these buses from the central processing unit, and disconnects the central processing unit from the central processing unit. When in the hold state, it immediately outputs a hold acknowledge signal to notify peripheral devices that the bus has been released, and when the bus use request signal is cut off, it re-executes the invalidated process or generates a try cycle.

(Example) Next, an example of the present invention will be described with reference to drawings and timing charts.

Figure 1 shows the central processing unit (hereinafter referred to as CPU) of the present invention.
FIG. 2 is a block diagram of one embodiment of FIG. It has a CPU bus control unit (BCU) 2 and an execution unit (EXU') 3. The BCU 2 fetches programs and generates various bus timing signals for executing the programs, and the EXU 3 interprets the programs transmitted from the BCU 2 and performs corresponding execution processing. Below, EXU
3 and the inside of BCU2 will be explained.

In the EXU 3, instructions input through the internal data bus 10 are interpreted by the instruction decoder 7 and executed by the execution unit 8.
A control signal for selecting and specifying the content to be executed is sent to the execution unit 8 via the execution control signal line 31.

When the EXU 3 accesses the external bus of the CPU through the BCU 2, it instructs the address generator 9 to generate an execution address through the control line 13.

Address generator 9 generates an execution address based on this and sends the execution address to address buffer 4 via internal execution address bus 12. On the other hand, the execution unit 8 is connected to the bus timing control unit 33 through the bus timing control line 11.
request to execute the necessary bus cycle.

Next, the BCU2 will be explained. The BCU 2 includes a bus timing control unit 33, an address buffer 4, and a data buffer/latch 5. The bus timing control unit 33 sends address/data to a signal line 37 during a bus cycle in order to control the address buffer 4 and the data buffer/latch 5. Outputs a buffer enable request signal, and also outputs a buffer enable request signal.
A bus cycle is generated by controlling the command timing signal of BCY of R and 27. In addition, if a bus cycle is being executed in response to a hold request signal input to the HLDR, Q terminal, wait until the bus cycle is completed.When the bus cycle is completed, a hold acknowledge signal for HLDRQ (hold request) is sent to the signal line 34. is output and the CPU enters the hold state. It also receives an internal retry signal 29 and generates a timing signal that invalidates the bus cycle currently being executed and causes the invalidated bus cycle to be re-executed in the next bus cycle. The internal retry request signal 29 is generated by ORing the retry request signal input to the IJ) retry request line 24 from outside the CPU and the sampled BUS OB signal 35 at the OR gate 16, and outputs either a retry request from the outside of the CPU or a retry request from the bus. When the use request signal 23 comes in, it becomes high level, and the bus timing control section 3
This is a request to try the current bus cycle for No. 3. The bus timing control unit 33 samples this retry request at the rising edge of the T4 cycle, invalidates the current bus cycle, and sets the next bus cycle as a retry bus cycle. The sampled BUSROB signal 35 is BUSROB
It is the Q output of the D-type flip-flop 19 which samples the bus use request signal inputted to CLK 23 at the rising edge of the clock signal inputted to CLK 30, and is set to high level active here. When the sampled BUSROB signal 35 becomes 2, the output of the OR gate 17 becomes high.The address buffer 4 and data buffer/latch 5 are made inactive through the address/data enable signal line 14, and the address line of AO-A15 is 20 and Do-
The data line 28 of D15 is set to high impedance. In addition, the sampled HUSH, OB signal 35 also serves as a command output enable request and a bus hold request to the bus timing control unit 33, and the W of 250R1) and 26
Disable the output of R,,270BCY mD@
% Make the WR line and BOY line high impedance.

Further, the bus cycle currently being executed is invalidated, and execution of the bus cycle is stopped until the sampled BU8ROB signal 35 becomes low level. Furthermore, sampled B
The USROB signal 35 is an input to the OR gate 18, and if the sampled BU8ROB signal 35 is high, it becomes H.
A high level is output as a hold acknowledge signal to the LDAK line 22 to notify peripheral devices that the command line and address/data bus have been set to zero impedance.

A signal line 37 is a signal output from the bus timing control unit 33 and is a signal that enables the address buffer 4 and data buffer/latch 5 during a bus cycle.

In addition, the input/output control line 36 includes a bus timing control section 33.
A control signal that determines the input/output direction of the data buffer/latch 5 during a bus cycle is output from.

FIG. 2 is a timing diagram of each signal when a bus use request signal enters the BU8ROB23 in BeO2 and when it is released. Reference numbers 50, 51, 52.

Each signal of 53.54, 55, 56.57 is 30 in Figure 1.
．． This corresponds to signals 27, 20, 25, 28, 23, 22, and 29. The period from T1 cycle 58 to T4 cycle is one bus cycle period for memory read, and BUSR
The OB signal 55 is at high level during the low level section of T2, and this is sampled at the rising edge of T3, and the BC
Make each RD output of Y51 and 520AO-A15 and 53 high impedance. Accordingly, data output from the peripheral device (DO-Di 5 at 54) is aborted.
1) 0-Di5 becomes high impedance. Also 5
HLDAK 6 notifies peripheral devices of the bus release.

The BU8ROB signal 55 is sampled at each rising edge of CLK50, and when a high level is sampled, the bus is immediately released to peripheral devices, and the bus timing control section 33 in FIG. Receive at rising edge and IJ in next bus cycle)
Prepares to generate a recycle and enters a hold state.

In FIG. 2, the 4-clock cycle section 59 is a hold cycle section, and the BOY section 51.

52 AO-A15, 53 RD, 54 DQ-Di5
becomes high impedance. 'HI-26 of 61 indicates a high impedance state. When the BU8ROB signal 55 becomes low level in the low level section of the third clock of 59, the low level is sampled at the rising edge of the fourth clock of 59, sets the HLDAK22 to low level, the bus timing control unit 33 releases the hold state, and then Execute a retry cycle. 60 four clock cycles are retry cycles.

As explained above, BUS) 1. When a bus use request signal is input to the OB terminal 23 asynchronously, the CLK terminal 30
At this time, the bus is immediately released to the peripheral devices, so the peripheral devices can use the bus with a wait time of only one clock at most.

(Embodiment 2) FIG. 3 is a block diagram of a second embodiment of the central processing unit of the present invention. In this embodiment, a multiplier 41 that doubles the clock 30 is provided between the CLK terminal and the D-type 7-lip/70-tub 19. Therefore, the sampled BU8ROB signal 35 is a D-type flip-flop 19 that samples the bus use request signal inputted to the BU8BOB123tζ at the rising edges of the clock signal 40 having a frequency 3002 times the clock output from the multiplier 41. The Q output is active high.

When the sampled BU8ROB signal 35 goes high, the output of the gate 17 goes high, disabling the address buffer 4 and the data buffer 7 address/data enable signal line 14, and disabling the AO-A1
The address line 20 of No. 5 and the data *28 of DO-Di5 are set to high impedance. Also sampled BUSROB
The signal 35 instructs the bus timing control section 33 to issue a command output disable request and a bus hold request;
The outputs of WR of D126 of No. 5 and BCY of No. 27 are respectively disabled, and the RD line, W line, and BCY line are made to have a high impedance of 2. It also invalidates the bus cycle currently being executed and stops execution of the bus cycle until the sampled BUSROB signal 35 becomes low level. moreover,
The sampled BUSROB signal 35 is an input to the 0 gate 18, and if the sampled BUSROB signal is NO or YES, a high level is output to the HLDAK line 22 as a hold acknowledge signal, making the command line and address/data bus high impedance. Let me know what you did.

FIG. 4 is a timing diagram thereof.

As explained above, the bus use request signal input asynchronously to the BUI and OB terminals 23 is sampled at the rising edge of the clock signal 40, which has twice the frequency of the clock input to the CLK terminal 30, and is immediately Since the bus is opened to peripheral devices, the peripheral devices can use the bus with a waiting time of at most 1/2 clock.

(Effects of the Invention) According to the present invention, in response to a bus use request from a peripheral device that is input asynchronously, the CPU stops the processing that is currently being executed and immediately allows bus use, allowing the peripheral device to use the bus instead. When the request is completed, the stopped processing is restarted from the beginning, and the bus usage time of peripheral devices can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the central processing unit of the present invention, FIG. 2 is a basic timing chart for explaining the operation of FIG. 1, FIG. 3 is a block diagram of another embodiment, and FIG. The figure is a timing chart. 2...BCυ, 3...EXU, 4-...
...Address buffer, 5...Data buffer/latch, 7...Instruction decoder, 8...
. . . Execution unit, 9 . . . Address generator, 10.
...Internal data bus, 11...Control signal, 12...Internal address bus, 13...
・Control signal, 14...address/data enable signal, 16.17.18...OR gate,
19...D type flip 70 knob, 20...
... Address bus, 21 ... Hold request signal line (HLDRQ), 22 ... Hold acknowledge signal line (HLDAK), 23 ... Bus intercept request signal line ( BUSROB), 24...
・Retry request signal line (ETBY), 25...
・Read command output signal line (RD), 26...
・Write command output signal line (WR), 27...
・Bass strobe output signal @ (BCY), 28...
・Data bus input/output signal line (Do-D15), 29・
...Internal retry request line, 30...Clock input signal line, 31...Control signal line, 33.
... Bus timing control section, 34 ... Hold acknowledge signal line, 35 ... Sampled BUS OB signal line, 36 ... Input/output direction control line, 37... Address/data buffer enable request line during bus cycle, 41... Multiplier, 50... Clock input signal, 51...
... Bus strobe output signal, 52 ... Address output signal, 53 ... Read command output signal, 54 ... Data bus input/output signal, 55 ...
...Bus stealing request signal, 56...Hold acknowledge signal, 57...Internal retry request signal, 58...1 bus cycle of read command, 59...・CPU hold state section, 60・
...Read retry cycle section, 61...
...High impedance state, 62...Signal stable state. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] an input terminal for inputting a bus use request signal from a peripheral device; and an input terminal for immediately invalidating a process being executed in response to input of the bus use request signal from the input terminal and allowing the peripheral device to use the bus. The central processing unit is characterized in that the disabled processing is executed again after the peripheral device finishes using the bus.