JPS62239238A - Break circuit - Google Patents

Abstract

PURPOSE:To easily shift the operation to a break processing after an instruction is executed by delaying and inputting the timing when the READY signal of a target system becomes active to a microprocessor. CONSTITUTION:An address agreement signal 6 reports to a READY detection circuit 7 and a READY delay circuit 8 that addresses agree with each other. The READY detection circuit 7 detects that a READYI9 from the target system is effective with the aid of a read control signal 5 and a clock 10, and makes a READY11 active. The READY delay circuit 8 delays the READY11 by the number of clocks that the address agreement signal 6, the READY11 and the clock 10 specify, and makes a microprocessor READY13 active.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a break circuit in a microprocessor development support device, and in particular, to a break circuit in a microprocessor development support device, and in particular, to , relates to a circuit that generates a break request signal.

[Conventional technology]

Conventionally, the break circuit in this building starts comparing the address value with the break condition address from the time the address in the bus cycle is resolved, and also compares the data value with the break condition data from the time the data value is determined. Start comparing. If both the address and data match, a break signal is generated.

[Problem that the invention seeks to solve]

The conventional break circuit described above compares the address and data in a bus cycle with a break condition, and if the comparison results in a match, a break request is sent to the microprocessor that outputs the address at that point. Normally, an NMI is used for a break request, and if an NMI is input before a certain point in a bus cycle, the microprocessor will accept the NMI after completing execution of the instruction that caused the bus cycle. However, if the NMI input is delayed to the next bus cycle, and the bus cycle in which the NMI is accepted is the bus cycle corresponding to the next instruction, the microprocessor will not accept the NMI after completing execution of the next instruction. I will attach it. For this reason, especially when a microprocessor attempts to request a break based on the data value read in a certain bus cycle, by the time the read data and the value set as the break condition are compared and a match is detected, the next The disadvantage is that the bus cycle is started, and the break does not occur at the target board, but after the execution of the next instruction is completed.

The above-mentioned drawback is that when a microprocessor performs pipeline processing and the execution of an instruction does not match, when a break request is requested at the data value of the last operand read of a certain instruction execution, If there is a possibility that after the command, several commands that have already been executed will be executed, this will be a bigger drawback. moreover,
As the clock frequency increases and the speed of Lm increases as in recent microprocessors, it becomes very difficult to transition to break processing after completing execution of an instruction having the target address and data.

[Means for solving problems]

The break circuit of the present invention includes an address comparator that compares an address value output from a microprocessor with a value set as a break condition, and a READY signal from a target system that is enabled by a match signal output from the comparator. a signal detection circuit; a READY signal delay circuit that delays the detected READY signal, which is activated by the coincidence signal, by a specified number of clocks; and a data value output from the memory or the microprocessor 4 to be read. Or, it has a data comparator that compares the write data value output from the microprocessor with a value set as a break condition, and requests the microprocessor to break if the data value matches the break condition. are doing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a break circuit according to an embodiment of the present invention. A break address setting section 1 is a block for setting an address value for breaking, and is set by a mechanical switch or a program. The set break address is input to the address comparison 641C through the entire break address signal 2. Address comparator 4 compares break address signal 2 and address signal 3 while read control signal (hereinafter referred to as FdEMR) 5 is active, and if they match, activates address match signal 6. MEMR5 is a signal output from the microprocessor and is a bus cycle for reading data.

Address match signal 6 is RE at the address comparator.
The ADY detection circuit 7 and READY delay circuit 8 are notified. The READY detection circuit 7 detects that the REAL)YI9 from the target system is valid using the read control signal 5 and the clock 10, and reads READYllxt.
lActivate. The READY delay circuit 8 delays READYlltt by the number of clocks specified by the address match signal 6, READYIll, and clock 10, and outputs the microprocessor READY (hereinafter CPURE).
It's called ADY. ) 13 is activated. It also detects the evening when the data becomes valid and activates the C1 data enable signal 12. READY19 is a READY signal input from the target system. Clock 10 is the clock of microprocessor 19, and READY detection circuit 7 and READY delay IC.
It is also input to circuit 8. READY Ill be READY
RE READY19 detected by detection time wr7
The ADY delay circuit 8 is notified. Data enable signal 1
2 is detected by the READY delay circuit 8 and communicates to the data comparator 17 the timing at which the /' data becomes valid.

CPUETEADYl 3 is set to 7! by the READY delay circuit 8! The microprocessor 19 is notified of the delayed READY signal. The break data setting section 14 is a block for setting data values at which a break should occur.
Set by ht switch or program.

The set break data is input to the data comparator 17 through the break data signal 15.

The data signal 16 is data outputted from the memory or Ilo at the request of the microprocessor 19, or data outputted by the microprocessor 19 during a write cycle, and is input to the data comparator 17. When the data enable signal 12 is active, the break data signal 15 and the data mark 16 are all compared, and if they match, the break request signal 18 is activated. Break request A8G3181 Notifies the microprocessor 19 that there is a break request.

The microprocessor accepts the pass-through break request as an IQ 9-inclusive request (hereinafter referred to as NMI) that cannot be masked, but if a microprocessor with a de-5x capability is used as the microprocessor 19. , it is accepted as an interrupt request for depacking (this is an interrupt input that does not exist in the original microprocessor, and usually has a higher priority than NMI). The microprocessor 19 is a microprocessor that executes a program for debugging by the user, and the address output from the microprocessor 19 is sent to the address comparator 4 as read data or write data (however, the write cycle is not explained in this embodiment). ) is the data comparator 17
is output to. Further, operations are performed in synchronization with clock 10, and the bus cycle is not completed until CPUREADY 13 becomes active. Furthermore, when the break request signal 18 is received, the execution of the user program that was being executed when the request signal 18 is received is completed, and then the break processing routine is executed.

Next, the present invention will be explained in detail.

First, the basic operation of a microprocessor will be explained using FIG. The microprocessor fetches instructions, reads and writes operands, and reads Ilo. The timing chart in Figure 2 is from T1 to T4.
This is the last operand read performed by a certain instruction, and the bus cycles after T1 are the bus cycles for the next instruction. The clock frequency I Q (MHz) is 100 [n! l:l. Furthermore, for example, the timing of the rise of the T1 clock described in the description indicates the rise of the evening/iminoji clock when T1 is started. In order to read the last operand of a certain instruction, the microprocessor outputs an address at the rising edge of the T1 clock.
At the falling edge of the clock T1, the MEMR signal is activated to indicate a read operation to the memory.

It is assumed that the time from when the address of the memory to be accessed is determined and the chip select signal becomes active until data is output from the memory is 220 (n8).

Therefore, by activating READY in the target system with sufficient setup time and hold time for the falling edge of T3, the microprocessor will read data 16 at the falling edge of the T4 clock following the T3 clock. Load. If READY is inactive at the falling edge of the T3 clock, the microprocessor inserts the TW clock next to the T3 clock, and when READY becomes active at the falling edge of the TW clock, the next clock becomes the T4 clock. , data is read at the falling edge of the T4 clock. The MEMR signal becomes inactive in synchronization with the falling edge of the T4 clock. The microprocessor then accesses the next instruction pool from the T1 clock.

An attempt is made to activate a break request to a microprocessor that performs the operations shown in FIG.

First, an attempt is made to activate a break request under an address-only condition, that is, when the address matches a previously specified address. It takes more than xoo (ns) from the start of the comparison until the result to determine whether they match or not, depending on the number of bits in the address, but in the following explanation, the results of address comparison and data comparison are determined by comparison. Assume that it takes 100[:nll, 1 after starting. Since a stable address is indicated by the activation of the MEMR signal, the comparison is started after the MEMR signal becomes active, and the comparison result is known just before the rising edge of the clock of T3. At this time, if a break request is activated for the microprocessor, the microprocessor will accept a break request that became active before the setup time of about 15 [ns] with respect to the falling edge of the T4 clock.
The subsequent cycles become break request response cycles. However, when address and data are specified as break conditions, matching of the address conditions can be recognized within this pass cycle as described above. However, since the timing at which it can be confirmed that the data is stable is the falling edge of the T4 clock, if the comparison is started from this timing, the break request signal will become active after the falling edge of the T1 clock. . For this reason, a break request is not accepted after the 15th instruction following the instruction to be broken is executed, so there is a drawback that depacking is delayed.

FIG. 1 shows an example in which the break circuit of the present invention is implemented in the timing-operated target system and microprocessor 19 shown in FIG. READY detection circuit 7 and READ
When the address match signal 6 is inactive, the Y delay circuit 8 outputs READY (READY) 9 to READYill and CPU
Since it is directly connected to EADY13, microprocessor 1
9 executes the command at the timing shown in FIG. Here, it is assumed that the microprocessor 19 is attempting to read an operand that reads the same data at the same address as the value set in the break condition. First, after the microprocessor 19 outputs the address,
Activate MEMR5. Address comparator 4 is M
When the EMR5 becomes active, a comparison between the address 3 and the break address signal 2 is started, and the address match signal 6 is activated before the rising edge of the clock T3. When the READY detection circuit 7 detects that the address match signal 6 becomes active at the second rising edge of the clock after 1VtEMR5 becomes active, that is, the rising edge of the clock T3, the READY detection circuit 7 outputs READY[l].
l is made inactive, READY1g2 is sampled at the falling edge of the clock after the falling edge of the T3 clock, and READYnl is sampled at the rising edge of the next clock.
The state of REAEY19 is transmitted to l. READY-
The M extension circuit 8 makes CPUREADYI3 inactive when the address-attack signal 6 becomes active. Therefore, the microprocessor 19 executes the first wait state (hereinafter referred to as TWl) before executing the T4 cycle. Therefore, the timing chart in this case is 7A.
The result will be as shown in Figure 3. In the timing chart, it is assumed that all signals except CLK, address, and data are active at low level. Now, IADY detection circuit 7
detects that READY)9 is active at the falling edge of the T3 clock, and activates READYnll at the rising edge of the TW1 clock. READ
The Y delay circuit 8 activates the data enable signal 12 at the falling edge of the next clock after the address match signal 6 is active and REAL)Yl[11 becomes active, that is, the falling edge of the clock of TWl. This is because READYI9 of the target system became active at the falling edge of the T3 clock, so at the falling edge of the next clock, that is, the falling edge of the TW1 clock, the stored data is input from the memory to the microprocessor 19. It is. Further, when the address signal 6 is active, the READY delay circuit 8 shifts READYIIll by one clock and controls the READY terminal of the microprocessor 19 as CPUREADY13. For this reason, CPU (
EADY13 is the second wait state period (hereinafter referred to as
It's called TW2. ), the microprocessor starts the next KT4 clock and reads data 16 at the falling edge of the f4 clock (in FIG. 1, data 16 and microprocessor 19 are not connected).

Microprocessor 19 to operate 1 as above
is normally TI when address matching condition 6 becomes accedip,
T2. Seven bus cycles are completed with each clock T3 and T4, but two states TW1 and TW2 are inserted between T3 and T4. The data comparator 17 is connected to the T vV when the data enable signal 12 becomes active.
Comparison starts from the falling edge of one clock. Since the break data signal 15 and the data signal 16 match in this read cycle, the break request signal 181 and T
It becomes active at the falling edge of the W2 clock. Therefore, the microprocessor 19 can detect that the break request 18 has become active at the falling edge of the T4 clock, making it possible to transition to the break processing routine from the T1 clock.

Note that the address match signal 6 becomes inactive when MEMIζ5 becomes inactive, and the data enable signal 12 and break request 18 also become inactive in sequence.

If the READYlg of the target system is at a timing that causes the microprocessor 19 to perform one wait in advance, the microgrossing circuit of the non-breakable circuit is activated. ]9 has three wait states. Further, it can be arbitrarily specified by the comparison speed of the shift clock au data comparator 17'4 of the READYilIL of the RE8 to Y delay processing circuit 8 in the description.

〔Effect of the invention〕

As explained above, the present invention delays and inputs the activation timing of READY No. 3 of the target system to the microprocessor at the specified address, so that the microprocessor can use the wait state specified by the target system in an extra manner. Therefore, even if the microprocessor compares the data read from memory with the break condition and the set data, and as a result, requests a break to the microprocessor, the memory If you request a break within the cycle, you will be able to come out, and you won't have to wait until the next stay. Further, in the first situation, the read cycle was explained, but if a break request is made in the same way in the customer input cycle, the next instruction will not be executed. However, it may not be necessary to control the READY signal because the microprocessor typically stabilizes the write data faster than the read data stabilizes during the load cycle. Further, the present invention can be applied not only as a break circuit for access to memory but also as a break circuit for access to the device 10.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the break circuit of the present invention, Fig. 2 is an evening/timing diagram showing the memory read cycle of the microprocessor, and Fig. 3 has the timing of the 2g2 diagram. It is a timing diagram when this break circuit is applied to a microprocessor and a target system. 1...Break address installation part, 2...
・Break address signal, 3...address signal, 4...address comparator, 5...read control signal, 6...address match signal, 7.
...READY detection circuit, 8...R1;
ADY delay circuit, 9...READYll 0
...CLK, 11...READYII
, 12...data enable signal, 13...
...Microprocessor READY, 14...
...Break data setting section, 15...Break data signal, 16...Data signal, 17...
...Data comparator, 18...Break request signal, 19...★ Microprocessor. Agent Patent Attorney Uchihara 2 days

Claims (1)

[Claims] an address comparator that compares an address value output from the microprocessor with a value set as a break condition; a READY signal detection circuit that is activated by a match signal output from the address comparator; and a READY signal detection circuit that is activated by the match signal. A circuit that delays the READY signal detected by the READY signal detection circuit by a specified number of clocks and supplies it to the microprocessor compares the data read or written by the microprocessor with the value set as the break condition. 1. A break circuit comprising: a data comparator, wherein a match signal outputted from said data comparator serves as a break request for said microprocessor.