JPH0760401B2 - Single-chip microcomputer for evaluation - Google Patents

Description

The present invention relates to an evaluation single-chip microcomputer having a privileged interrupt input terminal.

[Conventional technology]

The evaluation single-chip microcomputer has an evaluation privilege interrupt input terminal for temporarily interrupting the user program under a specific condition during execution of the user program and performing a privilege interrupt process for debugging. That is, by inputting a valid signal to the evaluation privileged interrupt input terminal, the user program can be interrupted, interrupt processing can be performed, and the debug interrupt processing program can be executed.

Normally, the debug interrupt processing program is mapped in a debug memory space different from the user program space. Therefore, when a privileged interrupt request occurs, the processing of the user program being executed at that time ends, and when the CPU actually accepts the interrupt request, the memory is switched from the user memory to the debug memory and the debug Execute the interrupt processing program on the memory. Therefore, a signal for maintaining an active level at the time of accepting a privileged interrupt request and during interrupt processing is created outside the chip, and this signal is used to switch between the user memory and the debug memory.

[Problems to be solved by the invention]

The conventional single-chip microcomputer for evaluation described above does not have a timing signal indicating that it is in the privileged interrupt processing state in response to the privileged interrupt request, and the CPU unit actually accepts the interrupt request. There is a drawback that a signal having the same function must be created and the user memory and the debug memory must be switched using this signal.

[Means for solving problems]

The single-chip microcomputer for evaluation according to the present invention is provided with a signal that the processor unit keeps the active level during the privileged interrupt processing, or once when the privileged interrupt is accepted and once after the recovery from the privileged interrupt processing. Generate a signal,
It has a circuit for outputting to the outside of the evaluation single-chip microcomputer.

[Action]

By using the signal as the privilege interrupt memory bank switching signal, the memory at the privilege interrupt time can be switched from the user memory to the debug memory, so that an external circuit which is conventionally required can be omitted.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a part of a first embodiment of a single chip microcomputer for evaluation of the present invention, and FIG.
The figure is a timing chart showing the operation.

The reset signal 1 is an initialization signal for a negative logic internal circuit input from outside the chip. The privileged interrupt input signal 2 is
This is a negative logic privileged interrupt request signal input from the outside.
The privileged interrupt output signal 3 is an external output signal indicating a negative logic active level during the privileged interrupt processing. The interrupt control unit 6 determines the priority of the interrupt,
This is a unit that controls the output of an interrupt request signal to the processor unit 10, the input of an interrupt acceptance signal from the processor unit 10 and the output of an interrupt acceptance signal 8. The interrupt return instruction end signal 7 is a negative logic timing signal output at the timing when the instruction return unit input from the instruction fetch unit 32 is decoded by the instruction decoder unit 31 and executed by the processor unit 10, and the instruction processing is completed. The D-FF 4 uses the inverted signal of the privileged interrupt input signal 2 as a clock input, the reset signal 1 or the write acceptance signal 8 as a preset, and outputs an interrupt request signal 9 from the Q output. D-FF5 inputs the Q output of D-FF4 to the clocker, reset signal 1 or interrupt acceptance signal 8
Is used as a preset input, and the privileged interrupt output signal 3 is output from the Q output.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

When the reset signal 1 becomes active (low) level by the external reset operation at the time t ₁ , D-FF4 and D-FF5 are initialized respectively, and the Q output becomes high level. Since the output of D-FF5 is the privileged interrupt output signal 3, the privileged interrupt output signal 3 is initialized to the high level. When privileges interrupt input signal 2 becomes active (low) level to the time t _2, the at its front edge, D-FF4 outputs the Q output latches a low-level data. This Q
The output is input to the interrupt control unit 6 as an interrupt request signal 9. Interrupt control unit 6
Then, the interrupt request signal is output to the processor unit 10, and the interrupt acceptance signal from the processor unit 10 output at an appropriate timing (time t ₃ ) is output as the interrupt acceptance signal 8. The interrupt acceptance signal 8 output from the interrupt control unit 6 activates the preset terminal PRT of D-FF4 and returns the Q output to the high level again. At the rising edge of Q output at this time, D-FF5
Latches the low level signal and outputs Q, that is, the privileged interrupt output signal 3 to the active low level.

Next, during the interrupt processing, when the processor unit 10 executes an interrupt return instruction to end the interrupt processing, the interrupt return instruction end signal 7 is set to active (low) level at time t ₄ at the same time as the end of the instruction. . End signal 7 is D
-Activate the preset terminal PRT of FF5, output Q,
That is, the privileged interrupt output signal 3 is returned to the high level again.

As described above, the privileged interrupt output signal 3 according to the present embodiment has the function of keeping the active (low) level during the processing of the privileged interrupt by the processor unit 10.

Next, the operation sequence for switching the memory from the user memory to the debug memory during the privileged interrupt processing by using the privileged interrupt output signal 3 will be described.

FIG. 3 is a diagram for explaining the memory bank switching operation of the evaluation single-chip microcomputer shown in FIG.

The evaluation single-chip microcomputer 11 includes a user program memory 12 and a debug program memory.
13 is connected to the address / data multiplex bus and the status bus, and is further connected to the privileged interrupt factor generation circuit 16. The user program memory 12 and the debug program memory 13 have memory chip select terminals 19 and 20, respectively. The evaluation single-chip microcomputer 11 has the evaluation privileged interrupt input terminal 15 and the privileged interrupt signal output terminal 14, and normally executes the user program mapped in the user program memory 12. During execution of the user program, the privileged interrupt input signal 2 is output from the privileged interrupt factor generation circuit 16,
When a valid signal is input to the evaluation privileged interrupt input terminal 15, the evaluation single-chip microcomputer 11
After the end of the user instruction currently being processed, privileged interrupt processing is performed at an appropriate timing. At the timing when the CUP operation switches from the user program execution state to the privileged interrupt processing state, the active level low privileged interrupt output signal 3 is output from the output terminal 14. As described above, the privileged interrupt output signal 3 maintains the active level during the privileged interrupt processing,
When the evaluation single-chip microcomputer 11 executes the interrupt return instruction during interrupt processing, the privileged interrupt output signal 3 becomes inactive at the timing of returning from interrupt processing and switching to the user program execution state again. Thus, only when the evaluation single-chip microcomputer 11 is in the privileged interrupt processing state,
By having the privileged interrupt output signal 3 which becomes active, this signal is used as the bank switching signal of the memory.

FIG. 4 shows the above-described series of operation sequences after the privileged interrupt input signal 2 is input to the evaluation privileged interrupt input terminal 15 with respect to the operations of the signals 2 and 3, the processor unit 10 and the memory map. The privileged interrupt output signal 3 is input to the chip select terminals 19 and 20 of the user program memory 12 and the debug program memory 13, and when the user program is executed, the user program memory 12 is selected and when the privileged interrupt is processed. Can select the debug program memory 13.

FIG. 5 is a block diagram showing a part of an internal circuit of the second embodiment of the evaluation single-chip microcomputer of the present invention, and FIG. 6 is a timing chart of each signal in FIG.

Reset signal 1, privileged interrupt input signal 2, interrupt control unit 6, interrupt return instruction end signal 7, interrupt acceptance signal
8, the interrupt request signal 9 has the same function as in the first embodiment. The privileged interrupt output signal 21 is
It is an external signal having a function of outputting a negative logic timing signal having a constant pulse width once, and then outputting a negative logic timing signal having a constant pulse width once again after returning from interrupt processing. . The first instruction execution signal 25 after returning from the interrupt is a negative logic signal output from the processor unit 26 when executing the next instruction after executing the interrupt returning instruction. The D-FF22 clock-inputs the inverted signal of the privileged interrupt input signal 2, reset signal 1 or interrupt acceptance signal 8
Is a preset input, and the Q output is an interrupt request signal 9. The D-FF 23 uses the inverted signal of the privileged interrupt input signal 2 as a clock input, the reset signal 1 or the first instruction execution signal 25 after the interrupt recovery as a preset input, and the Q output as an output control signal 34. The output control buffer 24 outputs an interrupt acceptance signal 8 and an interrupt return instruction end 7 when the output control signal 34 becomes low level.

Next, the operation of the circuit of FIG. 5 will be described with reference to the timing chart of FIG.

When the reset signal 1 becomes active (low) level by the external reset operation, D-FF22 and D-FF23
Are initialized respectively, and all Q outputs become high level. The Q output of D-FF22, that is, the interrupt request signal 9 is initialized to a high level inactive state, and D-FF23
Q output makes the output control buffer 24 inactive. Therefore, the privileged interrupt output signal 21 is also initialized to the high level. When the privileged interrupt input signal 2 becomes active (low) level at time t ₂ , D-FF22 occurs at the leading edge of the signal.
And D-FF23 latch the low level signal and output it to the Q output. The Q output of D-FF22 is input to the interrupt control unit 6 as the interrupt request signal 9. On the other hand, the Q output of D-FF23 activates the output control buffer 24. The interrupt control unit 6 outputs an interrupt request signal to the processor unit 26, and also outputs an interrupt acceptance signal 8 at an appropriate timing (time t ₃ ). Interrupt control unit 6
The interrupt acceptance signal 8 output from the D-FF 22 makes the preset terminal PRT of the D-FF 22 active and returns the Q output (interrupt request signal 9) to the high level again. The interrupt acceptance signal 8 is the output control buffer in the active state.
One pulse is given to the privileged interrupt output signal 21 via 24.

Next, when the processor unit 26 executes an interrupt return instruction to end the interrupt processing, an active level low pulse is output to the interrupt return instruction end signal 7 at time t ₄ at the same time as the end of the instruction, and similarly. The second pulse is applied to the privileged interrupt output signal 21. After execution of the interrupt return instruction is completed, the next instruction is transferred from the instruction fetch unit 32 to the instruction decoder unit 31, and the processor unit
The first instruction execution signal after returning from an interrupt when executed in 26.
25 becomes active (low) level (time t ₅ ) and D-
The preset terminal PRT of FF23 becomes active and the Q output of D-FF23 returns to high level. Therefore, the output control buffer 24 becomes inactive, and the privileged interrupt output signal 21 remains inactive until the next privileged interrupt occurs.

As described above, the privileged interrupt output signal 21 according to the present embodiment has a function of outputting an active (low) level timing signal having a constant pulse width once when a privileged interrupt is accepted and once after returning from the interrupt processing. Have.

Next, a memory bank switching operation sequence using this signal as in the first embodiment will be described.

FIG. 7 is a block diagram for explaining a memory bank switching operation using the evaluation single-chip microcomputer 27 having the circuit shown in FIG. 5, and FIG. 8 is a time chart of the memory bank switching.

The evaluation single-chip microcomputer 27 is the first
Similar to the embodiment described above, it has an evaluation privileged interrupt input terminal 15 and a privileged interrupt output terminal 28, and is connected to the user program memory 12 and the debug program memory 13 via the address / data multiplex bus and the status bus. A D-FF 30 which further has a reset signal output terminal 29 and generates a memory chip select signal 33 is connected between the privileged interrupt signal output terminal 28 and the memory chip select terminals 19 and 20.

In the second embodiment, the privileged interrupt output signal 21 functions as follows. Single-chip microcomputer for evaluation 27
Is a privileged interrupt input pin for evaluation during user program execution 15
When a valid signal is input to, privileged interrupt processing is performed at an appropriate timing after the end of the user instruction being processed. The evaluation single-chip microcomputer 27 outputs a timing signal (active level low) having a constant pulse width to the terminal 28 at the timing when the CUP operation switches from the user program execution state to the privileged interrupt processing state ( Time t ₁ ). Further, at the timing when the evaluation single-chip microcomputer 27 switches from the interrupt processing state to the user program execution state again, a timing signal having a constant pulse width is output again to the terminal 28 (time
t ₂ ).

In this way, the evaluation single-chip microcomputer 27 has a function of outputting a pulse once when a privileged interrupt is accepted and outputting the pulse once again after returning from the interrupt processing. The memory bank switching signal is created as follows. When the evaluation single-chip microcomputer 27 is reset,
A low level signal is output from the reset output terminal 29,
The output of D-FF30 becomes high level. When the reset of the evaluation single-chip microcomputer 27 is released, the evaluation single-chip microcomputer 27 executes the program on the user program memory 12 selected by the output (memory chip select signal 33).

Next, when the evaluation single-chip microcomputer 27 switches to the privileged interrupt state, the output of the D-FF 30 is inverted at the leading edge of the timing signal output to the terminal 28 (see the memory chip select signal 33 in FIG. 8). At this time, since the debug program memory 13 is selected, the evaluation single-chip microcomputer 27 executes the debug program on the debug program memory 13 (see the memory map in FIG. 8). Further, when returning from the interrupt processing, the output of the D-FF30 is inverted again at the leading edge of the second timing signal output to the second timing signal output terminal 28 output to the privileged interrupt signal output terminal 28, and the output of the D-FF30 is inverted. By selecting the program memory 12, the evaluation single-chip microcomputer 27 executes the user program after returning from the interrupt processing (see the memory map in FIG. 8).

Memory chip select signal 33 generated in this way
By using, the memory bank can be switched at the time of privileged interrupt processing.

〔The invention's effect〕

As described above, according to the present invention, the signal that the processor unit maintains the active level during the privileged interrupt processing or the active level timing signal having the constant pulse width is generated once when the privileged interrupt is accepted and after the recovery from the privileged interrupt processing. A signal is generated and output to the outside of the evaluation single-chip microcomputer. By using this signal as a memory bank switching signal for privileged interrupts, the memory at privileged interrupts can be switched from user memory to debug memory. The effect is that the external circuit can be omitted.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of an evaluation single-chip microcomputer of the present invention, FIG. 2 is a timing chart of each signal used in FIG. 1, and FIGS. FIG. 5 is an explanatory diagram of a memory bank switching operation of an evaluation single-chip microcomputer having the circuit shown in FIG. 1, FIG. 5 is a circuit diagram of a second embodiment of the present invention, and FIG. 6 is used in FIG. FIGS. 7 and 8 are timing charts of the respective signals that are provided, and are explanatory diagrams of the memory bank switching operation of the evaluation single-chip microcomputer having the circuit shown in FIG. 1 ... Reset signal, 2 ... Privilege interrupt input signal, 3,21
...... Privileged interrupt output signal, 4,5,22,23,30 …… D-FF, 6
…… Interrupt control unit, 7 …… Interrupt return instruction end signal, 8 …… Interrupt acceptance signal, 9 …… Interrupt request signal, 10,26 …… Processor unit, 11,27 …… Evaluation single-chip microcomputer, 12 ...... User program memory, 13 ・ ・ ・ Debug program memory, 14,28 ・ ・ ・ Privileged interrupt signal output terminal, 15 ・ ・ ・ Evaluation interrupt input terminal, 16 ・ ・ ・ Privileged interrupt factor generation circuit, 19,2
0 …… Memory chip select terminal, 24 …… Output control buffer, 25 …… First instruction execution signal after interrupt recovery, 29 …… Reset signal output terminal, 31 …… Instruction decoder unit, 32 …… Instruction fetch unit, 33 …… Memory chip select signal, 34 …… Output control signal.

Claims (3)

[Claims] 1. A single-chip microcomputer for evaluation which executes a user program stored in a user program memory in a normal state and executes a debug program stored in a debug program memory in a privileged interrupt state in a privileged interrupt input. An input terminal for receiving a signal; a means for detecting that the privileged interrupt input signal is supplied to the input terminal and generating a privileged interrupt output signal indicating a transition from the normal state to the privileged interrupt state; An output terminal for outputting an interrupt output signal to the outside, and the memory to be accessed is switched from the user program memory to the debug memory using the privileged interrupt output signal output from the output terminal. Single chip micro for evaluation characterized by Computer. 2. The privileged interrupt output signal is maintained at an active level during the privileged interrupt state, and the debug program memory is controlled to be in an access state by the active level. The evaluation single-chip microcomputer according to claim 1. 3. The privileged interrupt output signal once takes an active level at the transition from the normal state to the privileged interrupt state and again takes an active level at the time of returning from the privileged interrupt state to the normal state. 7. The evaluation single-chip microcomputer according to claim 1, wherein the access to the user program memory and the debug program memory is switched by a change in the active level of the evaluation single chip microcomputer.