JPS58107963A - Interruption processor - Google Patents

Abstract

PURPOSE:To prevent the complicated program constitution of a program to be normally processed and to attain efficient use of a memory address area, by storing a processing program arranged by each interruption cause at each bank number of the duplicated memory address area. CONSTITUTION:At the executing processing of an interruption processing program, to return the program to a normal processing program, a return instruction or the like is inserted at the final part of the interruption processing program. This return instruction is read out at a microcomputer MPU1, the return instruction code and an instruction code on a data bus 9 are compared and discriminated at a return instruction code discriminating circuit 8, and when both the codes are coincident, a latch of a latch circuit 4 forming a bank number generating circuit 2 is cleared. Thus, the bank number is reduced to 0, the memory address areas of the bank number 0 is selected, and the MPU1 returns to the interrupted program to be normally processed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt processing device capable of executing an interrupt processing program for each interrupt factor in a microcomputer (hereinafter referred to as MPU).

Conventionally, the processing program for each interrupt factor in the MPU is
It is laid out in the memory address area for direct access by the MPU, and storage addresses are assigned to each interrupt factor. Then, when an interrupt occurs, a transition is made to the necessary interrupt processing program.

However, in recent years, devices using MPUs have been required to have advanced functions and complicated processing, and the number of interrupt factors has increased, and the amount of interrupt processing programs has also tended to increase. For this reason, in conventional interrupt processing methods, as the amount of interrupt processing programs increases, the ratio of the storage area to the MPU direct access memory area increases, putting pressure on the normal processing program area, and sometimes causing the MPU direct access memory Sometimes it became impossible to store data within the area.

As described above, when the required memory capacity cannot be stored in the memory address area directly accessed by the MPU, memory is switched using the concept of banks. However, 1. Switching banks while the normal processing program is being executed requires inserting the bank switching program at various places in the normal processing program, which makes the program configuration very unconventional.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an interrupt processing device that can prevent the program configuration of a normal processing program from becoming complicated and can efficiently utilize a memory address area.

In order to achieve this objective, in the present invention, a part of the memory address area is overlapped, and the overlapped memory address area is switched by bank number, and the interrupt factor is specified for each bank number of the overlapped memory address area. Stores the processing program. The normal processing program is laid out in a memory address area directly accessed by the MPU, and operates at bank number O, or when an interrupt occurs, the bank number is switched according to the cause of the interrupt, and the program moves to the interrupt processing program. This makes it possible to avoid complicating the program structure of the normal processing program and to use the memory address area efficiently and effectively.

FIG. 1 is a block diagram of an interrupt processing device according to the present invention. In the figure, 1 is an MPU. This MPU'
During the execution of the normal processing program, I sets the bank number to 0 and operates using the memory area directly accessed by the MPU. A part of the memory address area for MPU direct access has a double memory address area. For example, as shown in FIG.
A processing program for interrupt factor 1 and a processing program for interrupt factor 2 are placed in FFH. The memory areas of 1.2110. Allocate. And this bank number 1.2111. The switching of each memory area is performed by the following.

2 is a bank number generation circuit that generates a bank number.

The bank number generation circuit 2 includes a priority encoder 3, a latch circuit 4, and a decoder 5. The priority encoder 3 selects interrupt factor 1 (i=1 to n) in a predetermined priority order and outputs the binary code of interrupt factor i. The latch circuit 4 and decoder 5 latch the interrupt factor i encoded by the priority encoder 3 as a bank number, and decode it.

6 is memory that can be directly accessed by the MPU, and is 6.0~
6. n indicates each memory address area of bank numbers 0 to n that overlap with each other.

7 is a transition instruction code generation circuit that generates a transition instruction for transitioning to the interrupt processing program; 8 is a return instruction code determination circuit. FIG. 3 shows a concrete block diagram of the transition instruction code generation circuit 7, including an AND circuit 7a which takes the AND of the interrupt response signal INTA applied from the MPU 1 and the instruction fetch cycle signal, and an instruction code setting circuit 7b.
It is composed of the following.

A return instruction code determination circuit 8 compares and determines the instruction code on the data bus 9t and the return instruction code during an instruction fetch cycle of the MPU 1, and when the two signals match, clears the latch of the latch circuit 4. FIG. 4 shows a concrete block diagram of this return instruction code determination circuit 8.

In this embodiment, the return instruction code from the instruction code setting circuit 8a and the instruction code from the data bus 9 are compared in the comparison circuit 8b, and the match signal is input to the AND circuit 8c to fetch the instruction from the MPU 1. The configuration is such that an AND with the cycle signal is taken, and when the AND conditions are met, a reset I= signal is sent to the latch circuit 4 of the bank number generation circuit 2, and the latch of the latch circuit 4 is cleared.

In the above configuration, when an interrupt factor i occurs, an interrupt signal INT is input to the MPU 1 via an OR circuit IO. When MPU 1 recognizes the occurrence of an interrupt by inputting this interrupt signal INT and moves to the interrupt processing program, MPU 1
1, an interrupt response signal INTA is inputted to the bank number generation circuit 2 and transfer instruction code generation circuit 7. When this interrupt response signal INTA is given to the transfer instruction code generation circuit 7, an instruction is issued from the transfer instruction code generation circuit 7 to transfer the processing program to a specific address in the memory address area overlapped with respect to MPUI. For example, a restart command, a call command, etc. are given. on the other hand,
In the circuit 4 of the bank number generation circuit 2, the bank number i due to the interrupt factor i is latched at the trailing edge of the interrupt response signal INTA.

The latched puncture number i is decoded by the decoder 5, and the memory address area 6. of the puncture number i is decoded from the duplicated memory address area. Select i. Then, the memory address area 6. is sent from the MPUI via the data bus 9. i
The processing program is migrated to a specific address within, and the corresponding processing program is executed.

When executing an interrupt processing program, in order to return to the normal processing program, insert a return instruction at the end of the interrupt processing program, read this return instruction with MPUI, and read the return instruction code and data bus 9. The return instruction code determination circuit 8 compares and determines the instruction code of the bank number generation circuit 2 with the instruction code of the bank number generation circuit 2 when the two codes match. As a result, the puncture number becomes 0, the memory address area with the puncture number O is selected, and the MPU 1 returns to the interrupted normal processing program.

As described below, according to the present invention, the interrupt processing program is deleted from the MPU direct access memory address area, stored in the bank address area, and accessed by switching the bank address depending on the interrupt factor. It is possible to provide an interrupt processing device that can avoid complicating the program configuration of a normal processing program and efficiently use a memory address area.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interrupt processing device according to the present invention, and FIG.
3 shows an example of a memory map, FIG. 3 shows a specific block diagram of a transfer instruction code generation circuit, and FIG. 4 shows a specific block diagram of a return instruction code determination circuit. l・--MPU 2...Bank number generation circuit 3--Skew priority encoder 4 Library/latch circuit 5...Decoder 7・φ・Transition instruction code generation circuit 8φ...Return instruction code determination circuit-31

Claims (1)

[Claims] (1) A memory configuration in which multiple memory areas are overlapped in a part of the directly accessible memory of a microcomputer and a memory bank number is assigned to each memory area, and a memory bank number is generated based on an interrupt factor. It is equipped with a bank number generation circuit, a transition instruction code generation circuit that shifts program processing to a specific address by an interrupt, and a return instruction code determination circuit that determines that the program has returned from interrupt processing. The memory bank number is changed depending on a factor, and the interrupt processing is performed by moving to a specific address of the corresponding memory area, and when returning to the interrupt processing, the memory bank number is returned to the memory area and the corresponding address before the transition to the interrupt processing. Interrupt processing device.