JPS63228926A - Automatic power factor regulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an automatic power factor adjustment device that can confirm whether a power factor correction capacitor is connected or disconnected from the power system.

(Prior Art) Conventionally, automatic power factor adjustment devices that measure the power factor of a power system and adjust the power factor by connecting or disconnecting a power factor correction capacitor based on the measurement result have been used. The one shown in Figure 4 is known.

The automatic power factor adjustment device 1 shown in this figure measures the power factor of the power system 20, and when this power factor is not within a predetermined range, turns on the closing relay (or cutting relay) 3. It drives the auxiliary relay 4 and connects or disconnects the power factor correction capacitor 5 from the power system 2. It is checked whether the power factor correction capacitor 5 is connected to the power system 2 or whether it is disconnected.

(Problems to be Solved by the Invention) However, in such a conventional automatic power factor adjustment device 1, it is not possible to detect a contact failure of the auxiliary relay 4 or a failure of the power factor correction capacitor.

For this reason, if such a contact failure or a failure of the power factor correction capacitor occurs, the power factor adjustment operation continues unknowingly, resulting in the inability to perform proper power factor control or the failure of the power factor correction capacitor. In many cases, the capacitor 5 was punctured.

In addition, since the opening/closing state of the contact 4a in the auxiliary relay 4 is detected to detect whether the power factor correction capacitor 5 is turned on or off, the automatic power factor adjustment device can be connected via the contact 4a. There were cases where noise entered the device and caused the device to malfunction.

In view of the above circumstances, the present invention is capable of detecting the turning on and off of a power factor improving capacitor without using the contacts of an auxiliary relay.
It is an object of the present invention to provide an automatic power factor adjustment device that can determine whether the control circuit for this power factor improvement shifter is functioning properly.

(Means for Solving the Problems) In order to solve the above problems, the automatic power factor adjustment device according to the present invention measures the power factor of the power system and installs a power factor correction capacitor based on the measurement result. In an automatic power factor adjustment device that adjusts the power factor by turning on or disconnecting the power factor correction capacitor, there is a storage section that stores the power factor before turning on or disconnecting the power factor correction capacitor, and a memory section that stores the power factor before turning on or disconnecting the power factor correction capacitor. There is a comparison section that compares the power factor with the power factor after the power factor improvement capacitor is connected or disconnected, and the quality of the power factor improvement capacitor is determined based on the comparison result of this comparison section. The present invention is characterized in that it includes a determination section that performs the following steps.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an automatic power factor adjustment device according to the present invention.

The automatic power factor adjustment device shown in this figure includes a voltage input section 15,
It includes a power supply section 23, a current input section 16, a phase difference pulse generation section 17, a central processing unit (CPU) 18, an operating condition setting section 19, a display section 20, and an output section 21,
It controls the turning on and off of the power factor improvement capacitor (shown in the diagram) so that the power factor of the power system 22 falls within a predetermined range, and also checks whether the power factor improvement capacitor or its control circuit is malfunctioning. Inspect the power factor correction capacitors and disable them if they are defective.

The voltage input section 15 includes an over-input protection circuit 31 that limits the voltage signal output from the transformer 30 provided in the Mino J system 22 to a certain value or less to protect the subsequent circuit, and this over-input protection circuit 31. a transformer 32 that transforms the output of the transformer 32, and an over-input protection circuit 33 that limits the voltage detection signal output from the transformer 32 to a certain value or less to protect the subsequent circuit.
and a level conversion circuit 34 that lowers the output of the over-input protection circuit 33 to the input level of the CPU 18.
A voltage detection signal is generated based on the output of the transformer 30, and is supplied to an analog input terminal of the CPU 15.

The power supply unit 23 also includes a transformer 35 that transforms the output of the over-input protection circuit 31, and a constant voltage circuit 36 that generates a power supply voltage of a predetermined value from the output of the transformer 35. , the power supply voltage obtained by this constant voltage circuit 36 is supplied to each part of the circuit.

The current input unit 16 also includes an insulation transformer 38 that transforms the output (current signal) of the current transformer 37 provided in the power system 22, and a current detection signal output from the transformer 38 to a constant value. An over-input protection circuit 39 protects the subsequent circuit by limiting the output to CP
It is equipped with a level conversion circuit 40 that lowers the input level to the input level of the current transformer 37, generates a current detection signal based on the output of the current transformer 37, and supplies this to the analog input terminal of the CPU 18.

Further, the phase difference pulse generating section 17 includes the over-input protection circuit 3.
a phase pulse generation circuit 41 that amplifies the output of No. 3 at a high amplification factor to generate a phase signal (rectangular wave signal) of the voltage detection signal;
It is equipped with a phase pulse generation circuit 42 that amplifies the output of the over-input protection circuit 39 at a high amplification factor to generate a phase signal (rectangular wave signal) of the current detection signal, and outputs each of these phase signals to CP-〇. - Supplied to each separate terminal of U18.

Further, one operating condition setting section includes a function selection setting circuit 50,
Leading reactive power setting circuit 51 and lagging reactive power setting circuit 5
2, a closing/cutting operation time setting circuit 53, a CT ratio setting circuit 54, a display setting circuit 55, and a PT ratio setting circuit 56.
, a control group setting circuit 57, and an overcurrent setting circuit 58, and the values set in each of the function selection setting circuit 50 to overcurrent setting circuit 58 are read by the CPU 18 at any time.

In this case, the function selection setting circuit 50 is 100V/200V
It is equipped with a changeover switch and a single-phase/three-phase changeover switch, which are operated when setting the set conditions for this device.

Further, the leading reactive power setting circuit 51 includes a setter (for example, a thumb, low-return switch, etc.) for setting the allowable value of the voltage and current flowing in the power system 22 on the leading phase side. Operated when setting tolerances.

Furthermore, the delayed reactive power setting circuit 52 includes a setter (for example, a thumb rotary switch, etc.) for setting the allowable values of the voltage and current flowing through the power system 22 on the delayed phase side. Operated when setting tolerances.

In addition, the closing/cutting operation time setting circuit 53 is equipped with a setter such as a thumb rotary switch, and after the setting conditions for turning on and shutting off the power factor correction capacitor are established, the power factor correction capacitor is actually operated. The dull time between turning on and turning off the capacitor is set.

Further, the CT ratio setting circuit 54 is equipped with a setter such as a thumb rotary switch, and the current transformer 3 is connected to this setter.
Level conversion circuit 40 by setting the current conversion ratio of 7.
The CPU 18 is taught the ratio between the value of the current detection signal output by the CPU 18 and the load current value of the power system 22.

The display setting circuit 55 also includes a setting device (for example, a thumb rotary switch, etc.) for setting which of each setting value and each measured value is displayed, and by operating this setting device, The types of set values and the types of measured values displayed on the display section 20 change.

Further, the PT ratio setting circuit 56 is equipped with a setter such as a thumb rotary switch, and this setter is connected to the transformer 3.
By setting the transformation ratio of o, the level conversion circuit 34
The CPU 18 is taught the ratio between the value of the voltage detection signal output by the CPU 18 and the line voltage value of the power system 22.

Further, the control group setting circuit 57 is equipped with a setting device such as a thumb rotary switch, and by operating this setting device, the device can be operated in automatic power factor correction mode.
It can also be operated in manual power factor correction mode.

Further, by operating this stabilizer, a specific power factor correction capacitor can be turned on (or cut off) in advance.

Further, the overcurrent setting circuit 58 includes a setting device such as a one-tsum rotary switch, and by operating this setting device, it is possible to determine whether or not an overcurrent is flowing in the power system 22. A reference value is entered.

The display unit 20 also includes a capacitor input state display circuit 60, a reactive power state display circuit 61, a display element group 63, and a display element group drive circuit 62, and the CPU 18
When display data and display signals are supplied from the controller, each lamp or display element is turned on or off in response to the display data or display signal.

In this case, the capacitor input state display circuit 6o
It is equipped with eight lamps 64a to 64h that turn on/off in response to a lighting signal and a lights-out signal from the puis, and by lighting these lamps 64a to 64h, the power factor correction capacitor that is currently connected is displayed. .

Further, the reactive power state display circuit 61 has a progress display lamp 64.
, a propriety indicator lamp 66, and a delay indicator lamp 67.When an advance signal is supplied from the CPU 18, the advance indicator lamp 65 is lit, and when a delay signal is supplied, the lag indicator lamp 67 is turned on. lights up. Also, when a proper signal is supplied from this CPU 18,
Avoid lighting the appropriateness indicator lamp 66. This displays the current phase state of the power system 22.

The display element group drive circuit 62 is configured to generate an advance display signal, a delay display signal, and a segment drive signal based on the output of the CPU 18. The display element group 63
supply to.

The display element group 63 includes a lead display element 70 that lights up when the lead display signal is supplied, a delay display element 71 that lights up when the delay display signal is supplied, and a segment drive signal that is supplied with the lead display element 70 that lights up when the lead display signal is supplied. At the time, the function selection setting circuit 50 is provided with three "'7" segment display elements 72a to 72C that display the numerical value indicated by this segment drive signal, and these advance display elements 70 to II 7 IT segment display elements 72c - CT ratio setting circuit 54, PT ratio setting circuit 56 - overcurrent setting circuit 58 respectively set values and measured values specified by display setting circuit 55 are displayed.

The output section 21 also includes eight closing/cutting output relays 81a.
A group of closing/cutting output relays 82 having a power output of ~81h, a closing/cutting output relay drive circuit 80 that drives the group of closing/cutting output relays 82 based on the output of the CPU 18, an overcurrent relay 84, and a An overcurrent relay drive circuit 83 that drives the overcurrent relay 84 based on the output, an abnormality alarm output relay 86, and the CPU 18.
It is equipped with an abnormal alarm output relay drive circuit 85 that drives the abnormal alarm output relay 86 based on the output of the relay 81, and drives each of these relays 81a to 81h, 84.86 to output each bank drive signal. , outputs an overcurrent contact signal or an abnormality alarm contact signal.

The CPU 18 also includes a microprocessor with an analog input terminal, a ROM in which programs and various constant data for the microprocessor are stored, a RAM that serves as a work area for the microprocessor, and a connection between the microprocessor and each part of the circuit. It is equipped with various interfaces for connecting.

In this case, a part of the RAM includes a measured value storage area 87 in which the current power factor value φ obtained by the measurement operation, the current reactive power value A, etc. are stored, as shown in FIG. A delayed reactive power set value storage area 88 where the reactive power set value B is stored, an advanced reactive power set value storage area 89 where the advanced reactive power set value C is stored, and a temporary reactive power set value storage area where calculation results etc. are temporarily stored. An area 90, an operation time setting value storage area 91 where the operation time setting value E is stored, a flag area 92 where 7 lag F is set when the operation time is being measured, and a flag area 92 where the 7 lag F is set when the operation time is being measured. A delay timer counter area 93 used, a comparison request flag area 94 where a flag H is set when comparing the previous reactive power value and the current reactive power value, and a comparison request flag area 94 used when measuring the operating time K. A counter area 95 for measuring operating time is provided.

When the power factor correction capacitor is turned on and off, the CPIJ 18 operates as described below.

First, before starting the process of turning on and cutting off the power factor improving capacitor, the CPU 18 reads out each setting value from the operating condition setting section 19 and stores them in the corresponding area of the RAM.

Further, in parallel with this operation, the CPU 18 calculates the power factor value ψ based on the difference between the respective phase signals output from the phase difference pulse generation section 17, and uses this power factor value ψ and the output from the voltage input section 15. A reactive power value A is determined based on the value ■ of the voltage detection signal output from the current input section 16 and the value of the current detection signal outputted from the current input section 16, and these power factor values ψ and reactive power values A are measured in the RAM. The value is stored in the value storage area 87.

When the process of turning on and cutting off the power factor improving capacitor starts, cpuis first changes the power factor value ψ,
The reactive power value A is compared with the delayed reactive power set value B stored in the delayed reactive power difference setting storage area 88 of the RAM, and it is determined whether the current reactive power value A is larger than the delayed reactive power set value B. To check.

Then, if A<B, the CPU 18 performs this step S.
TI branches to step ST2, where the current reactive power value A and the advanced reactive power setting value storage area 89 in the RAM are stored.
A is compared with the advanced reactive power setting value C stored in A.
If <C, the process advances from step ST2 to step ST3.

In step ST3, the CPU 18 clears the temporary area 90, flag area 92, and operation time measurement counter area 95 provided in the RAM, and then clears the comparison request flag area 95 in step ST4.
Check whether the comparison request flag H is set.

In this case, since the comparison request flag H is not set in the comparison request flag area 94, the CPU 18 ends the process of determining the quality of the power factor improving capacitor and proceeds to the next process.

Further, in step ST1, △≧B,
If A≧C in step ST2, CPU1
8 is these steps STI, 2 to step ST5
Flag F indicating that the operation time is being measured by branching to
is set in the flag area 92.

If this flag F is not set, the CPU
18 branches from this step ST5 to step ST6, where this flag F is set in the flag area 92. As a result, the operation time measurement counter area 95 is opened, and the value of the operation time measurement counter area 95 (operation time value K) is automatically changed every time the reference clock is output from the reference clock generator (not shown). is incremented to

Further, in the step ST5, if the flag F is set in the flag area 92, the step ST5
6 is skipped.

Next, in step ST7, the CPU 18 changes the operating time value K in the operating time measurement counter area 95 to the operating time setting value E stored in the operating time setting value storage area 91.
If the operation time value K does not exceed the operation setting value E, the process branches from this step ST7 to the above-mentioned step ST4, and the above-mentioned operation is repeated.

When the operating time value K exceeds the operating time setting value E, the CPU 18 detects this in step ST7 and branches from step ST7 to step ST8.

In step ST8, the CPU 18 transfers the current power factor value ψ and reactive power value stored in the measured value storage area 87 to the temporary area 90, and uses the power factor correction capacitor to turn on and off. Previous reactive power value A
After storing it as O, a closing signal (or a shutoff signal) is output in step ST9 to turn on/off a necessary one of the eight closing/cutting output relays 81a to 81h in the output section 21.

Next, in step 5T10, the CPU 18 sets 7 lags H in the comparison request flag area 94 to compare the reactive power value AO stored in the temporary area 90 with the reactive power value A that will be obtained next time. request.

As a result, the delay timer counter area 93 for measuring delay time is opened, and the value (operating time value G) of this delay timer counter area 93 is automatically incremented every time the reference clock is output. .

After that, in step ST11, the CPLJ 18 clears the flag area 92 and the counter area 95 for measuring operation time, and then proceeds to step ST4 to check whether the comparison request flag H is set in the comparison request flag area 94. do.

In this case, since the comparison request flag H is set in the comparison request flag area 94, the CPU 18 branches from step ST4 to step 5T12, where the value of the delay timer counter area 93 (delay time value G) is Operating time setting value E (in this case, this value E is 1 second,
or some other preset time).

If this does not exceed the operating time setting value F, then C
The PU 18 determines that the time indicated by the operating time setting value E has not elapsed since the power factor correction capacitor was turned on and off, and returns to the operation described above.

Then, when the time indicated by the operating time setting value E has elapsed since the power factor correction capacitor was turned on and off, C
When the PU 18 executes step 5T12, it detects this and executes step ST12 to step 5T1.
3, and here from the reactive power value △O before turning on/off the power factor improvement capacitor stored in the temporary area 90, the operating time setting value after turning on/off this power factor improvement capacitor is calculated. The reactive power value A when the time indicated by J: has elapsed is subtracted from F, and this subtraction result (power factor improvement amount X) is stored in the RAM.

Next, in step ST1/I, the CPU 18 checks whether the value of the power factor improvement amount Then, it is checked whether the value of this power factor improvement ftX is greater than or equal to "5" (or another preset value).

If X≧5, the CPU 18 determines that the power factor optimization capacitor has been turned on and off normally, and branches from step 5T15 to step 5T16, where the delay timer counter area 93 and , comparison request flag area 94, and then proceed to the next process.

Further, in the step 5T14, the value of the power factor improvement amount X is lQJ+ or negative, or the value of the power factor improvement amount
If T15 is X5, CPU18
determines that the power factor correction capacitor is not turned on and off normally, and performs these steps 5T14 and ST.
15, the process branches to step 5T17, where the one that was turned on this time among the on/off output relays 81a to 81h is turned off.

Next, in step 5T18, the CPU 18 disables the use of the closing/cutting output relay that was turned on this time, and from now on,
The use of the power factor improvement capacitor corresponding to this on/off output relay is prohibited, and at step 5T19, the abnormality alarm output relay 86 of the output section 12 is turned on to output an abnormality alarm.

Thereafter, the CPU 18 proceeds from step 5T19 to step 5T16, where it clears the delay timer counter area 93 and comparison request flag area 94, and then proceeds to the next process.

In this way, in this embodiment, in the power factor correction process, the power factor before the power factor correction capacitor is turned on is compared with the power factor after the power factor correction capacitor is turned on, and the power factor correction capacitor itself is
Alternatively, since it is determined whether the control part of the power factor correction capacitor is malfunctioning, it is possible to detect whether the power factor correction capacitor is turned on or off without using the contacts of the auxiliary relay. This prevents noise from entering the automatic power factor adjustment device through the contacts of the auxiliary relay, and
It is possible to prevent malfunctions of the equipment.

In addition, in this embodiment, if the power factor is not improved even after the power factor correction capacitor is turned on, it is determined that the power factor correction capacitor itself or the control part of the power factor correction capacitor is malfunctioning. Since this power factor correction capacitor is not used, even if one of the power factor correction capacitors fails, appropriate power factor control can be performed and the failed power factor correction capacitor can be replaced. This can prevent punctures.

(Effects of the Invention) As explained above, according to the present invention, it is possible to detect whether the power factor correction capacitor is turned on or off without using the contacts of the auxiliary relay, and thereby the power factor correction capacitor is correctly connected. You can judge whether it is working or not.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the automatic power factor adjustment device according to the present invention, Fig. 2 is a schematic diagram showing an example of a memory map of the same embodiment, and Figs. 3 (A) and (B) are respectively the same implementation. FIG. 4 is a flowchart illustrating an exemplary operation, and a block diagram illustrating an example of a conventional automatic power factor adjustment device. 18...Storage unit, comparison unit, determination unit (CPU), 22.
...Electric power system. Agent Patent attorney Tetsuji Iwa (and 1 other person) Figure 3 (
A) The 7-eyed pilgrim and others go to the library.

Claims (1)

[Claims] Automatic power factor adjustment equipment that measures the power factor of the power system and adjusts the power factor by inserting or disconnecting a power factor improving capacitor based on the measurement results. , a storage section that stores the power factor before disconnection, and a comparison section that compares the power factor stored in this storage section with the power factor after the power factor improvement capacitor is connected or disconnected. , and a determination section that determines the quality of the power factor improvement capacitor portion based on the comparison result of the comparison section.