JPS63257422A - Automatic power factor regulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention measures the power factor of a power system and, based on the measurement results, connects or disconnects a power factor correction capacitor to improve the power factor. The present invention relates to an automatic power factor adjustment device.

(Prior Art) As a device for adjusting the power factor of an electric power system, an automatic power factor adjustment device is conventionally known.

This device calculates the power of the power system based on a load current output from a voltage transformer installed in the power system and a line voltage output from a voltage transformer installed in the power system. After determining the line voltage, power factor, and reactive power values, compare the line voltage, power factor, and reactive power values with each preset value, and if the phase is lagging, add a power factor correction capacitor. The phase is advanced, and when the phase is advanced, the power factor correction capacitor is shut off and the phase is delayed.

(Problem to be Solved by the Invention) However, in such conventional automatic power factor adjustment devices, when the power factor of the power system is lagging, a power factor correction capacitor is inserted, but in this case, this power factor correction The power factor correction capacitor sometimes becomes half-wave connected due to failure of the power factor correction capacitor or the triac that controls the power factor correction capacitor.

In addition, in such conventional automatic power factor adjustment devices, if the load current drops below the specified value while the power factor correction capacitor is connected to the power grid, the power factor and reactive power cannot be controlled. , the line voltage of the power system could rise, damaging other equipment connected to the same system.

In view of the above circumstances, the present invention provides a power factor improvement capacitor,
When this power factor correction capacitor becomes half-wave connected due to a failure of the triac, etc. that controls this power factor correction capacitor, this can be detected and the use of this power factor correction capacitor prohibited or disabled. It is an object of the present invention to provide an automatic power factor adjustment device that can make notifications.

(Means for Solving the Problems) In order to solve the above problems, the automatic power factor adjustment device according to the present invention measures the power factor of the power system and installs a power factor correction capacitor based on the measurement result. In an automatic power factor adjustment device that adjusts the power factor by turning on and off, the power factor number R capacitor is turned on and off based on the line voltage and load current of the power system. After the power factor improvement capacitor is turned on by the cutoff control unit and the cutoff control unit, the line voltage value of the power system is compared with a preset overvoltage value, and this overvoltage set value is determined. The present invention is characterized in that it includes a determination unit that determines that the power factor correction capacitor that has been turned on this time is abnormal when the line voltage value is greater than or equal to a predetermined time.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an automatic power factor adjustment device according to the present invention.

The automatic power factor adjustment device shown in this figure includes a voltage input section 15,
The power supply section 23, the current input section 16, the phase difference pulse generation section 17, and the central processing unit]! I! It is equipped with a CPU 18, an operating condition setting section 19, a display section 20, and an output section 21. In addition to controlling the on/off of the power factor correction capacitor (omitted), the power factor correction capacitor and its control circuit are inspected to see if they are malfunctioning, and if they are found to be malfunctioning, the power factor correction capacitor is prohibited from use. do.

The voltage input section 15 includes an over-input protection circuit 31 that limits the voltage signal output from the transformer 30 provided in the power system 22 to a certain value or less to protect a subsequent circuit, and an over-input protection circuit 31 that protects the subsequent circuit. A transformer 32 that transforms the output, an over-input protection circuit 33 that limits the voltage detection signal output from the transformer 32 below a certain value to protect the subsequent circuit, and the output of the over-input protection circuit 33 is connected to a CPLJ. The converter 30 generates a voltage detection signal (N pressure detection value D) based on the output of the transformer 30, and supplies this to an analog input terminal of the CPU 15.

Further, the power supply unit 23 includes a transformer 35 that transforms the output of the over-input protection circuit 31, and a constant voltage circuit 36 that generates a power supply voltage of a predetermined value from the output of the transformer 35. The power supply voltage obtained by this constant voltage circuit 36 is supplied to each part of the circuit.

The rri current input section 16 also includes an insulating transformer 38 that transforms the output (current signal) of a current transformer 37 provided in the power supply system 22, and a constant il current detection signal output from this transformer 38. The current transformer 37 is provided with an over-input protection circuit 39 that protects the subsequent stage circuit by limiting the output voltage to below the current transformer 37; A current detection signal is generated based on the output of the CPtJ18, and is supplied to the analog input terminal of the CPtJ18.

Further, the phase difference pulse generating section 17 includes the over-input protection circuit 3.
a phase pulse generation circuit 41 that amplifies the output of No. 3 at a high amplification factor to generate a phase signal (rectangular wave signal) of the voltage detection signal;
It is equipped with a phase pulse generation circuit 42 that amplifies the outputs of the three over-input protection circuits at a high amplification factor to generate a phase signal (rectangular wave signal) of the current detection signal. Supplied to a separate terminal.

Further, the operating condition setting section 19 includes a function selection setting circuit 50,
Leading reactive power setting circuit 51 and lagging reactive power setting circuit 5
2, a closing/cutting operation time setting circuit 53, a CT ratio setting circuit 54, a display setting circuit 55, and a PT ratio setting circuit 56.
, a 4-control group setting circuit 57 , an overcurrent setting circuit 58 ,
The multi-values set in each of the function selection setting circuit 50 to overvoltage setting circuit 59 are read by the CPLI 18 at any time.

In this case, the function selection setting circuit 50 is 100V/200V
It is equipped with a changeover switch and a single-phase/three-phase changeover switch, which are operated when setting the set conditions for this device.

Further, the leading reactive power setting circuit 51 includes a setter (for example, a thumb, low-return switch, etc.) for setting the allowable value of the voltage and current flowing in the power system 22 on the leading phase side. Operated when setting tolerances.

Furthermore, the delayed reactive power setting circuit 52 includes a setter (for example, a thumb rotary switch, etc.) for setting the allowable values of the voltage and current flowing through the power system 22 on the delayed phase side. Operated when setting tolerances.

In addition, the closing/cutting operation time setting circuit 53 is equipped with a setter such as a thumb rotary switch, and this setter allows the power factor improvement to be performed after the conditions for closing and cutting off the power factor correction capacitor are established. The dull time between turning on and cutting off the capacitor is set.

Further, the CT ratio setting circuit 54 is equipped with a setter such as a thumb rotary switch, and the current transformer 3 is connected to this setter.
Level conversion circuit 40 by setting the current conversion ratio of 7.
The ratio between the value of the current detection signal outputted by the CPU 18 and the load current value of the power system 22 is taught to the CPU 18.

The display setting circuit 55 also includes a setter (for example, a thumb/lower switch) for setting which of each set value or each measured value is displayed, and by operating this setter, The types of set values and the types of measured values displayed on the display section 20 change.

Further, the PT ratio setting circuit 56 is equipped with a setter such as a thumb rotary switch, and this setter is connected to the transformer 3.
By setting a transformation ratio of 0, the level conversion circuit 34
The CPU 18 is taught the ratio between the value of the voltage detection signal output by the CPU 18 and the line voltage value of the power system 22.

Further, the control group setting circuit 57 is equipped with a setting device such as a thumb rotary switch, and by operating this setting device, the device can be operated in automatic power factor correction mode.
It can also be operated in manual power factor correction mode.

Further, by operating this stabilizer, a specific power factor correction capacitor can be turned on (or cut off) in advance.

In addition, the overcurrent setting circuit 58 is equipped with a setting device such as a thumb rotary switch, and by operating this setting device, a reference value for determining whether an overcurrent is flowing in the power system 22 is set. is input.

In addition, the overvoltage setting circuit 59 is equipped with a setter such as a thumb rotary switch, and by operating this setter, a reference value (overvoltage setting The value C) is input.

The display section 20 also includes a capacitor input state display circuit 60, a reactive power state display circuit 61, a display element group 63, and a display element drive circuit 62, and supplies display data and display signals from the CPU 18. When this occurs, each lamp or display element is turned on or off in response to this.

In this case, the capacitor input state display circuit 60
It is equipped with eight lamps 64a to 64h that turn on/off in response to a lighting signal and a lights-out signal from the PU 18, and by lighting these lamps 64a to 64h, the power factor correction capacitor that is currently connected is displayed. .

Further, the reactive power status display circuit 61 has an advance display lamp 65.
, a proper indicator lamp 66, and a delay indicator lamp 67, which lights the advance indicator lamp 65 when the CPU 18 supplies the advance signal, and lights the delay indicator lamp 65 when the CPU 18 supplies the delay signal. Turn on the lamp 67. Further, when a proper signal is supplied from the CPU 18, the proper display lamp 66 is turned on. This displays the current phase state of the power system 22.

Furthermore, the display element drive circuit 62 is configured to generate an advance display signal, an R-reduction display signal, and a segment drive signal based on the output of the CPU 18, and each of these The signal is supplied to the display element group 63.

The display element group 63 includes a lead display element 70 that lights up when the lead display signal is supplied, a delay display element 71 that lights up when the delay display signal is supplied, and a segment drive signal that is supplied with the lead display element 70 that lights up when the lead display signal is supplied. At this time, the device is equipped with three "7" segment indicating elements 72a to 72c that display the numerical value indicated by this segment drive signal, and these advance display elements 70 to "7" segment indicating elements 72C control the function selection setting circuits 50 to Setting values set in the CT ratio setting circuit 54, PT ratio setting circuit 56 to five overvoltage setting circuits, and values specified by the display setting circuit 55 among the measured values are displayed.

The output unit 21 also includes an output LED drive circuit 73 that outputs a closing drive signal and a cutoff drive signal based on the output of the CPU 18, and a power factor improvement based on the output of this output LED drive circuit 73. triac control circuits 74a and 74b for controlling the triac (path shown in the figure) for turning on and cutting off the capacitor (in this embodiment, "2"bank); and an overcurrent relay 84;
This overcurrent relay 84 is activated based on the output of the CPU 18.
, an overcurrent relay drive circuit 83 that drives an abnormality alarm output relay 86 , and an abnormality alarm output relay drive circuit 85 that drives this abnormality alarm output relay 86 based on the output of the CPU 18 . The circuits 74a, 74b and the relays 84, 86 are driven to turn on/off each power factor correction capacitor bank, output an overcurrent contact signal, and output an abnormality alarm contact signal.

In this case, each triac @ control circuit 74a174b is
When the closing drive signal is outputted from the ED drive circuit 73, the closing side photocoupler 75a, 75b takes in the signal and insulates it and supplies it to the subsequent circuit, and the output LED drive circuit 73 drives the closing drive signal. When a signal is output, cut-off side photocoupler 76a, 76b captures the signal, insulates it, and supplies it to a subsequent circuit;
When the closing drive signal is supplied from the closing side photocoupler 75a, 75b, a trigger signal synchronized with the zero cross of the power system 22 is generated to turn on the triac, and the blocking side photocoupler 76a, 76
a zero-cross trigger output circuit 77 that stops generating the trigger signal when a *off drive signal is supplied;
A surge absorption circuit 78 that absorbs surge noise generated when turning on/off the triac, and a resistor 79.
It is equipped with

The CPLJ18 also includes a microprocessor with an analog input terminal, a ROM in which programs and various constant data for this microprocessor are stored, a RAM that serves as a work area for the microprocessor, and a circuit between the microprocessor and the circuit. It is equipped with various interfaces to connect each part.

In this case, as shown in FIG.
A control group input order storage area 87 stores the bank number of the power factor improvement capacitor to be input next (control group input order data A), and a control group input order storage area 87 where the bank number of the power factor improvement capacitor to be input this time (control group input order data A) is stored. A control group closing state storage area 88 in which state data B) is stored, an overvoltage setting value storage area 89 in which an overvoltage setting value C is stored, a voltage detection value storage area 90 in which a voltage detection value is stored, A voltage confirmation request flag area 91 where a voltage confirmation request flag E necessary to confirm the voltage before and after applying the rate improvement capacitor is set, and a current undercurrent flag F which is set when the detected current falls below the starting current setting value. There are provided an undercurrent flag area 92 in which the current is set, and a delay timer counter area 93 used when measuring the delay time G.

When the power factor improving condenser is turned on and off, the CPU 18 operates as described below.

First, in the process of turning on and cutting off the power factor improving capacitor, the CPU 18 reads out each setting value from the operating condition setting section 19 and stores them in the corresponding area of the RAM.

Further, in parallel with this operation, the CPU 18 calculates the power factor value ψ based on the difference between the respective phase signals output from the phase difference pulse generation section 17, and uses this power factor value ψ and the output from the voltage input section 15. The value of the detected voltage detection signal (voltage detection value D)
and the value of the current detection signal output from the current input section 16, and calculate the reactive power value α based on the power factor value ψ and the reactive power value α. Introducing 74a and 74b (Mataha,
(blocking).

When connecting a power factor improving capacitor to the power system 22, step ST1 of the flowchart in FIG.
The control group input order data A stored in the control input order storage area 87 of the RAM is read out and temporarily stored, and among the triac control circuits 74a and 74b,
A power factor correction capacitor is connected to the power system 22 by outputting a power-on drive signal to the one designated by the control group power-on order data A.

Next, in step ST2, the CPU 18 calculates the bank number of the power factor improvement capacitor to be applied next, and stores this calculation result (υ control group application order data A) in the control application order storage area 87. After, step S
At T3, in the ill 111 group input state storage area 88,
The bank number of the power factor improvement capacitor that was turned on this time (control group plug-in state data B) is stored.

Next, in step ST4, the CPU 18 sets the voltage confirmation request flag E in the voltage confirmation request flag area 91, and then compares the current detected voltage value obtained by the voltage input section 15 in step ST5 with the overvoltage value. Compare it with the overvoltage setting value C stored in the correct setting planting storage area 89,
If D<C, it is determined that the voltage of the power system 22 has not increased abnormally, this process is ended, and the process proceeds to the next process.

Further, in step ST5, if D≧C, CP
U18 determines that the line voltage of the power system 22 has increased abnormally and sets the delay timer counter area 93.
The increment operation of the delay time Q is started, and the process branches from step ST5 to step ST6.

Then, in step ST6, the CPIJ 18 reads the delay time G@ from the delay timer counter area 93, and determines whether the value of the delay time G exceeds a predetermined value (for example, 01" seconds). If this is not exceeded, it is determined that it is not time to judge the voltage, this process is ended, and the process proceeds to the next process.

Further, in step ST6, if the value of the previous two delay times G exceeds a predetermined value, the CPU 18 branches from this step ST6 to step ST7, where the voltage confirmation request is sent to the voltage confirmation request flag area 91. Check whether flag E is set.

If this voltage confirmation request flag E is set, the CPU 18 determines that the voltage has increased due to the power factor correction capacitor being turned on, and this step ST7
The flow branches to step ST8, where control group input order data 8 indicating the power factor improvement capacitor input this time is prevented from being stored in the control X1 group input order storage area 87, and an abnormality alarm is issued at step ST9. Output relay 8
Turn on 6 to output an abnormality alarm.

Next, in step ST10, the CPU 18 outputs a cutoff signal to the triac control circuits 74a and 74b that have been inserted this time to disconnect the power factor correction capacitor that has been inserted this time from the power system 22, and then carries out this process. Finish and proceed to the next process.

Also, in step ST7, the voltage confirmation request flag area 9
If voltage confirmation request flag E is not set to 1,
The CPU 18 determines that the voltage increase is not due to the addition of the power factor correction capacitor, and executes this step ST7.
The process branches to step 5T11, where it is checked whether the current undercurrent flag F is set in the current undercurrent flag area 92.

Then, if this current undercurrent flag F is set,
The CPU 18 determines that it is now time to start, ends this process, and proceeds to the next process.

In addition, in step ST11, the current under-current flag area 92
If the current undercurrent flag F is not set, the CPU
18 is from this step ST11 to the step 5TI
Branch to O and perform the operations described above.

As described above, in this embodiment, after the power factor correction capacitor is turned on, the voltage of the power system 22 is monitored, and when this voltage rises abnormally, it is determined that the power factor correction capacitor that has been turned on this time is abnormal. It was determined that this power factor correction capacitor was used! ! Since the power factor correction capacitor is disconnected, when the power factor correction capacitor becomes half-wave connected due to a failure of the power factor correction capacitor or the triac, etc. that controls this power factor correction capacitor, this power factor correction capacitor can be disconnected. It is possible to prohibit or notify the use of capacitors.

(Effects of the Invention) As explained above, according to the present invention, the power factor correction capacitor becomes half-wave connected due to failure of the power factor correction capacitor or the triac, etc. that controls the power factor correction capacitor. In some cases, this can be detected and the use of this power factor correction capacitor can be prohibited or notified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the automatic power factor adjustment device according to the present invention, FIG. 2 is a schematic diagram showing an example of a memory map of the same embodiment, and FIG. 3 is a flowchart showing an example of the operation of the same embodiment. be. 15... Voltage input section, 16... Current input section, 18.
... Closing/cutting control section, determination section (CPU), 22...
power system. Agent Patent attorney Tetsuji Iwao (1 other person) Figure 2

Claims (1)

[Claims] In an automatic power factor adjustment device that measures the power factor of an electric power system and adjusts the power factor by turning on or disconnecting a power factor correction capacitor based on the measurement result, the line voltage and load of the electric power system are adjusted. a power-on/shut-off control unit that turns on and off the power factor correction capacitor based on the current;
After the power factor correction capacitor is turned on by this on/off control section, the line voltage value of the power system is compared with a preset overvoltage value, and the overvoltage setting value is 1. An automatic power factor adjustment device comprising: a determination unit that determines that the power factor correction capacitor that is currently connected is abnormal when the voltage between the power supply and the power supply is large for a predetermined period of time or more.