JPS63228927A - Automatic power factor regulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention measures the power factor of a power system and, based on the measurement results, connects or disconnects a power factor correction capacitor to improve the power factor. The present invention relates to an automatic power factor adjustment device.

(Prior art) An automatic power factor adjustment device that measures the power factor of an electric power system and adjusts the power factor by connecting or disconnecting a power factor correction capacitor based on the measurement result. A power factor detection circuit or a reactive power detection circuit detects the power based on the load current output from the connected voltage transformer and the line voltage output from the voltage transformer connected to the power system. The system measures the power factor and reactive power of the system, and adjusts the power factor by turning on or cutting off a power factor correction capacitor based on the measurement results.

In addition, in such a system, an overcurrent detection circuit measures the load current value of the power system, and
Based on this measurement result, it is determined whether the lances 1 to 10 provided as power sources for the power system are overloaded, and when they are overloaded, an alarm relay is activated to notify the user of this. ing.

(Problems to be Solved by the Invention) However, with such conventional automatic power factor adjustment devices, even if a transformer overload alarm is output, the transformer overload cannot be immediately resolved. There's a problem.

Furthermore, the provision of the overcurrent detection circuit increases the size of the device and increases the cost.

Furthermore, the number of parts required for the circuit configuration increases, resulting in a decrease in life and reliability.

In view of the above circumstances, it is an object of the present invention to provide an automatic power factor adjustment device that can reduce the load on the transformer when the transformer becomes overloaded without increasing the number of parts.

(Means for Solving the Problems) In order to solve the above problems, the automatic power factor adjustment device according to the present invention measures the power factor of the power system and installs a power factor correction capacitor based on the measurement result. In an automatic power factor adjustment device that adjusts the power factor by turning on, turning on, and disconnecting, an input section that takes in the voltage and current of the power system and generates a power system voltage value signal and a power system current value signal; , an overcurrent state determination section that determines whether the power system is in an overcurrent state based on a power system current value signal from the input section; When it is determined that this power In order to reduce the value of the grid current value signal, turn on a power factor correction power supply,
It is characterized by being equipped with a closing/cutting control section that turns on and off.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an automatic power factor adjustment device according to the present invention.

The automatic power factor adjustment device shown in this figure includes a voltage input section 15,
It includes a power supply section 23, a current input section 16, a phase difference pulse generation section 17, a central processing unit <CPU> 18, an operating condition setting section 19, a display section 20, and an output section 21,
The power factor improvement capacitor (shown in the diagram) is controlled to be turned on and off so that the power factor of the power system 22 falls within a predetermined range, and when the power system 22 becomes overloaded, this is alleviated as much as possible. Turn on or cut off the power factor correction capacitor as required.

The voltage input section 15 includes an over-input protection circuit 31 that limits the voltage signal output from the transformer 30 provided in the power system 22 to a certain value or less to protect a subsequent circuit, and an over-input protection circuit 31 that protects the subsequent circuit. A transformer 32 that transforms the output, an over-input protection circuit 33 that limits the voltage detection signal output from the transformer 32 to below a certain value to protect the subsequent circuit, and the output of the over-input protection circuit 33 is connected to a CPtJ. The voltage detection signal is generated based on the output of the transformer 30, and is supplied to the analog input terminal of the CPU 15.

Further, the power supply unit 23 includes a transformer 35 that transforms the output of the over-input protection circuit 31, and a constant voltage circuit 36 that generates a power supply voltage of a predetermined value from the output of the transformer 35. The power supply voltage obtained by this constant voltage circuit 36 is supplied to each part of the circuit.

The current input unit 16 also includes an insulation transformer 38 that transforms the output (current signal) of a current transformer 37 provided in the power system 22, and a current detection signal output from the transformer 38 to a constant value. An over-input protection circuit 39 protects the subsequent circuit by limiting the output to CP
It is equipped with a level conversion circuit 40 that lowers the input level to the input level of the current transformer 37, generates a current detection signal based on the output of the current transformer 37, and supplies this to the analog input terminal of the CPU 18.

Further, the phase difference pulse generating section 17 includes the over-input protection circuit 3.
a phase pulse generation circuit 41 that amplifies the output of the three over-input protection circuits with a high amplification factor to generate a phase signal (rectangular wave signal) of the voltage detection signal; A phase pulse generation circuit 42 that generates a phase signal (rectangular wave signal) of the current detection signal is provided, and each of these phase signals is supplied to each separate terminal of the CPU 18.

Further, the operating condition setting section 19 includes a function selection setting circuit 50,
Leading reactive power setting circuit 51 and lagging reactive power setting circuit 5
2, a closing/cutting operation time setting circuit 53, a CT ratio setting circuit 54, a display setting circuit 55, and a PT ratio setting circuit 56.
, a control group setting circuit 57 , and an overcurrent setting circuit 58 . The eight values set in each of the function selection setting circuit 50 to overcurrent setting circuit 58 are read by the CPU 18 at any time.

In this case, the function selection setting circuit 50 is 100V/200V
It is equipped with a changeover switch and a single-phase/three-phase changeover switch, which are operated to establish the set conditions for this device.

The setting circuit 51 includes a setting device (for example, a thumb rotary switch, ), which is operated when setting the tolerance value on the leading phase side.

Furthermore, the delayed reactive power setting circuit 52 includes a setter (for example, a thumb rotary switch, etc.) for setting the allowable values of the voltage and current flowing through the power system 22 on the delayed phase side. Operated when setting tolerances.

In addition, the closing/cutting operation time setting circuit 53 is equipped with a setter such as a thumb rotary switch, and after the setting conditions for turning on and shutting off the power factor correction capacitor are established, the power factor correction capacitor is actually operated. The dull time between turning on and turning off the capacitor is set.

Furthermore, the CT ratio setting circuit 54 is equipped with a setting device such as a rim/[]-tary switch, and the current transformation ratio of the current transformer 37 is set by this setting device. and the value of the current detection signal output by the power system 22.
The ratio between the load current value and the load current value is taught to the CPU 18.

The display setting circuit 55 also includes a setting device (for example, a thumb rotary switch, etc.) for setting which of each setting value and each measured value is displayed, and by operating this setting device, The types of set values and the types of measured values displayed on the display section 20 change.

Further, the PT ratio setting circuit 56 is equipped with a setter such as a thumb rotary switch, and this setter is connected to the transformer 3.
By setting a transformation ratio of 0, the level conversion circuit 34
The ratio between the value of the voltage detection signal outputted by the CPU and the line voltage value of the Mino J system 22 is taught to the Cpuis.

Further, the control group setting circuit 57 is equipped with a setting device such as a thumb rotary switch, and by operating this setting device, the device can be operated in automatic power factor correction mode.
It can also be operated in manual power factor correction mode.

Further, by operating this regulator, a specific power factor correction capacitor can be turned on (or cut off).

In addition, the overcurrent setting circuit 58 is equipped with a setting device such as a thumb rotary switch, and by operating this setting device, a reference value is set when determining whether or not an overcurrent is flowing in the power system 22. (Overcurrent setting value C) is input.

The display unit 20 also includes a capacitor input state display circuit 60, a reactive power state display circuit 61, a display element group 63, and a display element group drive circuit 62, and the CPU 18
When display data and display signals are supplied from the controller, each lamp or display element is turned on or off in response to the display data or display signal.

In this case, ] the capacitor input state display circuit 0 is
It is equipped with eight lamps 64a to 64h that turn on/off according to the lighting signal and the lights-out signal from the PU 18, and by lighting these lamps 54a to 64h, the current
Displays the installed power factor correction capacitor.

Further, the reactive power status display circuit 61 has an advance display lamp 65.
, a propriety indicator lamp 66, and a delay indicator lamp 67, which lights the advance indicator lamp 65 when the advance signal is supplied from the CPU 18;
Further, when a delay signal is supplied, the delay display lamp 67 is turned on. Further, when a proper signal is supplied from the CPU 18, the proper display lamp 66 is turned on. This displays the current phase state of the power system 22.

The display element group drive circuit 62 is configured to generate an advance display signal, a delay display signal, and a segment drive signal based on the output of the CPU 18. Display element group 63 for each signal
supply to.

The display element group 63 includes a lead display element 70 that lights up when the lead display signal is supplied, a delay display element 71 that lights up when the delay display signal is supplied, and a lead display element 71 that lights up when the delay display signal is supplied, and a display element 71 that is supplied with the segment drive signal. 117, which displays the numerical value indicated by this segment drive signal when
T+ segment display elements 728 to 72G are provided, and function selection setting circuit 5O-CT ratio setting circuit 54, PT ratio setting circuit 56 to overcurrent setting circuit 5 are provided with T+ segment display elements 728 to 72G.
8 and the values specified by the display setting circuit 55 among the measured values are displayed.

The output section 21 also includes eight closing/cutting output relays 81a.
A group of closing/cutting output relays 82 having a power output of ~81h, a closing/cutting output relay drive circuit 80 that drives the group of closing/cutting output relays 82 based on the output of the CPU 18, an overcurrent relay 84, and a An overcurrent relay drive circuit 83 that drives the overcurrent relay 84 based on the output, an abnormality alarm output relay 86, and the CPU 18.
It is equipped with an abnormal alarm output relay drive circuit 85 that drives this abnormal alarm output relay 86 based on the output of , and drives each of these relays 81a to 81h, 84°86 to output each bank drive signal, Outputs an overcurrent contact signal or an abnormality alarm contact signal.

The CPU 18 also includes a microprocessor with an analog input terminal, a ROM in which programs and various constant data for the microprocessor are stored, a RAM that serves as a work area for the microprocessor, and a connection between the microprocessor and each part of the circuit. It is equipped with various interfaces for connecting.

In this case, a part of the RAM includes a closing flag area 87 where a closing flag A necessary for closing the power factor improving capacitor is set, as shown in FIG. A cutoff flag area 88 in which cutoff flag B necessary for this purpose is set, and overcurrent setting value C
The overcurrent setting value storage area 89 stores the overcurrent setting value, the current value storage area 90 stores the current value obtained by the measurement operation, and the reactive power value (detected reactive power value E) obtained by the detection operation is stored. A detected reactive power value storage area 91 is stored, a leading reactive power setting value storage area 92 is stored, and a leading reactive power setting value storage area 92 is stored, and an operation prohibition necessary to prohibit the turning on and turning off of the power factor correction capacitor. An operation prohibition flag area 93 where a flag G is set, a temporary storage area 94 where measurement connections, calculation results, etc. are temporarily stored, and a current value Do before turning on or cutting off the power factor correction capacitor. A comparison request flag area 95 is provided in which a comparison request flag K necessary for comparing the current value after turning on and cutting off is set.

In the overcurrent relay, this CPU 18 operates as described below.

First, before starting this overcurrent process, the CPU 18 reads out each setting value from the operating condition setting section 19 and stores them in the corresponding area of the RAM.

Further, in parallel with this operation, the CPU 18 calculates the power factor value ψ based on the difference between the respective phase signals output from the phase difference pulse generating section 17, and stores it in the RAM.
The reactive power value (detected After determining the reactive power value E), these current values and the detected reactive power value E are stored in the current value storage area 90 and the detected reactive power value storage area 91 of the RAM.

When the overcurrent process is started, the CPU 18 selects the current value stored in the current value storage area 90 and the overcurrent value stored in the overcurrent setting value storage area 89 in step ST1 of the flowchart shown in FIG. The current setting value C is read and compared, and if D<C, it is determined that the power system 22 is not in an overcurrent state, and the process branches from step ST1 to step ST2, where the operation prohibition flag is set. The operation prohibition flag G in area 93 is reset.

After that, in step ST3, the CPU 18 checks whether the comparison request flag K is set to 1 to 1 in the comparison request flag area 95, and if it is not set to 1 to 1, the CPU 18 checks whether or not the comparison request flag K is set to 1 to 1 in the comparison request flag area 95. It is determined that there is no need to turn on or cut off, and this overcurrent processing is ended to proceed to the next processing.

Further, if D≧C in step ST1, the CPU 18 determines that the transformer supplying power to the power system 22 is in an overload state, branches from step STI to step ST4, and flags an operation prohibition flag. It is checked whether the operation prohibition flag G is set in area 93.

If this is set, the CPU 18 determines that the overload condition of the transformer could not be improved in the previous overcurrent processing, and performs step ST.
5, the process branches to step ST9.

Further, in step ST4, if the operation prohibition flag G is not set, the CPU 18 determines that there is room to improve the overload condition of the lances 1 to 1 by supplying the power factor improving capacitor υ, and performs step ST4. The process branches to step S]-5, where the power factor value ψ stored in the RAM is read out, and it is checked whether this is a delayed phase.

If this power factor value ψ is a delayed phase, the CPU 18 branches from step ST5 to step ST6, where it transfers the current value stored in the current value storage area 90 to the temporary storage area 94. , after storing this as the current value DO, the input flag area 8 is stored in step ST7.
7 and sets the closing flag A to turn on the necessary ones among the closing/cutting relays 81a to 81b of the output section 21.

Next, the CPtJ 18 sets the comparison request flag K in the comparison request flag area 95 in step ST8, and then
In step ST9, the overcurrent relay 86 is turned on to output an overcurrent alarm.

Thereafter, the cpuis proceeds to step ST3, where it checks whether the comparison request flag K is set in the comparison request flag area 95.

In this case, in step ST8, the comparison request flag K
is set, the CPU 18 executes this step S.
The process branches from T3 to step ST11, where the current value D output from the electric power saw unit 16, that is, the value of the current detection signal after the power factor correction capacitor is turned on (
The current value D) is compared with the current value Do stored in the temporary storage area 94 before the power factor correction capacitor is turned on.

Then, if D<Do, it is determined that the overload condition of the transformer has been improved by introducing the power factor improving capacitor this time, and this process is ended, and the process proceeds to the next process.

Also, in this step 5T11, if D≧DO,
The CPU 18 judges that the overload condition of the transformer has not been improved even if the power factor improving capacitor is turned on this time, and branches from this step ST11 to step 5T12, where a cutoff flag is set in the cutoff flag area 88. Set B to shut off the power factor correction capacitor that was inserted this time.

Thereafter, in step 5T13, the CPU i s sets the operation prohibition flag G in the operation prohibition flag area 93, then ends this overcurrent process and proceeds to the next process.

Further, if the power factor value ψ stored in the RAM is a leading phase in step ST5, the CPU 18 branches from this step ST5 to step 5T14, where the detected reactive power value stored in the detected reactive power value storage area 91 is The reactive power value E and the advanced reactive power set value F stored in the advanced reactive power set value storage area 92 are read out and compared.

Then, if E<F, the CPU 18 determines that there is room to improve the overload condition of the transformer by introducing a power factor improving capacitor, and in this step 5
The process branches from T14 to step ST6, and the above-described operations are performed.

Moreover, in this step 5T14, if E≦F,
The CPU 18 determines that it is no longer possible to input the power factor improvement capacitor, and performs step 5T1.
The process branches from 711 to step ST9, and the above-described operations are performed.

As described above, in this embodiment, when the transformer supplying power to the power system is in an overload state, there is room to improve the overload state of the transformer by turning on a power factor improving capacitor. Check if
If there is room for improvement, install a power factor improvement capacitor.

If the overload condition of the transformer is improved by turning on this power factor correction capacitor, then this power factor correction capacitor is left on, and if it is not improved, the power applied this time is Since the rate improvement capacitor is cut off, the load on the transformer can be reduced when the transformer becomes overloaded without increasing the number of components.

(Effects of the Invention) As described above, according to the present invention, when the transformer becomes overloaded, the load on the transformer can be reduced without increasing the number of parts.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an automatic power factor adjustment device according to the present invention, FIG. 2 is a schematic diagram showing an example of a memory map of the same embodiment, and FIG. 3 is a flowchart showing an example of the operation of the same embodiment. be. 15... Input section (voltage input section), 16... Input section (
current input unit), 18... overcurrent state determination unit, closing/cutting control unit (CPU), 22... power system. S''・ Figure 2 = 1N Kaisho 63-228 ri 27 (7) Previous 5J!, Rift et al.
5T4y N sTs Scattered side N Y 5T14 Y, &, + decoration 1, okay? 7 lags K ST 8 Output 7 lags ST9 - T3. =6.2baV

Claims (1)

[Claims] In an automatic power factor adjustment device that measures the power factor of an electric power system and adjusts the power factor by turning on or disconnecting a power factor improvement capacitor based on the measurement result, the voltage and current of the electric power system are adjusted. an input section that receives and generates a power system voltage value signal and a power system current value signal; and an overcurrent that determines whether the power system is in an overcurrent condition based on the power system current value signal from the input section. a state determination unit, and when the overcurrent state determination unit determines that the power system is in an overcurrent state, turning on a power factor correction capacitor;
Based on the power system current value signal before shutoff and the power system current value signal after turning on and shutting off the power factor correction capacitor, the power factor correction capacitor is set so that the value of the power system current value signal becomes small. An automatic power factor adjustment device characterized by being equipped with a closing/cutting control section that turns on or shuts off a capacitor.