JPS6322679B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multiplex transmission system.

FIG. 1 shows a schematic block diagram of a time division multiplex transmission system, and FIG. 2 shows the same transmission signals. 1 is the main control section, and this main control section 1 outputs a start pulse.
SP, address data AD, control data
A transmission signal 2 consisting of one channel including CD and return waiting pulse RP is cyclically transmitted to terminal devices 4 _{1 .} . . via a transmission signal line 3. Terminal 4 ₁
Each has its own address, and if the address data AD of the received transmission signal 2 match, the control data CD of that channel is output at the timing of the load control output signal CP, and the monitoring data based on the monitoring input AP is output. It has a function of returning the signal as a return signal to the main control unit 1 during the period of the return waiting pulse RP. In the figure, numeral 5 is a load drive unit operated by the load control output signal CP, and numeral 6 is a controlled load.

Here, FIG. 3 shows a schematic block diagram of the terminal device 4, and FIG. 4 shows a schematic time chart of its operation. In the terminal device 4, the pulse width of the transmission signal 2 shown in FIG. 4a is counted by the pulse count section 8 using the basic clock (FIG. 4b) of the basic clock oscillation section 7 which oscillates at a high level, and the count value is subjected to logical processing. The section 9 discriminates various signal data. Then, according to the count value, data is loaded into the address data discrimination unit 10 and the control data register 11, and when the preset address and address data AD match, the monitoring input AP
The monitoring input return processing unit 12 outputs the return signal as a return signal as shown in FIG. 4c according to the return waiting pulse count value. Also, when the start pulse SP is detected by the pulse count value, the control data is
The control data output latch section 13 outputs a latch output corresponding to CD as shown in FIG. 4 d, and the count value logic processing section 9 outputs a load control output signal CP as shown in FIG. 5 and controls the load 6.
FIG. 5 shows a circuit diagram of the load driving section 5. The load control output signal CP is defined by the pulse width of the start pulse SP and return waiting pulse CP, and is input from the pulse width changing unit 14 that can change the output signal width by counting pulses exceeding a certain count value. The load control output signals are output as shown in b to e in the figure for the transmission signal system shown in Fig. 6a.
CP will be changed. That is, the pulse width is changed depending on the type of load drive unit 5 such as the latching relay _Ry , thereby improving the efficiency of load drive. For example, transmission system noise ns is added to the return waiting pulse RP.
is superimposed as shown in Fig. 7a, the count value is reset by the noise ns, and if normal, the load control signals shown in Fig. 7b and c become as shown in Fig. 7d and e, respectively. A phenomenon occurred in which the pulse width became shorter than the set width, and therefore, there was a drawback that the drive of the load 6 could not be satisfied.

The present invention has been made in view of the above-mentioned drawbacks.
The purpose of this invention is to provide a time division multiplex transmission system that solves malfunctions of load control output signals of terminal equipment due to noise in the transmission system.

The present invention will be explained below with reference to Examples.

FIG. 8 shows a schematic block diagram of an embodiment, in which when the transmission signal 2 is input to the input of the terminal 4 and the load control output signal CP is output, the switching circuit 15 is operated during this period. Contact 15
a is inverted, the transmission signal line 3 is connected to the input end of the terminal device 4 via the integration circuit 16, and the transmission signal 2 is inputted via the integration circuit 16.

FIG. 9 is an operation time chart similar to the above. The operation of the embodiment circuit will be explained using this time chart. In other words, after the address matches, the load control output signal CP width is the start pulse SP, return waiting pulse
The RP count value is determined by the number of times it is obtained,
The data signals in between are completely unrelated. Therefore, for example, even if the return signal sent back in the current mode becomes noise ns and is superimposed on the return waiting pulse RP as shown in FIG. 9a, it can be absorbed by the integrating circuit 16 as shown in FIG. 9b. At this time, if the start pulse SP and return waiting pulse RP maintain the required count width, the load control output signal CP width can be obtained normally as shown in FIG. 9c.

FIG. 10 shows a specific circuit diagram of one embodiment, in which a switching circuit 15 is constituted by a relay R _y ' whose transistor Tr is turned on and excited by the load control output signal CP, and whose relay contacts Contact 1
5a.

FIG. 11 is a specific circuit diagram of another embodiment of the present invention, which includes an integrating circuit 16 and a transistor.
A parallel circuit with Tr ₂ is inserted between the terminal device 4 and the transmission signal line 3, and the transistor Tr ₃ , which is turned off by the load control output signal CP, turns off the transistor Tr ₂ .
The transmission signal 2 is input to the terminal device 4 via the integrating circuit 16.

FIG. 12 shows another embodiment circuit of the present invention, which circuit includes two analog switches 17a, 17
b, and when the drive control output signal is not output, the second
The analog switch 17b is turned on to input the transmission signal 2 to the terminal device 4 via the second analog switch 17b, and when the drive control output signal is output, the first analog switch 17a is turned on.
The transmission signal 2 is input to the terminal device 4 via the first analog switch 17a and the integrating circuit 16.

Since the present invention is configured as described above, the transmission signal can be integrated with the load control output signal, and even if noise is added to the transmission system, it can be completely absorbed and the load can be driven normally.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of the time division multiplex transmission system, Fig. 2 is a time chart of the same transmission signal, Fig. 3 is a circuit block diagram of the terminal device shown above, and Figs. 4 a to e are time charts of the same above. , Fig. 5 is a specific circuit diagram of the load driving section same as above, Fig. 6 a to e is an operation time chart when changing the width of the load control output signal as above, and Fig. 7 a to e is a diagram of the load control output signal as above. Malfunction time chart due to noise; FIG. 8 is a circuit block diagram of an embodiment of the present invention; FIGS. 9 a to c
is a time chart for explaining the operation of the same as above, FIG. 10 is a specific circuit diagram of the main part of the same as above, FIG. 11 is a specific circuit diagram of main part of another embodiment of the same as above, and FIG. 1 is the main control section, 2 is the transmission signal, 3 is the transmission signal line, 4 is the terminal, 6 is the load, SP is the start pulse, AD is the address data, and CD is the control. data, RP is the return waiting pulse, AP is the monitoring input, and CP is the load control output signal.

Claims (1)

[Claims] 1. A main control section, a terminal device having load control and input monitoring functions, and a transmission signal line connecting the main control section and the terminal device, and a start pulse, address data, etc. , control data, and a transmission signal consisting of a return waiting pulse is transmitted to the terminal device via a transmission signal line by time division multiplexing, and the output width of the terminal device is defined by the width of the start pulse and the width of the return waiting pulse. A load control output signal for controlling the load is output, and when the received address data matches the self address, the control data is taken in, and the load is controlled with the load control output signal based on the control data. In a time division multiplex transmission system that returns the monitoring input state connected to the terminal device to the main control unit within the pulse period, the transmission signal from the transmission signal line is connected to the integrator circuit during the same period as the output period of the load control output signal. A time division multiplex transmission system characterized by input to a terminal device via 2. The integration circuit is connected between a transmission signal line and a terminal device via a relay contact of a relay driven by the load control output signal. time division multiplex transmission system. 3. An integrating circuit is connected between the transmission signal line and the terminal device, and a switching transistor is connected in parallel to the integrating circuit, so that the switching transistor is turned off by the load control output signal of the terminal device. A time division multiplex transmission system according to claim 1, characterized in that: 4. Connecting an integrating circuit between the transmission signal line and the terminal device via a first analog switch, and connecting a second analog switch in parallel to the series circuit of the first analog switch and the integrating circuit, 1st
2. The time division multiplex transmission system according to claim 1, wherein the second analog switch is turned on during the output period of the load control output signal, and the second analog switch is turned off.