JP3282278B2 - Communications system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex communication system having a power saving mode for reducing a load on a battery when mounted on an automobile.

[0002]

2. Description of the Related Art As a conventional communication system of this kind, there is, for example, an in-vehicle multiplex communication system shown in FIGS. The slave station 310 is a terminal station subordinate to the master station 300, and the slave station 310 is accessed from the master station 300 via the communication line 318, receives transmission data from the master station 300, and based on the received data. Determine the action. The power saving mode is realized by a sleep operation in which the operation of each oscillation circuit or the like is suspended in the master station or slave station, and the master station 300 has a transmission right and a control right to execute and cancel sleep. ing.

On the other hand, when the master station 300 and the slave station 310 are in a sleep operation, the slave station 310 transmits a wake-up pulse requesting cancellation of the sleep operation when an input change occurs in the slave station, and When the station 300 receives the wake-up pulse, the station 300 cancels the sleep operation.

First, the configuration of the master station will be described. Master station 300
Is provided with a reception buffer 301 for receiving a pulse signal which is data from the communication line 318.
1 converts the received pulse signal into a logic value of a logic circuit. The receiving buffer 301 is provided with buffer resistors R2 and R3. A fixed bias is applied to the receiving buffer 301 so that the receiving buffer 301 does not malfunction when the master station 300 and the slave station 310 are not transmitting. Is to be stabilized.

[0005] The received data input via the receiving buffer 301 is held in a transmission / reception register 303. The transmission / reception register 303 holds transmission data at the time of transmission. The three-state transmission buffer 302
The logic value data from the transmission / reception register 303 is converted into a voltage value and transmitted to the communication line 318.

Further, a pulse detection circuit 306 composed of a mono-multi circuit is provided, receives the received data from the reception buffer 301, detects a wake-up pulse emitted from the slave station 310, and outputs a detection output pulse. This detection output pulse includes a resistor R1 and a capacitor C1.
The pulse width is set by the time constant of

[0007] The latch circuit 307 is
6 is used as a trigger signal to latch received data from the receiving buffer 301, detect the pulse width of the wake-up pulse, and
08 to output a wake-up pulse to notify the input of a wake-up pulse. In addition, the latch circuit 307
Instructs the oscillation circuit 305 to temporarily resume the oscillation operation via the OR gate 320. Oscillation circuit 30
5 outputs a clock of a predetermined cycle based on the oscillator 309.

The control unit 304 has a function of controlling the transmission / reception operation and determining whether to execute or cancel the sleep operation. The control unit 304 receives an operation clock from the oscillation circuit 305 and issues a stop signal from the control unit 304. Oscillation circuit 30
5 has a function of temporarily stopping the oscillation operation.

The counter 308 counts the wake-up detection signal, receives the wake-up detection signal a predetermined number of times for noise elimination, and outputs a count-up signal to the control unit 304. The counter 308 is provided with a timer 317, which monitors the cycle of the received wake-up detection signal. If the wake-up detection signal cycle is longer than a predetermined time, the counter 308 is sent to the counter 308 via the OR gate 330. Apply a reset.

Next, in the slave station 310, a reception buffer 311 having functions corresponding to those of the master station, buffer resistors R4 and R5, and a transmission buffer 312 are provided for input / output with the communication line. . Further, a pulse generation circuit 314 of a mono-multi circuit for generating a wake-up pulse and a command determination circuit 313 are provided.

The reception data input via the reception buffer 311 is input to a command determination circuit 313. When the command determination circuit receives a command frame instructing execution of a sleep operation, the command determination circuit 313 receives an input trigger signal of the pulse generation circuit 314. Of the latch circuit 315 that latches the wake-up pulse is released. The pulse width of the wake-up pulse of the pulse generation circuit 314 is set by the time constant of the resistor R6 and the capacitor C2, and the pulse cycle is set by the time constant of the resistor R7 and the capacitor C3.

An input change detection circuit 316 is provided to detect a change in the state of the external switch 327 connected to the slave station, and when the state of the external switch 327 changes, the latch circuit 315 is latched. , Causing the pulse generation circuit 314 to output a wake-up pulse. The wake-up pulse from the pulse generation circuit 314 is transmitted from the transmission buffer to the communication line via 312.

The operation from the execution of the power saving mode in the above configuration to the release of the power saving mode by the wake-up pulse will be described below. First, in the master station 300, the control unit 304 sets command data for executing the power saving mode in the transmission / reception register 303, and the command data is transmitted from the transmission buffer 302 to the communication line. After that, the control unit 303 fixes the reset signal on the release side to initialize the latch circuit 307 and the counter 308, and sets the transmission buffer 302 to a high impedance state. Then, a stop signal is sent to the oscillation circuit 305 via the OR gate 330 to stop the oscillation operation, and the device enters a sleep state.

The slave station 310 receives command data input via the communication line 318 into the reception buffer 311, and the command determination circuit 313 determines the command data. When it is determined that the command data requires execution of the power saving mode, the sleep state is set, the clear signal of the latch circuit 315 is released by the output of the command determination circuit, and the detection signal of the state change of the external switch 327 can be latched. State.

The input change detection circuit 316 is connected to the external switch 3
27, the latch circuit 315 holds the change of the switch, causes the pulse generation circuit 314 to output a wake-up pulse, and outputs the wake-up pulse.
The pulse signal is transmitted to the communication line via the communication line 2.

When the master station 300 receives the wake-up pulse in the reception buffer 301, the pulse detection circuit 306
Supplies a trigger signal to the latch circuit 307. The latch circuit 307 latches the wake-up pulse in response to the trigger signal, and upon detecting the wake-up pulse, causes the oscillation circuit 305 to resume its oscillating operation and sends a wake-up detection signal to the control unit 304 and the counter 308. The oscillation circuit 305 supplies a clock to the control unit 304 after the oscillation operation is stabilized.

The control unit 304 resets the latch circuit 307 and prepares for detection of a wake-up detection signal after two pulses. The counter 308 repeats counting every time a wakeup detection signal after two pulses is detected,
After counting the predetermined number of times, the control unit 304 outputs a count-up signal and releases the sleep state. Control unit 3
In step 04, after releasing the sleep state of the master station, command data for instructing release of the sleep state of the slave station is set in the transmission / reception register 303 and transmitted from the transmission buffer 302 to the slave station via the communication line.

[0018]

In such a conventional multiplex communication system, the latch circuit 307 needs to be initialized in order to detect the wake-up detection signal after the second pulse as described above. However, since the control unit cannot operate until the oscillation operation of the oscillation circuit is stabilized, the latch circuit cannot be initialized during the oscillation operation stabilization wait time, and the second wake-up pulse is received after the oscillation operation is stabilized. Must be set to That is, the cycle of the wake-up pulse must be lengthened so that the relationship between the oscillation stabilization time and the wake-up pulse cycle is as follows: oscillation stabilization time <wake-up pulse cycle. It is necessary to increase the time constant of the generating circuit.

As a result, the resistance value and the capacitance of the capacitor that determine the time constant become large, which increases the cost and, in particular, the accuracy of the wake-up pulse period due to changes in temperature, humidity, and the like as the use environment for vehicles. This can lead to reliability problems, such as difficulty in maintenance.

If the sleep state is canceled by receiving only one pulse of the wake-up detection signal,
Although the above problem does not occur, if a short-circuit failure between the communication line and the power supply line occurs, the power supply voltage appears immediately after the transmission buffer is set to the high impedance state due to sleep, and this is erroneously detected as the wake-up detection signal. Detected,
Execution of the power saving mode may not be practically possible. Therefore, the present invention has been made in view of the above-mentioned conventional problems,
A communication system that enables the cycle of the wake-up pulse to be set without being affected by the oscillation operation stabilization time at the master station, eliminates cost increase and reliability reduction, and reliably implements the power saving mode. The purpose is to provide.

[0021]

According to the present invention, a master station and a slave station connected by a communication line each have an oscillation circuit, and the oscillation operation of the oscillation circuit is stopped to save power. Having a power saving mode for power saving, the master station has means for instructing execution and cancellation of the power saving mode,
In a communication system including a unit in which the slave station issues a wake-up pulse and requests the master station to cancel the power saving mode, the master station includes a timer that counts a predetermined count after the execution instruction of the power saving mode, and a wake-up pulse. A counter for counting and outputting a count-up signal of one pulse and a plurality of pulses; and a selector for selecting the count-up signal in accordance with a state of the timer, and instructing execution and cancellation of the power saving mode. Means for continuing the oscillation of the oscillation circuit of the master station until the timer has completed counting up, and when a wake-up pulse is received during counting of the timer, the power-saving mode is set based on the count-up signal of the plurality of pulses. Wake-up pulse after timer means counts up When receiving is assumed that is configured to direct the release of the 1 pulse count-up signal based power saving mode.

According to a second aspect of the present invention, there is provided a power saving mode in which a master station and a slave station connected by a communication line each have an oscillation circuit, and the oscillation operation of the oscillation circuit is stopped to save power. Wherein the master station has means for instructing execution and cancellation of the power saving mode, and the slave station has a means for issuing a wake-up pulse to request the master station to cancel the power saving mode. The station has a dummy signal generating means for generating a dummy signal, and a changeover switch, the means for instructing execution and cancellation of the power saving mode, when receiving a wake-up pulse,
First, a dummy signal is sent from the dummy signal generating means,
Thereafter, a communication signal for instructing cancellation of the power saving mode is transmitted by switching a changeover switch.

[0023]

According to a first aspect of the present invention, there is provided a timer for counting a predetermined count after a power saving mode execution command is issued to a master station, and a counter for outputting a wake-up pulse count-up signal of one pulse and a plurality of pulses, and the timer is provided with a timer. During the counting, the oscillation of the oscillation circuit of the master station is continued, and when a wake-up pulse is received during this period, a plurality of wake-up pulses are counted and then the power saving mode is released. As a result, even if a noise pulse enters immediately after the execution of the power saving mode due to a communication line failure or the like, the noise pulse is discriminated and removed, and the oscillation circuit is still oscillating for a normal wake-up pulse. The cycle of the plurality of pulses can be set to an arbitrary short time without requiring a stabilization time such as when resuming oscillation.
In addition, it is reliably detected.

According to the second aspect of the present invention, a dummy signal generating means for generating a dummy signal is provided in the master station. When instructing the cancellation of the power saving mode, the dummy signal is first transmitted, and then the cancellation of the power saving mode is performed. Since the communication signal for commanding is transmitted, the slave station stabilizes the oscillation operation of the oscillation circuit while receiving the dummy signal, and the communication signal for commanding cancellation thereafter is reliably decoded without misunderstanding.

[0025]

FIG. 1 shows an embodiment of the present invention. Master station 1
00 and the slave station 113 exchange data via the communication line 112. The wake-up pulse generation function of the slave station is the same as that of the conventional example shown in FIG. The master station has a reception buffer 10
1, pulse detection circuit 106, resistor R1, capacitor C
1. The transmission / reception register 103, the latch circuit 107, the transmission buffer 102, the oscillation circuit 105, the oscillator 109, and the first timer 117 are the reception buffer 301, the pulse detection circuit 306, the resistor R1, and the capacitor C1 in the conventional example of FIG. , Transmission / reception register 303, latch circuit 30
7, transmission buffer 302, oscillation circuit 305, oscillator 30
9 and a timer 317.

On the other hand, the difference is that the counter 108 has two types of count-up outputs, and the two types of count-up signals are switched by the selector 111 and input to the control unit 104. That is, the counter 108 counts the wake-up detection signal from the latch circuit 107 and outputs a count-up signal indicating detection of each of 1 count and n count.

Further, a second timer 110 is provided,
After transmitting the command data for executing the power saving mode, the control unit 104 starts the operation. This is provided to delay the time from when the command data is transmitted to when the oscillation of the oscillation circuit 105 is stopped.

The control unit 104 controls the transmission and reception and the execution and cancellation of the power saving mode as in the conventional example. However, when executing the power saving mode, the second timer 110 is started after the command data is transmitted. Until the timer counts up, the oscillation operation of the oscillation circuit 105 is continued, while the transmission buffer 102 is set in a high impedance state to be in a standby state for receiving a wake-up pulse.

When a wake-up pulse is received during the counting operation of the second timer 110, the control unit 104 stops the counting operation of the second timer. With this stop, the output of the second timer 110 is set to the selector 111
Is switched to the n count side, and the control unit 104 releases the sleep state in response to the n count-up signals of the counter 108. Thus, the reception of the plurality of wake-up pulses is confirmed, and the power saving mode is released.

On the other hand, when the first timer 117 counts up without receiving the second wake-up pulse, its output resets the counter 108 via the OR gate 130. Further, the control unit 104 cancels the stop of the stopped second timer 110 and enters a state of waiting for the reception of a wake-up pulse. Second timer 110
Receives a wake-up pulse after counting up, the selector 111 connects the one-count output of the counter 108 to the control unit 104. As a result, the control unit 104 releases the sleep state with one wake-up pulse.

The operation of the embodiment configured as described above is as follows.
This will be described with reference to the timing chart of FIG. Master station 10
Command data 407 instructing execution of the sleep state from 0, and the wake-up pulse 40 from the slave station 113.
8 and 409 appear on the communication line in the order shown in FIG. (D) and (e) of the figure show the operating states of the second timer 110 and the first timer 117. (G) shows the oscillation state of the oscillation circuit 105.

After the master station transmits the command data 407, the second timer 110 is started and the initial state 416 is set.
Then, the operation enters a count operation, and enters a wake-up detection signal reception waiting state 417. Master station pulse detection circuit 10
6 outputs an input detection signal 411 when the first wake-up pulse 408 is input, as shown in FIG. With this output as a trigger, the wake-up detection signal 412 as shown in FIG.

When the first wake-up pulse 408 is received during the wake-up detection signal reception waiting state 417 of the second timer 110, the wake-up detection signal 412 is sent from the latch circuit 107 to the control unit 104. The signal is input to the counter 108 and the first timer 117, the first timer 117 is started, and the process proceeds to the count operation 421 in (e).

The counter 108 enters the count 1 state 424 in FIG. 7F, and at the same time, the control unit 104 sets the second timer 110 to the count stop state 418 in FIG. Over,
The initial state 432 shown in FIG. 3C is set to prepare for receiving the next wake-up pulse. At this time, the selector 11
1 switches to the n-count side.

Thereafter, the second wake-up pulse 40
When 9 is received, the wake-up detection signal 413 is again output from the latch circuit 107 based on the input detection signal 414. The counter value of the counter 108 becomes the count 2 state 425 in (f). When it is set in advance to output a count-up signal with the count number n = 2, the control unit 104 receives the count-up signal and puts the control unit 104 into a sleep state. To cancel.

Here, the latch circuit 107 and the second timer 110 are reset to the initial states 433 and 431, respectively, as shown in FIGS.
As shown in (a), command data 410 for instructing release of the sleep state is transmitted. During this time, as shown in (g), the oscillating operation of the oscillating circuit 105 is continued without stopping from the execution to the cancellation of the power saving mode.

Next, the timing chart of FIG. 3 shows the execution of the power saving mode when a short circuit occurs in the communication line and the release of the power saving mode while the oscillation operation is stopped after the second timer 110 times out. The operation is shown. 3A shows a communication signal on the communication line, FIG. 3B shows an output signal of the pulse detection circuit 106, FIG. 3C shows a wake-up detection signal from the latch circuit 107, and FIG. d) shows the operation state of the second timer,
(E) shows the operation state of the first timer 117, (f) shows the count state of the counter 108, and (g) shows the oscillation state of the oscillation circuit 105.

Command data 501 shown in (a) of FIG.
Is transmitted, the control unit 103 sets the second timer 110
Is started, and the timer enters a count operation from an initial state as shown in (d), and enters a wake-up detection signal reception waiting state 502. Here, the transmission / reception register 1
03 sets the transmission buffer 102 to a high impedance state.

As described above, when the communication line 112 has a short-circuit failure to the power supply line, an abnormal voltage 503 appears on the communication line 112 as shown in FIG. When the abnormal voltage 503 is detected,
The input detection signal 50 shown in FIG.
4 and the wake-up detection signal 505 is output from the latch circuit 107 as shown in FIG. As a result, the first timer 117 is started, and the flow proceeds to the counting operation 507 in (e).

However, since the second wake-up pulse is not received during the count operation 507 of the first timer, the count-up of the first timer 117
After 10, the second timer 110 is again activated as shown in (d).
Is restarted, and the counter 108 is also reset to the count 0 state 513 as shown in FIG. Then, when the second timer 110 enters the count-up state 525, the control unit outputs a stop signal via the OR gate 120, and the oscillation circuit 105 enters the oscillation operation stop state 514 of FIG. Becomes

Next, a case where a wake-up pulse is received from a slave station after oscillation stops in the master station will be described. When the first wake-up pulse 517 in (a) is received in the oscillation operation stop state 514 of the oscillation circuit in (g), the wake-up detection signal 519 in (c) is output from the latch circuit 107 in the same manner as described above. Is done.
As a result, the oscillation circuit 105 enters the oscillation restart state 521 shown in FIG.

Then, when the oscillation stable state 522 is reached, the control section 104 operates to reset the latch circuit 107 to the initial state 524 of (c). At this time, the second timer 110 is in the count-up state 52 of (d).
5, the selector 111 selects one of the counters 108.
The count output is connected to the control unit 104. This allows
Release of the sleep state is determined only by the first wake-up pulse, and after resetting the second timer 110 to the initial state 526, the command data 527 for instructing the release of the sleep state is child as shown in (a). It is transmitted to the station 113. The second timer 110 constitutes the timer of the invention.

As described above, according to this embodiment, the circuit for continuing the oscillation operation for a predetermined time after transmitting the command for executing the sleep state and the circuit for switching the count number of the wake-up detection signal are used as the parent. By providing the station, the wake-up period can be set without being affected by the oscillation stabilization time of the master station, and the sleep state can be reliably executed even if a communication line fails.

Next, FIG. 4 shows details of a receiving section including a command determination circuit for receiving a sleep state execution command from the master station in the slave station. A communication signal from the communication line enters the changeover switch 212 via a path from the reception buffer 201 via the flip-flop 210 and a direct path from the reception buffer 201, and is then input to the differentiating circuit 213.

The output of the differentiating circuit 213 is a transistor 215 connected in series with a resistor R8 between a power supply and ground.
Input to the gate. Resistor R7 and transistor 2
The connection point 15 is connected to the inverter 217, and the output of the inverter 217 is input to the CPU (not shown) as the carrier sensor signal CS. A capacitor C7 is interposed between the input terminal of the inverter 217 and the ground.

A decoder 221 for receiving a communication signal from the receiving buffer 201 is provided, and a clock is supplied from the oscillation circuit 211 to the flip-flop 210 and the decoder 221. The decoder 221 includes an external actuator 22
4 and an output latch 223 connected thereto, and a sleep state execution release signal holding circuit 222 is connected.

The decoder 221 decodes and extracts the command data of the execution and release commands of the sleep state included in the communication signal, outputs a sleep execution or ON or a sleep release or OFF signal to the holding circuit 222, and outputs other data. Output to the output latch 223. The holding circuit 222 is configured by combining a NAND circuit, and receives the sleep ON or sleep O
The FF signal is held to be a sleep signal and output to the CPU.

The changeover switch 212 is switched by the sleep signal, and the sleep signal is turned on.
, The receiving buffer 201 is directly connected to the differentiating circuit 213, and the sleep signal is set to sleep OFF.
, The flip-flop 210 is connected to the differentiating circuit 213. The sleep signal and the carrier sensor signal inverted by the inverter 219 are represented by A
When the output of the AND circuit is input to the oscillating circuit 211 and the sleep signal is in the sleep ON state and the carrier sensor signal indicates no input signal, the oscillating circuit 211 is used as a stop signal. Stop the oscillation operation of

When a communication signal is input during execution of the sleep state, the signal enters the transistor 215 from the reception buffer directly through the differentiating circuit 213. Transistor 215
Turns on and the capacitor C7 discharges, the inverter 2
The carrier sensor signal from 17 becomes H level. As a result, the stop signal from the AND circuit 220 disappears, and the oscillation operation of the oscillation circuit 211 is restarted. Among them, the decoder 221 and the holding circuit 222 constitute the above-described command determination circuit.

In the above configuration, when a communication signal including command data for releasing the sleep state is received from the master station, the communication signal is decoded by the decoder 221. This decoder operates with the clock from the oscillation circuit 211. If the oscillation circuit 211 is not stable, the decoder itself cannot operate stably. As described above, the oscillation circuit 211 is in the sleep ON state and is stopped when there is no input signal. Therefore, even if the oscillation circuit 211 starts the oscillation operation due to the change of the carrier sensor signal, the master station is not operated while the oscillation is not stable. There is a possibility that the communication signal transmitted from is decoded by the decoder.

FIG. 5 shows a second embodiment in which the risk of misreading at the slave station is eliminated at the master station. That is, the master station is further provided with a dummy pulse generation circuit 231 and a changeover switch 232 in addition to the configuration of FIG. Except for the control unit 104 ', the same components as those in FIG. 1 are not shown. Dummy pulse generation circuit 2
31 and the changeover switch 232 are connected to the control unit 10
4 'is connected to receive a control command. The changeover switch 232 is inserted between the transmission / reception register 103 and the dummy pulse generation circuit 231 and the transmission buffer 102, and switches the output of the transmission / reception register 103 and the dummy pulse generation circuit 231 to the transmission buffer 102 according to the control command. input.

When the master station receives the wake-up pulse from the slave station and the control section 104 'decides to release the sleep state, the master station first transmits the output of the dummy pulse generation circuit 231 from the transmission buffer to the communication line. Then, after that, a switching command is issued to the changeover switch 232 to cause the transmission / reception register 103 to transmit command data for instructing cancellation of the sleep state.

FIG. 6 shows these timing charts. In the figure, (a) shows a communication signal transmitted on the communication line, (b) shows an input potential of the inverter 217 in the slave station, (c) shows a sleep signal from the holding circuit 222 of the slave station, and ( d) shows the operation state of the oscillation circuit 211 of the slave station. First, upon receiving command data 601 for instructing execution of the sleep state from the master station, the slave station outputs a sleep signal as indicated by 602 in (c).
When the input signal goes high, the transistor 215 turns off due to the disappearance of the input signal, and the capacitor C7 is charged.
Input potential gradually rises. When the inverter is inverted, a stop signal is generated, and the oscillation circuit 211
Is in the oscillation operation stop state 604 of (d).

When the wake-up pulse 605 is transmitted from the transmission buffer to the communication line in the sleep state of the slave station, first, the slave station receives the wake-up pulse from the reception buffer and receives the wake-up pulse 605 from the transistor 215.
Is turned on, and the inverter 21 is turned on as indicated by 606 in FIG.
7 is inverted and the carrier sense signal goes high. As a result, the stop signal from the AND circuit 220 is turned off, and the oscillation circuit 211 enters the oscillation start stage 607 of (d).

Here, in the master station, the control section 104 'first causes the output 608 of the dummy pulse generation circuit 231 to be transmitted as shown in FIG. 9A, whereby the transistor 215 of the slave station continues to be turned on. As shown in (b), the input potential of the inverter 217 does not exceed the inversion threshold value, and thus the stop signal from the AND circuit 220 continues to be off. The dummy pulse output from the dummy pulse generation circuit 231 has a frame configuration different from that of a normal communication signal as illustrated in FIG.
Is not mistaken for a communication signal.

During this time, the oscillation of the oscillation circuit 211 becomes the stable state 609 in FIG. 6D, and thereafter the master station issues the command data 6 for instructing the release of the sleep state as shown in FIG.
Send 10 This command data is already correctly decoded by the decoder because the oscillation of the oscillation circuit 211 is already in a stable state, and the sleep signal from the holding circuit 222 becomes the sleep-off L level 611. Thus, the wake-up operation is completed.

This embodiment is configured as described above. At the time of wake-up, the master station outputs a dummy signal different from the communication signal before transmitting the communication signal. The communication signal can be received in a state where the oscillation operation of the circuit is reliably stabilized, and there is an effect that highly reliable wake-up is performed.

[0058]

As described above, according to the present invention, in a communication system having a power saving mode, a timer which counts a predetermined count after a power saving mode execution command is issued to a master station,
A counter that outputs a wake-up pulse count signal of one pulse and a plurality of pulses is provided, the oscillation of the oscillation circuit of the master station is continued for a predetermined count by a timer, and a plurality of wake-up pulses are received when a wake-up pulse is received during this period. The power saving mode is canceled after counting, and the cancellation is performed by one pulse thereafter. Therefore, even if a noise pulse enters immediately after the execution command of the power saving mode due to a communication line failure or the like, it is discriminated and removed. The oscillation circuit keeps oscillating with respect to the regular wake-up pulse, so that the wake-up pulse with a short cycle can be reliably detected without being affected by the stabilization time such as when restarting oscillation. Having.

Further, a dummy signal generating means for generating a dummy signal is provided in the master station so that a dummy signal is transmitted first when instructing the release of the power saving mode, and thereafter a communication signal for instructing the release of the power saving mode is transmitted. In this configuration, the slave station stabilizes the oscillation operation of the oscillation circuit while receiving the dummy signal, so that the communication signal of the release command received thereafter is reliably decoded without erroneous recognition. This has the effect of improving reliability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the first embodiment.

FIG. 3 is a timing chart showing an operation in the first embodiment.

FIG. 4 is a diagram illustrating a receiving unit of a slave station.

FIG. 5 is a diagram showing a second embodiment.

FIG. 6 is a timing chart showing an operation in the second embodiment.

FIG. 7 is a diagram illustrating a dummy pulse signal.

FIG. 8 is a diagram showing a parent station in a conventional example.

FIG. 9 is a diagram showing a slave station of a conventional example.

[Explanation of symbols]

 Reference Signs List 100 parent station 101 reception buffer 102 transmission buffer 103 transmission / reception register 104, 104 'control unit 105 oscillation circuit 106 pulse detection circuit 107 latch circuit 108 counter 110 second timer 111 selector 112 communication line 113 slave station 117 first timer 120, 130 OR gate 201 Receive buffer 210 Flip-flop 211 Oscillator 212 Switching switch 213 Differentiator 215 Transistor 217 Inverter 219 Inverter 220 AND circuit 221 Decoder 222 Holding circuit 223 Output latch 224 Actuator 231 Dummy pulse generation circuit 232 Switching switch 300 Master station 301 Reception Buffer 302 Transmission buffer 303 Transmission / reception register 304 Control unit 305 Oscillation circuit 306 Pulse detection circuit 307 Latch circuit 308 Counter 309 Oscillator 310 Slave station 311 Receive buffer 312 Transmission buffer 313 Command determination circuit 314 Pulse generation circuit 315 Latch circuit 316 Input change detection circuit 317 Timer 318 Communication line 320 OR gate 327 External switch 330 OR gate

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-25046 (JP, A) JP-A-4-283140 (JP, A) JP-A-4-310444 (JP, A) Patent 2949998 (JP, A) B2) Patent 2988185 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 29/00

Claims (3)

(57) [Claims] 1. A master station and a slave station connected by a communication line each have an oscillation circuit, and have a power saving mode in which the oscillation operation of the oscillation circuit is stopped to save power. A communication system comprising means for instructing execution and cancellation of a power mode, and wherein the slave station issues a wake-up pulse to request the master station to cancel the power saving mode. A timer that counts a predetermined count after a mode execution command, a counter that counts the wake-up pulse and outputs a count-up signal of one pulse or a plurality of pulses, and selects the count-up signal according to the state of the timer. Means having a selector, for instructing execution and cancellation of the power saving mode,
Until the timer counts up, the oscillation of the oscillation circuit of the master station is continued, and when the wake-up pulse is received during the counting of the timer, the power saving mode is canceled based on the count-up signal of the plurality of pulses. The communication system according to claim 1, wherein when the timer means receives the wake-up pulse after the count-up, the wake-up pulse is instructed to release the power saving mode based on the one-pulse count-up signal. 2. A master station and a slave station connected by a communication line each have an oscillation circuit, and have a power saving mode in which the oscillation operation of the oscillation circuit is stopped to save power. A communication system comprising means for instructing execution and cancellation of a power mode, and wherein the slave station issues a wake-up pulse to request the master station to cancel the power saving mode, wherein the master station has a dummy signal. A dummy signal generating means for generating a signal, and means for instructing execution and cancellation of the power saving mode,
When the wake-up pulse is received, first, a dummy signal from the dummy signal generating means is transmitted, and then, a communication signal for instructing the release of the power saving mode by switching the changeover switch is transmitted, and the oscillation of the slave station is performed. A communication system configured to transmit a communication signal for instructing cancellation of the power saving mode in a state where the oscillation operation of the circuit is stable. 3. A master station and a slave station connected by a communication line each have an oscillation circuit, and the master station has a power saving mode in which the oscillation operation of the oscillation circuit is stopped to save power. A communication system comprising means for instructing execution and cancellation of a power mode, and wherein the slave station issues a wake-up pulse to request the master station to cancel the power saving mode. A timer that counts a predetermined count after a mode execution command, a counter that counts the wake-up pulse and outputs a count-up signal of one pulse or a plurality of pulses, and selects the count-up signal according to the state of the timer. A selector, a dummy signal generating means for generating a dummy signal, and a changeover switch, for executing and canceling the power saving mode. Ryosuru means,
Until the timer counts up, the oscillation of the oscillation circuit of the master station continues, and when the wake-up pulse is received during the count-up of the timer, the power-saving mode is canceled based on the count-up signal of the plurality of pulses. When the timer means receives the wake-up pulse after counting up, it issues a command to cancel the power saving mode based on the count-up signal of the one pulse, and transmits a communication signal instructing cancellation of the power saving mode. When performing the communication, the communication device is configured to first transmit a dummy signal from the dummy signal generation unit, and thereafter transmit a communication signal for instructing release of the power saving mode by switching the changeover switch. system.