JPS59193648A - Time division multiplex supervising system - Google Patents

Abstract

PURPOSE:To attain 9 high speed response by providing respectively a device generating a high-order bit of an own address data as an interruption signal to each terminal device and providing a device retrieving an interruption generator of a terminal device to a master deive based on the high-order bit of a receiving data. CONSTITUTION:An interruption signal generating circuit 5 transmits the high- order bit of the own address data as the interruption signal in synchronizing with a start pulse signal ST of the terminal device. Further, a 8-bit counter circuit 6 is reset by a start synchronizing pulse SP in synchronizing with the signal ST and constituted to count a clock CL in 100kHz. When outputs Q4-Q7 of the circuit 6 and address signals AD4-AD7 representing the high-order bit of the address data of the terminal device are coincident, an interruption pulse generating circuit 8 generates an interruption pulse. On the other hand, the master device is provided with an interruption retrieval device calling the terminal device based on the high-order bit of the received address data as the interruption signal and retrieving the interruption generator.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a time division multiplex monitoring system.

[Background technology]

Figure 1 shows the schematic structure of this type of time-division multiplex monitoring system, in which a base unit (1) and a plurality of terminal units (2) are connected via a pair of signal lines (3). In addition, a start pulse signal is sent from the main unit (1), an address data signal for individually calling each terminal unit (2), and a PIL for waiting for a return.

The called terminal device (2) sends out a transmission signal VS with a signal Fj, and sends out a return signal VB that returns monitoring data from the called terminal device (2) to the base device fl in synchronization with the return standby pulse signal. The monitoring data signal sent back to the main operation panel (11) is created based on the level or level change of the monitoring input signal. The control data signal of the load device connected to 2) is transmitted by the transmission signal VS, so that the load device can be remotely controlled.By the way, in such a monitoring system, the main device +1) is usually The terminal device (2) is called up cyclically in the same order for control and monitoring.The signal waveform and signal format of the transmission signal VS sent from the base device (1) are
The ones shown in FIG. 3 and FIG. 3 are conceivable. In other words, the transmission signal Vs sent from the base unit f1+ includes a start pulse signal ST indicating the transmission start point, a 4-position t-do signal MD for setting the signal shade, and a 4-position page for address expansion. A page data signal PD for transmitting data, an address data signal AD for transmitting 8-bit address data for calling the terminal device (2), and an 8-bit address signal AD for controlling the load device connected to the terminal device (2). A control data signal CD that transmits the control data of the pits, a checksum data signal C8 that transmits the checksum data of 4 pits that checks whether the data has been transmitted normally, and a return signal VB from the terminal device (2). The signal is formed by a return standby pulse signal -IJWP that sets the return timing of the signal, and is sequentially and cyclically transmitted to each terminal (2). This transmission signal Vs is subjected to asymmetric pulse width modulation based on a predetermined 90-degree clock, and is transmitted as a bipolar signal. The terminal circuit (4) of each terminal device (2) includes an address match determination means for comparing the address data signal AD of the transmission signal Vs with its own address set by the address setting switch (SA), and control when the addresses match. A control output means that generates a control output to control the load device (L) based on the data signal (CD), and a monitoring input signal that outputs the monitoring data signal to be returned to the main operation panel (l) during the period of the return standby pulse signal WP. It is configured as a return signal generation means that is generated based on the levels of S, ~S4. (RET) is a data output terminal to which a monitoring data signal or an address data signal is output. ) return signal V
B is returned to the main unit (il) during the period set by the return standby pulse R (WP), and a low resistance (R1) is connected between the signal line (3) by turning on the transistor (T'rρ). It is sent out as a current pulse signal. In the figure (
DB) is a diode ridge, (G) is a power supply circuit, (R
2XR3) is a resistor, CD) is a diode, and in the embodiment, the transmission signal VS for data transmission is rectified and stabilized to form a power source for the terminal circuit (4).

By the way, in such a monitoring system, the terminal device (
When the number of terminals (2) increases, the base unit (1) will control all the terminals (
2), the time required to call the terminal (2) becomes longer.
The response speed to changes in the monitoring input decreases,
This becomes a problem when high-speed response is required. Therefore, for monitoring inputs that require a high-speed response, the terminal device (2) generates an interrupt to the base unit (1) to notify R machine + 1) that there is a monitoring input or that there has been a change. I found a way to speed up the process. Figure 4 shows the basics of the conventional interrupt processing procedure. First, the terminal device (2) that requires interrupt processing due to changes in monitoring input, etc.
generates an interrupt signal consisting of one current pulse at the timing of the start pulse signal ST. The base unit (1) that detected this interrupt signal sends out a transmission signal Vs.
An interrupt polling code (hereinafter abbreviated as MDIP) is used to discover the address of the terminal device (2) that is generating the interrupt signal, and the address of the interrupt terminal device (2). Enter. MDIP transmission signal V
The operation of the terminal device (2) for s is that if the received data ignores the lower 4 pits of the address data and the upper 4 pits of the address data match, it determines that it has been called. The terminal device that issued the interrupt signal (2
) and the interrupt flag is set, the lower four pits of its own address data are sent back to the base unit (1) in return signal VB instead of monitoring data. Therefore, the base unit (1) identifies the interrupt terminal (2) by combining the upper 4 bits of the address data it sent and the lower 4 bits of the address data returned from the terminal (2). The interrupt terminal (2) can immediately monitor the t-mode signal M D and transmit the transmission signal V at -F.
s to cause the monitoring data to be returned in synchronization with the return standby pulse signal WP. Finally, the interrupt flag of the interrupt terminal (2) is reset to end the interrupt processing and return to normal monitoring and control mode.

As mentioned above, R machine (1) has multiple (
Terminal 2) consisting of 16) terminals (2): calls the group, checks the interrupt terminal (2) from among the simultaneously called terminals (2), and selects the identified interrupt terminal (2).
The terminals were immediately called up individually and the monitoring data signals were sent back, making it possible to respond quickly to a large number (256) of terminals (2). However, even in such a conventional example, when the number of terminal devices (2) increases, the time required to search for the interrupt terminal device (2) by MDIP increases, making it impossible to provide a high-speed response. For example, in the conventional example mentioned above, MDIP is required 16 times in the worst case, and if sufficient attention is not paid to the address allocation to the terminal device (2) and the signal processing software of the base device (1), the response speed will increase. There was a problem that it was not possible to speed up the process.

[Purpose of the Invention] Honmaruaki was developed in view of the above points, and its purpose is to provide a timetable multiplex monitoring system that shortens the time required to search for interrupt terminals and enables high-speed response. It is also Ω.

[Disclosure of the invention]

(Embodiment 1) FIG. 5 shows an embodiment of the present invention, in which (5) is an interrupt generating means that sends out the upper hit of its own address data as an interrupt signal in synchronization with the start pulse signal ST; This interrupt generating means (5) generates a start synchronization pulse S which is synchronized with the start pulse signal ST outputted from the terminal circuit (4) (outputted with a certain time delay from the rising edge).
The counter circuit (6) at 8 o'clock which counts the clock CL of 100KH2 which is 7 bits at P, and when the counter circuit (6) counts up (when O8 becomes 1), D Flippu 0tsu″j to stop inputting CL
(FF); Gate circuit (7) consisting of t=- and A/D circuits (A, ), and the output Q+~Q of the counter circuit (G)
, and the top hits of the address data of the terminal device (2) are displayed.
The exclusion or all path (XO,) to (XO4) generates an interrupt pulse when the
), an interrupt pulse generation circuit (8) consisting of an AND circuit (A2), and an OR circuit (9).

On the other hand, the main device (1) receives an interrupt signal (U) based on the upper pit of the address data, and calls the terminal device (2; group) to search for the interrupt generating terminal device (2). (not shown) is provided.

(Operation of Embodiment 1) First, the operation of generating damage will be explained as follows.
Now, when the terminal circuit (4) outputs the start synchronization pulse SP which is the same as the start pulse signal ST as shown in FIG. 6, the califter circuit (6) operates and the output of the counter circuit (6) Q4 /-Qy and address No. 45 AD
, ~AD7, the outputs of exclusive-OR circuits (XO,) ~ (XO4;l all become H repeats, the AND circuit (A2) output becomes H level, and the transistor (Tr, ) Turn on and start pulse signal S
TO song half section S] ゛Divided section tO which divided 1 into multiple parts ~
An interrupt consisting of a current pulse is generated at either time t or 5. The position of this interrupt pulse IP corresponds to the top four hits of the address data of the terminal (2). For example, the top four hits of the address data are (OII
In the case of IJ, an interrupt pulse IP is generated in the divided section t7 as shown in FIG. In the embodiment, the address signals AD4 to AD are the inverted data of the top four hits of the address data, and the generation position of the interrupt (response) IF is the ninth division section t7 from the front. Each division interval. ~t, the distance is 807 seconds. Next, the interrupt detection means of the base device (1) checks the position of the interrupt pulse IP based on the sending timing of the sent start pulse signal ST, thereby detecting the top four hits of the address data of the interrupt terminal device (2). can be determined, and using the top 4 hits of this address data, MDI
The address of the interrupt terminal (2) is specified by sending the transmission signal VS of P and returning the lower four pits of the address data of the interrupt terminal (2). At this time, the top four hits of the address data of the interrupt terminal (2) are transmitted to the base unit (1) as the interrupt signal IP, so the M
The interrupt terminal (2) can be identified by just sending the DIP transmission signal Vs once, and the interrupt processing operation can be performed quickly. Next, the base device (+) individually calls the specified interrupt terminal device (2), sends out the monitoring data transmission signal Vs, and receives the monitoring data returned from the interrupt terminal device (2). It fits. Next, the master unit fl sends a reset mode transmission signal Vs to the interrupt terminal (2), registers the interrupt flutter set in the latch, and ends the interrupt operation.

(Embodiment 2) FIG. 7 shows another embodiment, in which the interrupt generating stage (5a) is arranged so that the top four hits of address data are transmitted in accordance with the position and current level of the interrupt application pulse IP. In the embodiment shown in FIG. 5, an AND circuit (Aυ, a transistor ('1' r 2 ), and a resistor (R4) are added to determine the current level of the interrupt pulse IP based on the address signal AD. This is so that you can change it.

(Operation of Embodiment 2) Now, in Embodiment 2, the output Q of the sword circuit (6)
5 to Q7 and address signals AD5 to AD, the transistor Tr is turned on similarly to the previous embodiment, and the resistor (R1) is connected between the signal lines (3), and an interrupt t'' consisting of a current pulse is generated. + pulse IP is generated, and the position of the interrupt pulse IP is set based on the top eight hits of the address data of the terminal (2).

On the other hand, the transistor (Tr2) is turned on and off based on the address signal AD4, and when the output of the AND circuit (A2) is at H level and the address signal AD4 is at level ■, the AND circuit (
The AA) output goes high and turns on, and a resistor (R1) is connected between the signal lines (3) to generate an interrupt pulse IP with a large current level. For example, the upper 4 bits of the address data of terminal device (2) are (011
0), the transistor Tr1 in the division section t3
In addition, when the upper four hits of the address data are (0011), the transistor in the divided section t1 is generated. r1.1 and r2 are turned on and an interrupt pulse IP with a high current level is generated.In this case, in the R machine +1+, the upper address data of the interrupt terminal (2) is determined based on the position and current level of the interrupt pulse IP. 4 humans can be identified, and as in the previous example, MD
The interrupt terminal (2) can be identified by just sending the IP transmission signal Vs once, and the interrupt processing operation can be performed quickly.

[Effect of the Invention J As described above, the present invention connects a base unit and a plurality of terminal units via a pair of signal lines, and converts the base unit into a start pulse signal and calls each terminal unit into address data °υ゛In a time division multiplex monitoring system, a transmission signal having a return standby pulse signal (g) is sent out, and a monitoring data signal is sent back from the called terminal to the base unit in synchronization with the return standby pulse signal. , each terminal device is provided with an interrupt generating means that sends out the high-order hit of its own address data as an interrupt signal in synchronization with the start pulse signal, and the terminal device group is called based on the high-order hit of the received address data to generate an interrupt. The base unit is equipped with an interrupt search means for searching for terminals, and the upper pit of the address data of the terminal is sent as an interrupt signal, so the time required for the base unit to search for interrupt terminals is shortened. , it has the advantage of being able to respond quickly to monitoring input.

[Brief explanation of drawings]

FIG. 1(a) is a diagram showing a schematic configuration of a time-division multiplex monitoring system according to the present invention, FIG. 1(b) is a block circuit diagram of a main part of a conventional example, and FIGS. 2 to 4 show the operation of the same as above. Explanatory diagram, 5th
6 is a circuit diagram of one embodiment of the present invention, FIG. 6 is an explanatory diagram of the same operation, FIG. 7 is a circuit diagram of another embodiment, and FIG. 8 is an explanatory diagram of the same operation. (1) is the main unit, (2) is the terminal, (3) is the signal line, (6
) is an interrupt generation means. Agent Patent Attorney Ishi 1) Chief 7 Procedures Amendment (Voluntary) 1.・J<Display of 1982 Patent Application No. 67267-2, Name of the invention: Time-division multiplex monitoring system 3, Relationship with tenancy of the person making the amendments.Personal address where the patent was issued: 1048 Kadoma, Kadoma City, Osaka Prefecture. Name (58
3) Matsushita Dencho Co., Ltd. Representative Iku Kobayashi 4, Agent postal code 530 5, Date of amendment order Self-corrected as shown in the attached document Application number Japanese Patent Application No. 58-67267 No. 1, Specification of the present application, page 9 In line 18, "When they match" will be corrected to "When they are all different." 2. On page 12 of the same page, lines 5 and 6, "When they match" is corrected to "When they all differ." 3. Same as above, page 10, lines 8 to 12, “In addition,...
``Natteshi,'' will be deleted. Agent Patent Attorney Ishi 1) Choshichi

Claims (2)

[Claims] (1) Connect the base unit and multiple terminals via a pair of signal lines, and send out a transmission signal from the base unit that includes a start pulse signal, an address data signal for calling each terminal, and a pulse signal for waiting for return. In a time division multiplex monitoring system in which a monitored data signal is returned from the called terminal to the base unit in synchronization with the return standby pulse signal, the upper pit of its own address data is used as an interrupt signal to generate a start pulse signal. Each terminal device is provided with an interrupt generating means that is sent out in synchronization with the received address data, and the base device is provided with an interrupt searching device that calls a group of terminal devices based on the top hit of the received address data and searches for the terminal device that has generated the interrupt. A time-division multiplex monitoring system featuring: (2) An interrupt generating means that generates an interrupt pulse consisting of a current pulse in one of the divided sections obtained by dividing the start pulse signal section into a plurality of sections, and transmits the top seven hits of address data in correspondence with the position of the interrupt pulse. 0(8) The time division multiplex monitoring system according to claim 1 comprising 2. The time division multiplex monitoring system according to claim 1, wherein the interrupt generating means is formed so as to transmit the upper pit of the address data in response to the current level.